Analysis and Design of Wideband CMOS Transimpedance Amplifiers Using Inductive Feedback

Transcription

1 Analysis and Design f Wideband CMOS Transimpedane Amplifiers Using Indutive Feedbak Omidreza Ghasemi A Thesis In the Department Of Eletrial and Cmputer Engineering Presented in Partial Fulfillment f the Requirements Fr the Degree f Dtr f Philsphy at Cnrdia University Mntreal, Quebe, Canada April 01 Omidreza Ghasemi, 01

2 This is t ertify that the thesis prepared CONCORDIA UNIVERSITY SCHOOL OF GRADUATE STUDIES By: Entitled: Omidreza Ghasemi Analysis and Design f Wideband CMOS Transimpedane Amplifiers using Indutive Feedbak and submitted in partial fulfillment f the requirements fr the degree f DOCTOR OF PHILOSOPHY (Eletrial & Cmputer Engineering) mplies with the regulatins f the university and meets the aepted standards with respet t riginality and quality. Signed by the final examining mmittee: Dr. J. Jans Dr. G.W. Rberts Dr. A. Dlatabadi Dr. M.Z. Kabir Dr. M.O. Ahmad Dr. C. Wang Dr. Y.R. Shayan Chair External Examiner External t Prgram Examiner Examiner Examiner Administrative Supervisr Apprved by April 10, 01 Dr. J.X. Zhang, Graduate Prgram Diretr Dr. Rbin A.L. Drew, Dean Faulty f Engineering & Cmputer Siene ii

3 Abstrat Analysis and Design f Wideband CMOS Transimpedane Amplifiers Using Indutive Feedbak Omidreza Ghasemi, Ph.D. Cnrdia University, 01 Optial reeivers have an imprtant rle in high data rate wireline data mmuniatin systems. Nwadays, these reeivers have data rates f multi Gb/s. T ahieve suh high data rate in the design f ptial reeivers, all the amplifiers in the signal path need t be wideband and at the same time have minimum gain variatins in the passband. As a rule f thumb, the bandwidth f amplifiers in the ptial reeivers shuld be 70% f the data rate. The first mpnent f the ptial reeiver is phtdide whih nverts phtns reeived frm ptial fiber t urrent signals. The small urrent reeived frm the phtdide is amplified using the transimpedane amplifier (TIA) whih is ne f the main building blks in the reeiver frntend. Due t high data rate f fiber pti mmuniatin systems the bandwidth f TIAs shuld be high and it shuld satisfy gain requirements. It has been shwn that indutive feedbak tehnique is apable f extending the bandwidth f CMOS TIAs amplifiers effetively. Hwever, n mathematial analysis is available in the literature explaining this phenmenn. The main fus f this thesis is t explain mathematially the mehanism f bandwidth extensin f CMOS TIAs with indutive feedbak. iii

4 In this thesis, it is shwn mathematially that the bandwidth extensin f inverter based CMOS TIAs with indutive feedbak is due t either zer-ple anellatin r hange in the harateristis f mplex njugate ples. It is shwn that fr large phtdide apaitane fr example 150fF the phenmenn fr the bandwidth extensin is zer ple anellatin. In the ase f small phtdide apaitane fr example 50fF, the bandwidth extensin happens due t hange in the harateristis f mplex njugate ples. Finally, the zer ple anellatin using indutive feedbak methd fr mmn sure based transimpednae amplifier with resistive lad using different values f phtdide apaitanes has been analyzed. In additin t that a new 3-stage mmn sure based transimpedane amplifier using indutive feedbak tehnique is designed. The press f bandwidth extensin is shwn analytially and is nfirmed with simulatin results using well-knwn tls and tehnlgies. T shw the system level mtivatin, an eye diagram simulatin is perfrmed fr all tplgies and it is verified that bandwidth extensin des nt disturb the perfrmane. Mrever, the nept is verified based n a frequeny saled dwn disrete implementatin. In this thesis, fr inverter based CMOS TIA using phtdide apaitanes f 150fF and 50fF bandwidths f 16.7GHz and 9.7GHz are ahieved. In the ase f mmn sure based TIAs, nsidering 50fF, 100fF, 150fF phtdide apaitanes, -3dB bandwidths f 3.1GHz, 1.8GHz, and 15.8GHz are ahieved. A new three-stage TIA is prpsed whih ahieves bandwidths f 4.8GHz, 35.5GHz, and 8.5GHz fr 50fF, 100fF, 150fF phtdide apaitanes. Based n mparative analysis, it is shwn that, indutive feedbak is the mst effetive methd t extend the bandwidth f TIAs in terms f number f indutrs. iv

5 Aknwledgments I wuld like t express my sinere gratitude t my supervisr Prf. Yusef Shayan fr his invaluable enuragement during my PhD studies at Eletrial and Cmputer Engineering department at Cnrdia University. His trust and hpe in my wrk made me believe in myself and mve frward with my studies. Dr. Shayan was always there t give me supprt during tugh times. His sund visin and experiene helped me imprve bth prfessinally and persnally. I want t thank my thesis defense mmittee members: Prf. Grdn Rberts f MGill University, Prf. Dlatabadi f Mehanial Eng. department, and Drs. Kabir, Wang, and Ahmad. My speial thanks g t the external examiner f my thesis, Prf. Grdn Rberts, fr the time he tk t arefully read and evaluate my dissertatin. I am prud t have him as external examiner f this thesis. Prf. Dlatabadi als guided me in several aspets f my wrk. Many peple supprted me during years f my studies. Namely, I am grateful t Drs. Raut and Cwan fr their initial supprt f this wrk. I wuld like t als thank Dr. Kahrizi, frmer GPD f the department, fr his guidane and Dr. Asim Al-Khalili fr reading my PhD thesis prpsal. I wish t als thank Ms. Pamela Fx, PhD prgram rdinatr, fr her kind behavir and Ted Obuvihz fr keeping the neessary tls running. I am indebted t my parents fr their unnditinal enuragement thrughut my studies sine primary shl t PhD. I als thank my brthers fr their help and supprt. I wish t thank my friends in Cnrdia University fr all the heerful mments we shared. Finally, I am truly grateful t my lvely wife, fr her help and supprt during my PhD studies. Her patiene and sarifie made this thesis pssible. v

6 Dediatin This thesis is dediated t my wife, my parents, and all thse wh truly ared abut mpletin f this wrk. vi

7 Table f Cntents List f Figures ix List f Tables.. Xi List f Symbls and Abbreviatins Xii Chapter 1: Intrdutin Optial Cmmuniatin Systems 1. CMOS Transimpedane Amplifiers Literature survey and mtivatin Objetives and Cntributins Organizatin f the thesis. 10 Chapter : Bakgrund 1.1 BW extensin in TIA design 1. Shunt peaking Series peaking.. 16 vii

8 .4 PIP tehnique 17.5 Mathing indutr between the stages Indutive feedbak tehnique Cnlusin Chapter 3: Bandwidth extensin using zer ple anellatin Small signal mdel and zer ple anellatin 4 3. Simulatin results fr an illustrative example Zer-Ple Canellatin Press Frequeny respnse Eye diagram Cnlusin 35 Chapter 4: Bandwidth extensin using mplex njugate ple mpensatin Send rder system Cmplex njugate ples mpensatin Simulatin results Zer-Ple Analysis 4 viii

9 4.3. Frequeny respnse Eye diagram Estimatin f BW Extensin Rati (BWER) BWER fr large PD BWER fr small PD Cnlusin 51 Chapter 5: Wideband Cmmn Sure based TIAs Single stage mmn sure based TIA using indutive feedbak Zer-Ple Canellatin Press Frequeny respnse fr single stage CS-based TIA Three Stage Cmmn Sure based Transimpedane amplifier Nise Analysis Eye diagram Disrete frequeny saled dwn experiment Cnlusin. 83 Chapter 6: Cnlusin Cnlusins and ntributins f the thesis. 85 ix

10 6. Future wrk.. 89 Appendix A 90 Appendix B. 91 Appendix C. 9 Referenes x

11 List f Figures Fig 1.1 Optial Transmitter Blk Diagram 3 Fig 1. Optial Reeiver Blk Diagram 3 Fig.1 PD, TIA and LA 13 Fig.. shunt peaking 14 Fig.3 shunt peaking tehnique used t extend the BW by Hasan [31] 15 Fig.4 shunt peaking tehnique by Krmer [3] 16 Fig..5 Mdel f series peaking tehnique [35] 17 Fig.6 Ciruit fr series peaking implemented by Wu [35] 17 Fig..7 PIP tehnique small signal mdel [34] 18 Fig.8 Ciruit implemented by Jin and Hsu [34] 18 Fig..9 Mdel f the prpsed tehnique by Analui [38] 19 Fig..10 Ciruit implemented by Analui 0 Fig..11 Ciruit shematis f lw-vltage TIAs with indutive feedbak [39] 1 Fig. 3.1 TIA with resistive feedbak 5 Fig. 3. TIA with indutive feedbak 5 Fig. 3.3 Small signal mdel f the TIA with indutive feedbak 6 Fig 3.4 Rt-Lus f the indutive feedbak TIA 30 Fig. 3.5 Spiral Indutr Mdel 31 Fig. 3.6 Frequeny respnse f the iruit 33 Fig. 3.7 Eye diagram fr data rate f 0GHz 34 xi

12 Fig. 4.1 TIA with indutive feedbak 38 Fig. 4. Frequeny respnse f the iruit 43 Fig. 4.3 Eye diagram fr the iruit fr data rate= 40Gb/s 45 Fig. 4.4 Mathematial simulatin f transfer funtin 47 Fig. 4.5 Mathematial simulatin f transfer funtin 49 Fig.5.1 CS-TIA with resistive feedbak 55 Fig. 5. CS-TIA with indutive feedbak 55 Fig. 5.3 Small signal mdel f the CS-TIA with indutive feedbak 56 Fig. 5.4 Spiral indutr mdel used fr simulatin 63 Fig.5.5FrequenyrespnseftheCS-TIA(PD=50fF) 64 Fig.5.6FrequenyrespnseftheCS-TIA(PD=100fF) 65 Fig.5.7 Frequeny respnse f the CS-TIA (PD=150fF) 66 Fig 5.9 Frequeny respnse f the three stage TIA (PD=50fF) 69 Fig 5.10 Frequeny respnse f the three stage TIA (PD=100fF) 70 Fig 5.11 Frequeny respnse f the three stage TIA (PD=150fF) 70 Fig 5.1 Nise equivalent mdel f the CS-TIA 73 Fig 5.13 Simulated In, in with different values f Cpd and L fr ne stage CS TIA 76 Fig 5.14 Simulated In, in with different values f Cpd and L fr three stage CS TIA 77 Fig Eye diagram fr the three-stage TIA (data rate= 50Gb/s) 80 Fig Eye diagram fr the ne stage CS-TIA (data rate= 40Gb/s) 80 Fig Disrete iruit assembled and the utput 81 Fig Frequeny respnse based n disrete experiment 8 xii

13 List f Tables Table 1.1-Standard bit rates fr ptial mmuniatin Table 3.1 Ple -Zer analysis fr the iruit in Fig Table 3. Values f the parasiti elements 3 Table 3.3-AC simulatin result f the TIA 3 Table 3.4-Perfrmane f the TIA and mparisn 34 Table 4.1 Ple -Zer analysis fr the iruit 4 Table 4.-AC simulatin result f the TIA 44 Table 4.3-Perfrmane f the TIA and mparisn 44 Table 5.1 Ple -Zer analysis fr the iruit (PD=50fF) 60 Table 5. Ple -Zer analysis fr the iruit (PD=100fF) 61 Table 5.3 Ple-Zer analysis fr the iruit (PD=150fF) 6 Table 5.4 Typial Values f the parasiti elements 64 Table 5.5 AC simulatin result f the TIA (CPD=50fF) 67 Table 5.6 AC simulatin result f the TIA (CPD=100fF) 67 Table 5.7 AC simulatin result f the TIA (CPD=150fF) 67 Table 5.8 Three Stage CS based TIA with indutive feedbak (CPD=50fF) 71 Table 5.9 Three stage CS TIA with indutive feedbak (CPD=100fF) 7 Table 5.10 Three stage CS TIA with indutive feedbak (CPD=150fF) 7 Table 5.11 Summary f the results and mparisn with ther wrks 78 xiii

14 List f Symbls and Abbreviatins BW BWER In,in Cs Rs Cx Csi Rsi Z(s) CMOS VLSI SONET SDH PD TIA A DSP IC Z ZBW Bandwidth Bandwidth extensin rati Ttal input nise urrent Parasiti apaitane f substrate Parasiti Resistane f substrate Parasiti apaitane f xide Parasiti apaitane f silin Parasiti Resistane f silin Transimpedane Transfer Funtin Cmplementary Metal Oxide Semindutr Very Large Sale Integratin Synhrnus Optial Netwrk Synhrnus Digital Hierarhy Pht Dide Transimpedane amplifier mir ampere Digital Signal Pressing Integrated Ciruit transimpedane transimpedane-bandwidth-prdut xiv

15 LA OEIC PCB EMI RMS ISI BR CCVS CS CG GBW GHz CS-TIA Limiting Amplifier Opteletrni Integrated Ciruits Printed Ciruit Bard Eletrmagneti Interferene Rt-Mean Square Inter-Symbl Interferene Bit Rate Current Cntrlled Vltage Sure Cmmn Sure Cmmn Gate Gain-Bandwidth Prdut Giga Hertz Cmmn Sure based Transimpedane Amplifier xv

16 Chapter 1 Intrdutin Nwadays everybdy wants t have mmuniatin and mstly thrugh internet. By inreasing the demand f mmuniatin thrugh internet, the vlume f the data transprted in the mmuniatin system has inreased. The data rate f the glbal internet system will inrease frm tens f Gb/s t terabits per send very sn. This indiates that the bandwidth requirements will inrease by a fatr f mre than 100. Appliatins suh as virtual reality require data rates that are 10,000 times higher than urrently available nes [1],[]. Transprtatin f suh data rates requires media with lw lss and high bandwidth [3]. Amng the available medium t transfer the data, ptial fibers have the best perfrmane. Optial fibers are very mmn these days t transprt very high rate digital data. Suh high speed data rates an be transprted ver kilmeters f ptial fiber and withut signifiant lss. Nrmally lss is very lw when the signal is transmitted using light rather than eletrial signal [4]. These fibers als have the advantage f being lw st in additin t imprvement f perfrmane. In state- 1

17 f-the-art tehnlgy, fiber pti devies and systems are evidently emplyed t realize very high data rates [5]. Fiber pti mmuniatin is a slutin beause high data rates an be transmitted thrugh this high apaity able with high perfrmane [6],[7]. 1.1 Optial Cmmuniatin Systems Optial fibers are mmuniatin medium apable f prviding high rate transfer f data. This is the reasn why there is a big demand fr high-speed ptial transeivers whih nsist f data transmitters and reeivers. These systems have been implemented using slid state devies and iruits [8]. There are standard data rates fr ptial mmuniatin systems whih are shwn in Table 1.1. Table 1.1-Standard bit rates fr ptial mmuniatin SONET SDH Bit Rate OC Mbit/s OC-3 STM Mbit/s OC-1 STM Mbit/s OC-48 STM Gbit/s OC-19 STM Gbit/s OC-768 STM Gbit/s In fiber pti transmissin system, the synhrnus ptial netwrk (SONET) and synhrnus digital hierarhy (SDH) standard define a tehnlgy t arry many signals f different apaities [1],[9]. Basi transmissin bit rate OC-1 is at 51.8Mbit/s, and higher bit rates ffered by SONET/SDH are summarized in Table 1.1[5],[10]. The tw high data rate mmerial systems SONET OC-19 and OC-768 [11],[1], perate at 10 and 40Gb/s

18 respetively. The 10Gb/s transeivers have already been intrdued by a few mpanies [13]. In this respet, an extensive amunt f researh has been perfrmed t imprve the design f these systems. The 10Gb/s transeivers have been implemented using CMOS (Cmplementary Metal Oxide Semindutr) tehnlgy. Hwever, implementatin f 40Gb/s CMOS transeivers is an nging researh tpi. The reasn is that these systems have nly beme realizable in advaned tehnlgies. Figures 1.1 and 1. shw the blk diagram f the ptial transmitter and reeiver system. The transmissin f ptial data via fiber pti invlves eletrial-t-ptial nversin in the transmitter and ptial-t-eletrial nversin in the reeiver. In Fig. 1.1 whih is the ptial transmitter, data is serialized synhrnus t a lk in Tx and then ges thrugh the driver and is nverted t light using the laser dide and then delivered t the ptial fiber. Tx Data Driver Laser Dide Optial fiber Fig. 1.1 Optial Transmitter Blk Diagram Pht dide Transimpedane Amplifier Limiting Amplifier Clk and Data Revery Data Fig. 1. Optial Reeiver Blk Diagram 3

19 In Fig. 1. whih is the ptial reeiver, the data ming frm the ptial fiber is nverted t eletrial signal (urrent) using the pht dide (PD) and amplified using the transimpedane amplifier and the limiting amplifier and then revered in lk and data revery part [],[14]. In this thesis, the fus is n the transimpedane amplifier f the ptial reeiver. The light whih is traveling thrugh the fiber pti usually ges under a lt f attenuatin befre reahing the phtdide (PD) [15]. Therefre the amunt f urrent reeived by the ptial reeiver is very small. This urrent is in the range f tens f mir amperes. An ptial reeiver fr a lw-st and high-speed link must nvert this urrent t a digital signal [6],[16]. The main jb f the transimpedane amplifier is t amplify this urrent signal and prdue a vltage signal. The limiting amplifier amplifies the utput vltage f transimpedane amplifier (TIA) and prdues an aeptable vltage level t be delivered t lk and data revery part (CDR) [17]. The lk and data revery part (CDR) perfrms timing synhrnizatin and amplitude-level deisins n the input signal, whih will lead t digital data stream [7],[18]. 1. CMOS Transimpedane Amplifiers The fus f this thesis is n transimpedane amplifier (TIA) as ne f the main parts in the ptial reeiver. The jb f the transimpedane amplifier is t amplify the small urrent reeived frm the phtdide and nvert it t a vltage signal. The transimpedane amplifier des the first level f amplifiatin n the small urrent reeived frm the phtdide in the ptial reeiver. 4

20 There are imprtant parameters in the design f transimpedane amplifiers suh as bandwidth, gain, nise, pwer, and supply vltage. Sine the data rate in the ptial reeiver is high, the transimpedane amplifier (TIA) shuld have high bandwidth t avid inter symbl interferene (ISI). The input urrent t the TIA is very small and therefre the gain shuld be high enugh t be able t prdue an aeptable vltage level fr the limiting amplifier. This vltage is in the level f few mili-vlts. Sine the input urrent f TIA is very lw, in rder t ahieve high signal t nise rati, the input referred nise f TIA must be lw. Therefre, transimpedane amplifier is a wideband, high gain, and lw nise amplifier with lw pwer nsumptin and lw supply vltage. In nlusin, design f transimpedane amplifiers is a big hallenge fr analg iruit designers [8],[19]. In vltage t vltage amplifiers the figure f merit (FM) is the gain bandwidth prdut (GBW). This means that the gain is traded ff against the bandwidth. Transimpedane amplifiers are urrent t vltage amplifiers. Therefre their figure f merit is defined as transimpedane (Z) bandwidth prdut (ZBW) as ppsed t GBW. There exist different values ahieved fr the gain f the TIA. In the literature, the gain f between 40dB-Ohms and 60dB-Ohms has been reprted fr reent TIAs. Bandwidth is defined as the upper frequeny fr whih the transimpednae gain rlls ff 3dB belw its midband value. This bandwidth is alled the 3dB bandwidth r -3dB bandwidth. Bandwidth is usually determined by the ttal apaitane ntributed by the phtdide, the transimpedane amplifier and ther parasiti elements present at the ptial frnt-end. Typially the transimpedane amplifier is required t ammdate wide-band data extending frm d t high frequenies t avid inter-symbl interferene (ISI) [0]. Bit errr rate (BER) whih is the 5

21 rati f the number f errrs reeived t the ttal number f bits in the ptial system shuld be 1 less than10. T ahieve suh BER, a rule f thumb nsiders the ptimum 3-db bandwidth fr the transimpedane amplifier (TIA) t be abut /3 f the data rate. Similarly, we an say that the ptimum bandwidth fr the transimpedane amplifier is abut 70% f the bit rate [1]. Fr example fr an ptial reeiver t be emplyed in a 10Gb/s bit-rate system, we need t have at least 7GHz bandwidth fr the transimpedane amplifier. In rder t reah a data rate f 40Gb/s, the amunt f bandwidth is at least 8GHz. In this thesis the fus is n hw t ahieve high bandwidth fr transimpedane amplifiers in rder t maintain signal integrity. Traditinally, beause f the perfrmane requirements fr the TIA, the frnt-end iruitry has used III-V mpund semindutr tehnlgies. These days it has beme neessary t design the transimpedane amplifier, the limiting amplifier, and lk and data revery iruits n the same integrated iruit. High level f integratin fr these mpund semindutr tehnlgies is very stly and smetimes impssible. On the ther hand CMOS tehnlgy has the advantage f high apaity fr integratin at a very lw st. In the past deades, CMOS tehnlgy has been used t design high speed analg integrated iruits, with prviding lw-st and high perfrmane slutins []. Majrity f the analg and mixedsignal prduts and systems in tday s semindutr industry are designed and fabriated in CMOS tehnlgies. Using the CMOS transistrs and press fr fabriatin f the eletrni interfae in the ptial system allws fr integratin f high-speed iruits n single hips. This integratin an redue the pakage size, bard size, and the st f the system. The saling f reent CMOS tehnlgies at the level f nanmeter enables the fabriatin f transistrs with higher unity gain frequenies. Nwadays, due t these 6

22 harateristis, there is a great interest in implementing ptial reeivers in CMOS tehnlgy whih enables design f high speed transimpedane amplifiers [3]. 1.3 Literature survey and mtivatin Many researhers are wrking n design f varius parts f ptial reeivers. They are wrking n phtdides, ptial fibers, transimpedane amplifiers, limiting amplifiers, and lk and data revery iruits [4]. In this thesis the fus is n the transimpedane amplifiers and speifially hw t imprve their bandwidth. Several bandwidth extensin tehniques have been intrdued in the literature. Althugh indutr-less tehniques suh as apaitive peaking [5],[6], sure degeneratin [7],[8], and regulated asde [9] have been used t extend the bandwidth f transimpedane amplifiers, the indutr-based wideband transimpedane amplifiers are f great intetrest tday. T extend the bandwidth effetively, the effet f parasiti apaitanes must be redued. The effetive way t mitigate the effet f parasiti apaitanes is t use indutrs. Indutrs are very large in terms f hip area and nsumatin f large area n the hip means big st. Therefre in indutr based designs, we always lk fr less number f indutrs. Shunt peaking whih is t add an indutr t the lad f the amplifier has traditinally been used t extend the bandwidth f amplifiers. It has been used t extend the bandwidth f transimpedane amplifiers as well [30],[31],[3],[33]. Althugh this tehnique emplys ne indutr, it annt extend the bandwidth f transimpedane amplifiers by a large fatr. The indutr based tehnique f Pi type Indutive Peaking (PIP) has als been used t extend the bandwidth f TIAs [34]. This methd is using a mbinatin f three indutrs in eah stage t extend the bandwidth. Hwever, this tehnique uses a large number f indutrs whih is nt 7

23 favrable in the design f analg integrated iruits. PIP tehnique an extend the bandwidth f the transimpedane amplifiers by a large fatr. Anther tehnique in the literature is indutive series peaking [35]. This tehnique als uses large number f indutrs. Anther tehnique is putting indutr between the stages [36],[37],[38]. This tehnique uses 4 indutrs t extend the bandwidth f the transimpedane amplifier. This tehnique is apable f absrbing big amunt f phtdide apaitane and extend the bandwidth by a large fatr. Anther tehnique is indutive feedbak [39] whih is used t extend the bandwidth f CMOS transimpedane amplifiers. This tehnique has been applied t extend the bandwidth f transimpedane amplifiers intuitively in different tplgies. This tehnique is apable f extending the bandwidth f transimpedane amplifiers by a large fatr and uses nly ne indutr. Hwever, in the lierature, the mehanism f bandwidth extensin has nt been explained analytially fr transimpedane amplifers. Mtivatin f this thesis is t fill this empty gap by mathematial analysis. Als sine the thehnique has shwn a great ptential t extend the bandwidth f CMOS transimpedane amplifiers, a mtivatin exists t disver pssible new transimpedane amplfiers using this tehnique. 1.4 Objetives and Cntributins The main bjetive f this thesis is t explain mathematially the press f bandwidth extensin using indutive feedbak tehnique fr CMOS transimpedane amplifiers in different tplgies. In additin, this thesis explres the pssibilities fr prviding new iruits based n this tehnique in CMOS tehnlgy. Based n this bjetive detail ntributins f this thesis are as fllws: 8

24 Inverter based CMOS transimpedane amplifier based n indutive feedbak has been studied t explre the mehanism f bandwidth extensin in this iruit. As a result it is shwn that the mehanism is different based n different amunts f input apaitane. It is shwn that fr large phtdide apaitane fr example 150fF fr inverter based TIA with indutive feedbak, the press f bandwidth extensin is zer ple anellatin. This has been prved analytially and by extensive simulatin. It is shwn that fr small phtdide apaitane f 50fF fr inverter based TIA, indutive feedbak is apable f bandwidth extensin by mpensatin f harateristis f mplex njugate ples. This has been shwn analytially and verified by extensive simulatin. Cmmn sure based CMOS transimpedane amplifier with resistive lad using indutive feedbak has been studied. The press f zer ple anellatin fr different amunts f phtdide apaitanes has been explred in detail. This has been mpleted by extensive analytial disussin and detailed simulatins. Als the nept is verified based n a frequeny saled dwn disrete implementatin. In ntinuatin f the researh a new 3 stage CMOS transimpedane amplifer using indutive feedbak has been designed and simulated in a well-knwn CMOS tehnlgy. The effetiveness f the new iruit in extending the bandwidth f the TIA has been prved analytially and by extensive simulatin results. 9

25 In rder t shw the system perfrmane f the iruitries, fr eah struture an eye diagram has been prdued. The pen eyes prve the effetiveness f the iruitries t pass the high rate data bits and t maintain signal integrity. 1.5 Organizatin f the thesis In hapter 1, ptial reeivers and TIAs as ne f the main parts f the ptial reeivers are disussed. Then the literature survey n different methds fr ahieving high bandwidth transimpedane amplifiers is given. As a result bjetive and ntributins f the thesis are detailed. In hapter, existing tehniques in the literature t extend the bandwidth f the TIAs are detailed. Sme insight abut the bakgrund f these tehniques is given. In this hapter the fus is n tehniques using spiral indutrs t extend the bandwidth f transimpedane amplifiers. In hapter 3, the disussin f indutive feedbak tehnique using zer ple anellatin t extend the bandwidth f inverter based CMOS TIAs has been dne. The small signal analysis fr the iruit is given. The tehnique is disussed analytially. The press f zer ple anellatin based n large phtdide apaitane is shwn by extensive simulatin results. Eventually, mparisn with previus wrks is shwn in this hapter. In hapter 4, the disussin f indutive feedbak tehnique t extend the bandwidth f inverter based transimpedane amplifiers fr the ase f small phtdide apaitane (50fF) is dne. It is shwn that fr small phtdide, the hange in the harateristis f mplex njugate ples is the reasn fr press f bandwidth extensin. Simulatin results using well- 10

26 knwn tls and tehnlgies tgether with sme mparisn with ther previus wrks are shwn in this hapter. In Chapter 5, bandwidth extensin using indutive feedbak tehnique is applied fr the mmn sure-based transimpedane amplifiers. Detailed analysis fr zer ple anellatin fr different values f phtdide apaitane is shwn. Then a new three stage transimpedane amplifier is designed and the bandwidth extensin press is shwn using extensive simulatin results with well-knwn tls. In Chapter 6, nlusins and diretins fr future wrk are disussed. 11

27 Chapter Bakgrund The purpse f this hapter is t review previus wrks whih have been dne fr bandwidth extensin f transimpedane amplifiers. The hapter starts with disussin f the issues f bandwidth extensin fr TIAs. Existing indutr based tehniques t extend the bandwidth f transimpedane amplifiers are disussed in this hapter..1 BW extensin in TIA design The general struture fr the feedbak TIA is shwn in the Fig..1 in whih we an see that a vltage amplifier with a resistive feedbak an be nverted t a Transimpedane amplifier [36]. As we an see the light is nverted t urrent using the Phtdide (PD) and then this urrent is amplified using the TIA. The utput vltage signal f TIA is delivered t the main amplifier (Limiting Amplifier). 1

28 Fig.1 PD, TIA and LA There are several bstales t extend the Bandwidth f a TIA: Phtdide Capaitane (CPD) Inherent parasiti apaitane f the CMOS Transistrs Lading Capaitane (input apaitane f the main amplifier) On the tpi f bandwidth extensin, the methds nrmally seen in the literature are dealing with these issues and try t defeat them in sme respets and hene extend the bandwidth f the TIA. There are several bandwidth extensin tehniques fr the TIAs in the literature. Fr the matter f this disussin we need t define the wrd bandwidth. The bandwidth is defined as the lwest frequeny at whih the TIA gain drps by r 3dB. Ardingly, this bandwidth is ften alled the 3-dB bandwidth [37]. Sme f the tehniques whih have been dne previusly in the literature are summarized in the fllwing setins. 13

29 . Shunt peaking Shunt peaking is the traditinal way t enhane the bandwidth in wideband amplifiers. It uses a resnant peaking at the utput f the iruit. It imprves the BW by adding an indutr t the utput lad. It intrdues a resnant peaking at the utput as the amplitude starts t rll ff at high frequenies. Basially what it des is that, it inreases the effetive lad impedane as the apaitive reatane drps at high frequenies [37]. The mdel fr a mmn sure amplifier with shunt peaking is shwn in Fig.. [30], [33]. As we an see an indutr is added in series with the resistive lad and establishes a resnane iruit and redues the effet f the utput apaitane whih in this figure nsists f all the parasiti apaitanes f the drain f the transistr and the lading apaitane f the next stage. Fig.. shunt peaking Hasan [31] has used shunt peaking (indutive peaking) tehnique and the struture f his TIA is shwn in Fig.3. As we knw shunt peaking des nt inrease the bandwidth in mparisn with ther tehniques. 14

30 Fig.3 shunt peaking tehnique used t extend the BW by Hasan [31] The first stage f this TIA is mmn gate (CG) and the send stage is a differential amplifier fr whih the shunt peaking is applied. The third stage is mmn sure (CS) and the furth ne is mmn drain (CD). Hassan has implemented the iruit in 0.5um CMOS tehnlgy and he has ahieved apprximately 3.5 GHz -3dB BW and 60dB hms transresistane. The amunt f phtdide apaitane in this wrk is 50fF. Anther shunt peaking example is shwn in Fig..4. Krmer [3] has used indutive peaking tehnique in all the 3 stages f the TIA. The main stage is mmn gate (CG) and it uses bsting stages in the path f the signal. Based n this iruit Krmer ahieves a transresistane gain f 5dB hms and -3dB BW f 13GHz. He has implemented this iruit using 80nm CMOS tehnlgy. In this implementatin a PD apaitane f 0fF has been nsidered. 15

31 Fig.4 shunt peaking tehnique by Krmer [3] The advantage is that the iruit dissipates lw pwer. Hwever, the iruit uses 3 indutrs whih inherently upy large area..3 Series peaking Wu [35] has presented series peaking tehnique as shwn in Fig..5. This tehnique mitigates the deterirated parasiti apaitanes in CMOS tehnlgy. Beause the indutr is inserted in series with all the stages in the signal path, it is alled series peaking tehnique. As we an see in Fig..5 the struture f the iruit shws that indutrs are used t redue the effet f the parasiti apaitanes in the different stages f the amplifier. Withut indutrs, amplifier bandwidth is mainly determined by RC time nstants f every nde. 16

32 Fig..5 Mdel f series peaking tehnique [35] This wrk was dne in 0.18um CMOS tehnlgy and ahieves a gain f 61dB-Ohms and BW f arund 7GHz. The amunt f PD apaitane in this wrk is 50fF. Fig.6 Ciruit fr series peaking implemented by Wu [35] This iruit uses 7 indutrs fr 3-stage and 9-indutrs fr 5 stage TIAs. The iruit nsumes a large area n the hip. The advantage f this iruit is the extensin f the bandwidth by a large fatr..4 PIP tehnique Jin and HSu [34] have prpsed this tehnique t defeat the parasiti apaitanes using the mbinatin f several indutrs. The mbinatin f the indutrs shapes a Π and hene 17

33 they all it a Pi-type Indutr Peaking (PIP). Fig..7 shws hw the mbinatin f 3 indutrs in a mmn sure amplifier nstruts the PIP tehnique. Fig..7 PIP tehnique small signal mdel [34] This tehnique imprves the BW f the TIA by resnating with the intrinsi apaitanes f the devies. The atual implemented iruit is shwn in Fig..8. Fig.8 Ciruit implemented by Jin and Hsu [34] 18

34 This iruit is implemented in 0.18 CMOS tehnlgy and ahieves a high bandwidth f 30GHz and 51dB-Ohms gain. The amunt f PD apaitane in this iruit is the lwest fund in the literature and it is 50fF. This iruit an extend the bandwidth f the transimpednae amplifier by the largest fatr fund in the literature whih is 3.3. The disadvantage f this wrk is using 15 indutrs t extend the bandwidth f the transimpednae amplifier. This results in nsuming a large area n the hip..5 Mathing indutr between the stages Analui [38] has prpsed a tehnique t islate between different stages f an amplifier. In this methd a passive netwrk is used t islate the effet f apaitrs. This passive netwrk absrbs the effet f parasiti apaitr f the transistr. The prpsed passive netwrk in Fig..9 is an indutr and it frms a ladder filter with the parasiti apaitanes f devies. Fig..9 Mdel f the prpsed tehnique by Analui [38] The iruit whih is implemented by Analui is shwn in Fig..10. The parasiti apaitanes f the devies are shwn in the iruit. These apaitanes frm the ladder struture with the deliberately added indutrs. 19

35 Fig..10 Ciruit implemented by Analui [38] Based n this struture, gain f 54dB and 3dB BW f 9.GHz have been ahieved. This iruit has been implemented in 0.18um BICMOS press using CMOS transistrs. The amunt f PD apaitane has been nsidered 500fF. This tehnique uses 4 indutrs and mitigates the effet f the largest phtdide apaitane fund in the literature. The bandwidth extensin rati (BWER) fr this iruit is.4. The iruit dissipates high pwer in mparisn with ther methds..6 Indutive feedbak tehnique Chalvatzis [39] has used the indutive feedbak tehnique t extend the bandwidth f CMOS transimpedane amplifiers. Inverter based transimpedane amplifiers and mmn sure based transimpedane amplifiers using indutive feedbak have been intrdued and 0

36 implementatin results f these iruits have als been prdued. The tehnique has been shwn t be apable f extending the bandwidth f transimpedane amplifiers effetively. In this referene the tehnique has been alled as resistr indutr transimpedane feedbak. Fig..11 Ciruit shematis f lw-vltage TIAs with indutive feedbak [39] In [39], the iruits shwn in Fig..11 have been used as building blks fr 40Gb/s system. These iruits have been intrdued in this referene but the bandwidth extensin is intuitively explained by resnane phenmenn. Hwever, this explanatin based n resnane phenmenn is nt satisfatry. Sine in the paper, n frmulatin fr alulating the required indutr value has been given, it seems the value f the indutr has been seleted based n trial and errr methd. Therefre a mre general apprah based n small signal analysis and transfer funtin harateristis f the iruitries is required. Understanding the exat behavir f the iruitries an make it pssible t further inrease the bandwidth mpared t referene [39]. In this thesis the main fus is n explaining mathematially the mehanism f bandwidth extensin fr these iruits. The tehnique is really interesting sine by using nly ne indutr the bandwidth extensin is high. This is the mst effetive tehnique t extend the bandwidth f 1

37 transimpedane amplifiers using less number f indutrs. This is the reasn that this wrk is hsen t mtivate the wrk f this thesis..7 Cnlusin In this hapter we reviewed sme f the BW extensin tehniques available in the literature in the field f TIA design. In general, indutive tehniques are mmn t extend the bandwidth in TIAs. The prblem with indutrs is the nsumptin f a large area n the hip. The researhers use indutr based methd as an effetive methd t extend the bandwidth f TIAs. The belief is that it is wrth t nsume area n the hip and instead have a mre wideband iruit. Hwever, redutin f the area remains imprtant. In indutive feedbak methd, amunt f bandwidth extensin is high when the iruit emplys nly ne indutr. Unfrtunately this tehnique has been used in the wrk intuitively withut muh explanatin f the mehanism f the extensin. Therefre mtivatin exists t shw in this thesis hw the tehnique is apable f extending the bandwidth effetively by mathematial analysis and extensive simulatins.

38 Chapter 3 Bandwidth extensin using zer ple anellatin In the previus hapters we intrdued the ptial reeivers as imprtant parts f the wireline data mmuniatin systems and then we fused n the transimpedane amplifiers as ne f the main elements f the ptial reeivers. We als intrdued sme f the bstales t extend the bandwidth f the TIAs. In this hapter the disussin f zer ple anellatin fr bandwidth extensin f TIAs using indutive feedbak is dne. The press f bandwidth extensin using zer ple anellatin fr the inverter based TIA is dne bth analytially and by simulatin results using well-knwn tls. We als shw a mparisn between this wrk and sme ther state-f-the-art wrks in the literature. A simulatin f the eye diagram fr the TIA is dne t shw the apability f the tehnique t pass the high data rate. 3

39 3.1 Small signal mdel and zer ple anellatin In CMOS amplifier iruits, the main prblem t extend the bandwidth is the parasiti apaitane invlved with the transistr. In the trans-impedane amplifiers the situatin is muh wrse beause we als need t als defeat the pht dide parasiti apaitane at the input f the amplifier. In rder t extend the bandwidth f the TIA we need t have sme srt f indutive apaitive resnane t be able t anel the effet f the parasiti apaitrs. This an be dne by the use f indutrs whih is quite mmn. In the literature it is aeptable t lse sme area f the hip by using sme spiral indutrs t ahieve wide bandwidth amplifiers. This study nsiders the indutive feedbak tehnique [39], [40] fr bandwidth extensin f CMOS TIAs whih redues the effet f the inherent parasiti apaitanes f the MOS transistr and the PD. The tehnique is analyzed and explained mathematially and by simulatin based n small signal mdel and transfer funtin. The shunt-shunt feedbak tehnique [41] has been used fr bandwidth extensin f amplifiers and it is the traditinal way f extending the bandwidth f an pen lp amplifier by adding a resistive feedbak t the amplifier. Shunt Shunt feedbak r Vltage Current feedbak [4] in mireletrnis is a struture fr whih the sample f the utput vltage using the feedbak netwrk (the impedane in the feedbak path) is taken and returns a urrent t the input f the system. Usually in this type f design, the lsed lp amplifier has a dminant ple whih nstruts the -3db BW f the amplifier. This struture will have a near-nstant gainbandwidth prdut (GBW), meaning that gain is traded ff against bandwidth. Previus studies shwed that judiial hie f the elements in a TIA uld lead t better perfrmanes f the 4

40 amplifier [43]. The idea here is t extend the BW f the TIA by deliberately adding a zer t the transfer funtin f the TIA and hene anel the dminant ple f the amplifier thereby extending the BW. This an be dne by adding an indutr t the feedbak path f the TIA. The newly intrdued indutr in the feedbak path (indutive feedbak) adds ne zer and ne ple t the transfer funtin f the TIA and by an apprpriate design the newly added zer an anel the dminant ple f the amplifier and hene extend the BW [44]. In rder t disuss the tehnique in detail we nsider tw TIAs shwn in Figures 3.1 and 3.. Fig. 3.1 TIA with resistive feedbak Fig. 3. TIA with indutive feedbak 5

41 In this study we refer t the iruit in Fig. 3.1 as the TIA with resistive feedbak and the iruit in Fig. 3. as the TIA with indutive feedbak. The small signal mdel [45] fr the TIA with indutive feedbak is shwn in Fig Fr the previus ase (TIA with resistive feedbak) we an simply have a shrt iruit instead f the indutr (r set L=0 in the fllwing equatins). Fig. 3.3 Small signal mdel f the TIA with indutive feedbak In the small signal mdel fr the TIA we have these definitins: G m g g, r r r ) (3.1) m1 m ( ds1 ds i gs 1 gs PD f gd1 gd, db 1 db L and the transfer funtin f this iruit is: a * s b * s Z( s) 3 A* s B * s C * s D (3.) 6

42 7 In whih fr the ase f the Fig. 3.1 (L=0) the effiients are shwn with the index 1 and we have: 1 0 a b R f 1 R G m A ) ( 1 f i f i R B (3.3) ) ( 1 m f f i i G g g R C g G m D 1 Fr the ase f the iruit in Fig 3. we have the effiients as (shwn with the index ): a L f R f LG m b R G m 1 (3.4) ) ( f i f i L A ) ( ) ( m f f i f i f i G g g L R B ) ( m f f i i G g g R C g G m D Nw nsidering the transfer funtin f the system in Fig. 3.1, the dminant ple f the system (-3db BW) an be apprximately alulated as D1/C1 whih is: ( m) f f i i m G C g C C g R C C G g P (3.5)

43 The nditin fr existene f a real dminant ple is t have a relatively large input apaitane. This translates as with a relatively large phtdide apaitane, the iruit has a real dminant ple. This is bvius as having a large phtdide apaitane means existene f a big RC time nstant at the input f the iruit. In this apprah, the dminant ple is anelled by adding a zer. This an be ahieved by adding an indutr in the feedbak path f the amplifier giving the iruit in Fig. 3.. As we an see adding an indutr t the feedbak path adds ne ple and ne zer t the transfer funtin and the amunt f newly added zer is apprximately: R Z L (3.6) Nw as we an see frm the equatins that by a judiial hie f the indutane we an anel the dminant ple f the iruit in Fig. 1 whih determines the -3db BW and hene extend the BW. An apprximate value fr the amunt f the indutr an be alulated by slving the equatin P=Z s we will have: L R( C i C ) R g ( C g G i m C f G m ) (3.7) 3. Simulatin results fr an illustrative example In rder t shw the feasibility f the methd, the iruit in Fig. 3. has been simulated using a well-knwn sub-mirn CMOS tehnlgy (i.e. 90nm CMOS STMireletrnis). Simulatins are dne with a single supply (i.e. Vdd =1. V) and in the presene f a 150fF phtdide apaitane and 5fF lading apaitane. This lading apaitane is used t mdel an n-hip limiting amplifier that wuld typially fllw a TIA [46]. 8

44 3..1 Zer-Ple Canellatin Press The zer ple analysis utlined here was dne using the shemati f the iruit (Fig 3..) with ideal indutr values t shw the press f zer-ple anellatin in detail. Based n the zer ple analysis fr the iruit in Fig. 3.1 (TIA with resistive feedbak), the iruit has tw ples and ne zer and the ples are lated in the LHP f the s-plane whih shws the iruit is stable [47]. Nw we nsider the ase in Fig. 3. in whih we have added the indutr t the feedbak in the iruit. Nw in this ase the iruit will have tw zers and three ples. By hsing the indutr arding t (3.7) we an anel the dminant ple leaving a pair f mplex njugate ples in the iruit. The iruit after having anelled the single dminant ple will have tw mplex njugate ples with a damping fatr and natural frequeny whih an be designed fr the desired frequeny respnse. The atual values f the ples and zers extrated frm the simulatin are shwn in Table 3.1. The zer-ple anellatin press has been shwn in Table 3.1 and we an see that by hanging the value f the indutr in the iruit the newly added zer is mving twards the dminant ple f the iruit. In the end it reahes t that ple and anels it and hene this zer an extend the -3dB BW. We an als see that the psitins f the mplex njugate ples are hanging by sweeping the value f the indutr. The rt-lus f the lsed lp system as a funtin f L is shwn in Fig

45 Fig 3.4 Rt-Lus f the indutive feedbak TIA (Z: zer added by the indutr, P:dminant ple) Table 3.1 Ple -Zer analysis fr the iruit in Fig. 3. L(nH) Zers Ples (GHz) (GHz) ±17.9j ±17j ±16j ±15j 30

46 3.. Frequeny respnse T evaluate TIA-Gain vs. Frequeny simulatins have been dne in this part. Spiral indutr was mdeled using typial mdels and values available in the literature [48], [7]. Other parts f the iruit exept the indutr were extrated frm the layut and the spiral indutr mdel whih was used in this simulatin is shwn in Fig This is a widely used mdel in the literature and the typial values fr the parasiti elements are the values whih are available in the literature [48]. Fig. 3.5 Spiral Indutr Mdel The values whih are used fr this mdel are shwn in the Table 3.. These values are apprpriate fr a spiral indutr f apprximately 3nH. Hwever these values depend n t the indutr value [33], [77]. 31

47 Table 3. Values f the parasiti elements Element C s R s C x C si R si value 0 ff ff ff 1 K The frequeny respnse results based n different values f the indutr is shwn in Fig. 3.6 and summarized in Table 3.3. The amunt f gain peaking has been shwn as well. Frm Table 3.3 it an be seen that the -3dB bandwidth f 7.1GHz fr L=0 was extended using the indutive feedbak tehnique t 16.7GHz. This rrespnds t a Bandwidth Extensin Rati (BWER) f apprximately.4. Table 3.3-AC simulatin result f the TIA M1(um) M(um) R(Ohms) L(nH) G(dB-Ohms) BW(GHz) Peaking(dB) 1/0.1 1/ n /0.1 1/ n /0.1 1/ n /0.1 1/ n /0.1 1/ n /0.1 1/ n

48 Fig. 3.6 Frequeny respnse f the iruit In Table 3.4 we an see the mparisn f this wrk with ther previusly published wrks using ther tehniques. The iruit is very lw pwer and mpares favrably with ther wrks. The tehnique s lsest rival [3] ahieved a smewhat lwer bandwidth, but with a smewhat larger PD apaitane, and in a better tehnlgy. Hwever, the iruit used nly ne indutr f nh, whereas the iruit in [3] required three indutrs, eah f slightly larger value. Therefre this tehnique ffers lw-pwer dissipatin, high bandwidth, using nly ne indutr. The pwer dissipatin in this iruit is.mw. Als nise perfrmane in this iruit is mpetitive. 33

49 Table 3.4-Perfrmane f the TIA and mparisn Tehnlgy TIA Gain -3 db i n, in (pa/ Hz) Number f PD Cap Pwer (mw) (db-ohm) BW(GHz) Indutrs (ff) This wrk 90nm- CMOS Design[35] 180nm-CMOS Design[38] 180nm-BiCMOS Design[34] 180nm-CMOS Design[3] 80nm-CMOS Design[55] 180nm-CMOS N/A Eye diagram The eye diagram fr the iruit in this hapter has been simulated and shwn as fllws. The main bjetive f bandwidth extensin is t pass high data rate thrugh the system. This data requires speifi perfrmane whih may nt be ahieved if the TIA des nt satisfy the neessary nditins t avid ISI. Therefre t make sure that the perfrmane is prper, the eye diagram prdued by the iruit must be simulated and examined. If the eye is pen, it means perfrmane is gd enugh. Therefre we simulated the iruit t ahieve the eye diagram as shwn in Fig As we an see in the Fig. 3.7 the eye is quite pen and therefre it shws that the perfrmane f the system is gd enugh t pass the high data rate. The amunt f the data rate fr this simulatin has been nsidered as 0Gb/s. Fig. 3.7 Eye diagram fr data rate f 0GHz 34

50 3.4 Cnlusin In this hapter the zer ple anellatin fr the indutive feedbak tehnique fr inverter based transimpedane amplifier was shwn mathematially and the press was prved by detailed zer ple analysis. As an illustrative example the amunt f phtdide apaitane was hsen t be 150fF. Evaluatin f the results shws that zer ple anellatin is the phenmenn fr bandwidth extensin f the TIA. This methd may be applied in mass prdutin f these iruits. Hwever, beause f mismath prblem, sme extensive effrt may be required. The eye diagram fr the iruit was als simulated and shwn. The wide pen eye shws the suess f the iruit t pass the high data rate withut ISI and therefre with high perfrmane. In the next hapter anther mehanism f bandwidth extensin using indutive feedbak fr inverter based CMOS transimpedane amplifier is disussed. That is bandwidth extensin using mpensatin f the harateristis f mplex njugate ples. 35

51 Chapter 4 Bandwidth extensin using mplex njugate ple mpensatin In hapter 3 the indutive feedbak tehnique was detailed as an effetive tehnique t extend the bandwidth f the transimpedane amplifiers and the BW extensin press was explained. In the previus ase the dminant ple f the system was anelled using a newly added zer by the indutive feedbak and hene the bandwidth extensin using the press f zer-ple anellatin happened. The dminant ple f the system in that ase is the ple nstruted by the phtdide apaitane (PD) sine the value f the apaitane is suh that 36

52 the ple nerned with that apaitane is the dminant ple in mparisn with the ther ples in the system. Nrmally the dminant ple f a system an be nstruted by large apaitanes. Hwever, when we have a small phtdide apaitane in the system, we realize that in this ase there is n dminant ple nstruted by the phtdide apaitane f the system. Even thugh, we bserve the extensin f the bandwidth using the indutive feedbak tehnique. Fr the simpliity reasns we all the first ase large PD and the send ase small PD. In the ase f large PD the zer ple anellatin press happens whereas fr the small PD ase des nt. In this hapter [49] we will disuss the press f bandwidth extensin fr the ase f the small PD in detail. The feasibility f the press will be analyzed and the methd will be nfirmed mathematially and by extensive simulatins. In this hapter the same TIA iruit using indutive feedbak as hapter 3 is used. Hwever, instead f large PD (150fF) a small PD (50fF) is nsidered. It is shwn that bandwidth extensin press is based n hange in the harateristis f the mplex njugate ples. 4.1 Send rder system T explain the bandwidth extensin press we will briefly lk at the send rder system and its harateristis. Send rder system with a pair f mplex njugate ples and the mathematial harateristi f the ples and relatins with frequeny respnse are given as fllws. These relatins shwn in (4.1) are mmn equatins fr the send rder system in ntrl system bks [47]. 37

53 n Z( s) (4.1) s s n n Ples =-a± j b a, b>0 Ples= n j n 1 a a b n a b BW= (1 ) (1 ) 1 n ( ) BW n (fr 0.3< <0.8) In these relatins and n are damping fatr and natural frequeny f the transfer funtin Z(s). Ples f the system (rts f the denminatr) have been shwn in the relatins. The -3dB bandwidth f the transfer funtin is BW whih has been alulated in the relatin. 4. Cmplex njugate ples mpensatin system is Based n Fig. 4.1 whih is the same as Fig. 3. in hapter 3 the transfer funtin f the Fig. 4.1 TIA with indutive feedbak 38

54 a * s b * s Z( s) 3 A* s B * s C * s D (4.) In whih fr the ase f L=0 the effiients are shwn with the index 1 and we have: a 1 0 b1 R f 1 1G A 1 0 B C m R R( ) (4.3) 1 i f i f R( g G 1 i i f f m g ) D 1 g G m Based n the transfer funtin the (delta) f the send rder denminatr is 1 4B1D 1 C (4.4) If we plug in the effiients frm the equatins and simplify, we find bundary nditins as C i 4RCGm (4.5) (1 Rg ) If C i is large than this term the iruit will have a psitive delta, therefre the iruit will have real ples. In the ase f negative delta the iruit will have a negative delta and therefre the iruit will have mplex njugate ples. In this hapter we refer t the first ase as large PD and the send ase as small PD. 39

55 In Fig. 4.1 fr L 0, we have the fllwing effiients a L f b R f LG m 1G R m (4.6) A L( i f i f B C R( ) ) L( g i f i f i f f m R( g G i i f f m g ) g G ) D g G m In the ase f small PD sine the input apaitane is small based n Eq. (4.5) mplex njugate ples exist. Hwever, in the ase f large PD real ples exist. In the ase f small PD these mplex ples are the dminant ples f the iruit. By adding the indutr the effiients fr the transfer funtin will hange and therefre the harateristi f the ples will hange and the BW whih is established based n these effiients will hange as well. We will explain this mathematially in the fllwing. In a transfer funtin with tw mplex ples and ne real ple, the denminatr is a third rder plynmial as: s 3 ( n ) s ( n n ) s n (4.7) In this plynmial and n are damping fatr and natural frequeny f the mplex njugate ples and is the real ple. 40

56 41 When the real ple is nt dminant (i.e. is big) we an simplify the plynmial as: 3 n n s s s (4.8) In the ase f L=0, we had a pair f mplex njugate ples with damping fatr and natural frequeny as D B B C B D n (4.9) ) ( 1 f i f i R B ) ( 1 m f f i i G g g R C g G m D 1 After adding the indutr (applying the indutive feedbak) we will have new damping fatr and natural frequeny fr the amplifier: 5 0. D B B C B D n (4.10) ) ( ) ( m f f i f i f i G g g L R B ) ( m f f i i G g g R C g G m D We an see that by adding the indutr we an ntrl the damping fatr and natural frequeny f the mplex njugate ples using the value f the indutr. Therefre by a judiial hie f the value f the indutr we an extend the bandwidth.

57 4.3 Simulatin results In rder t shw the feasibility f the methd, the iruit has been simulated using a wellknwn sub-mirn CMOS tehnlgy (i.e. 90nm CMOS STMireletrnis). Simulatins are dne with a single supply (i.e. Vdd =1. V) and in the presene f a 50fF phtdide apaitane and 5fF lading apaitane. This lading apaitane is used t mdel an n-hip limiting amplifier that wuld typially fllw a TIA [46] Zer-Ple Analysis The zer ple analysis is perfrmed using the shemati f the iruit (Fig. 4.1) with ideal indutr. Based n the ple-zer analysis fr the iruit when L=0 the iruit has tw ples and ne zer and the ples are lated in the LHP f the s-plane whih shws the iruit is stable [47]. Fr the ase f L 0 the iruit will have tw zers and three ples. Summary f the results fr zer ple analysis f the iruit is shwn in table 4.1. Table 4.1 Ple -Zer analysis fr the iruit L(nH) Zers (GHz) Ples (GHz) Damping Fatr Natural Frequeny (GHz) Calulated BW (GHz) 0-0.1±13.5j ±0.1j ±0.7j ±18.8j

58 4.3. Frequeny respnse The frequeny respnse (TIA-Gain vs. Frequeny) based n different values f the indutr is shwn in Fig. 4. and summarized in Table 4.. These results are based n extrated layut f the iruit in whih the spiral indutr was mdeled using typial mdels and values available in the literature [48] as shwn in Fig. 3.5 in hapter 3. Fig. 4. Frequeny respnse f the iruit 43

59 Frm Table 4. it an be seen that the -3dB bandwidth f 15.6GHz fr L=0 was extended using the indutive feedbak tehnique t 9.7GHz. The pwer dissipatin in this iruit is.mw. Table 4.-AC simulatin result f the TIA M1(um) M(um) R(Ohms) L(nH) G(dB-Ohms) BW(GHz) Peaking 1/0.1 1/ n /0.1 1/ n /0.1 1/ n /0.1 1/ n In Table 4.3 we an see the mparisn f this wrk with ther previusly published wrks using ther tehniques. The iruit is very lw pwer and mpares favrably with ther wrks. The tehnique ffers lw-pwer dissipatin, high bandwidth, using nly ne indutr. Als nise perfrmane in this iruit is mpetitive. Table 4.3-Perfrmane f the TIA and mparisn Tehnlgy TIA Gain -3 db i n, in (pa/ Hz) Number f PD Cap Pwer (mw) (db-ohm) BW(GHz) Indutrs (ff) This wrk 90nm- CMOS Design[35] 180nm-CMOS Design[38] 180nm-BiCMOS Design[34] 180nm-CMOS Design[3] 80nm-CMOS Design[55] 180nm-CMOS N/A

60 4.4 Eye diagram The eye diagram fr the iruit is simulated and shwn in Fig The main bjetive f bandwidth extensin is t pass the data f high rate thrugh the system withut ISI. This high data rate impses speifiatins n the TIA. Therefre t make sure that the perfrmane is prper, the eye diagram prdued by the iruit must be simulated and examined. If the eye is pen, it means perfrmane is gd enugh. As we an see in the Fig. 4.3 the eye is quite pen and therefre it shws that the perfrmane f the system is gd enugh t pass the high data rate. Fr the inverter based TIA using indutive feedbak in this simulatin the amunt f input apaitane is 50fF. The amunt f the indutr fr this simulatin is 1nH and the amunt f data rate is 40Gb/s. Fig. 4.3 Eye diagram fr the iruit fr data rate= 40Gb/s 45

61 4.5 Estimatin f BW Extensin Rati (BWER) One f the imprtant parameters t evaluate the Bandwidth extensin tehniques in transimpedane amplifiers is theretial bandwidth extensin rati (BWER). The definitin fr this term is the mparisn between the bandwidth befre applying the tehnique t the iruit and after applying the tehnique. The rati f the new BW and the ld BW will define the BWER. The BW extensin rati an be fund using simulatins sine the analytial alulatin f BWER an result n mpliated and umbersme equatins and it has been avided in the literature. Beause f the mplexity f these analg systems when we fae these kinds f analyses, we have t make sme assumptins. The disussin f the bandwidth extensin rati fr the tw previusly mentined ases (i.e. large and small PD) were dne and will be reprted in this part. The analysis fr BWER fr the Indutive Feedbak tehnique shws that fr the first ase (large PD) where the zer-ple anellatin press is dne the theretial BWER is apprximately.7. Fr the send ase (small PD) in whih the BW extensin press happens based n the hange in the harateristis f the mplex njugate ples BWER is apprximately.1. These figures f merits are mpetitive in mparisn with ther Bandwidth extensin tehniques whih will be disussed in this hapter. 46

62 4.5.1 BWER fr large PD The press fr bandwidth extensin in this ase is zer ple anellatin. The iruit befre adding the indutr has tw ples in whih ne f the ples is dminant and by adding the indutr the dminant ple will be anelled and the iruit will be left by a pair f mplex njugate ples. In rder t find the theretial BWER we need t mathematially plt the transfer funtins f the systems befre and after applying the tehnique. The BWER based n the mathematial frmula f the transfer funtin and typial values fr the iruit parameters has been shwn in Fig Fig. 4.4 Mathematial simulatin f transfer funtin Frm Fig. 4.4 with L=0 and L=1nH the values fr the -3dB bandwidth are 165Grad/s and 455Grad/s. Therefre theretial BWER f mre than.7 an be ahieved using this tehnique. 47

63 4.5. BWER fr small PD In this ase the effiient C1 is small and therefre the magnitude f this ple will be large whih means the real ple f the transfer funtin is nt dminant. Therefre the BW extensin will happen using the indutive feedbak by hanging the harateristis f the dminant ples (mplex njugate ples). In this ase the iruit already has a pair f mplex njugate ples. Based n the transfer funtin, damping fatr and natural frequeny an be fund using these relatins C 0.5 B 1 1 B1 D 1 D 1 n (4.15) B1 B R( C 1 i f i f R( g 1 i i f f m ) g G ) D1 g G m Based n the damping fatr and the natural frequeny we an alulate the -3dB bandwidth frm BW= n (1 ) (1 ) 1 (4.16) We an apprximately assume that the mplex njugate ples nstrut the frequeny respnse f the iruit whih is nt very far frm reality. C 0.5 B B D D n (4.17) B 48

64 49 ) ( ) ( m f f i f i f i G g g L R B ) ( m f f i i G g g R C g G m D Based n the damping fatr and the natural frequeny we an alulate the -3dB bandwidth frm the relatin BW= 1 ) (1 ) (1 n (4.18) Fr the PD=50fF the same press was dne and the result was shwn in Fig Fig. 4.5 Mathematial simulatin f transfer funtin

65 The theretial bandwidths based n values f indutrs f L=0 and L=0.75nH are 76Grad/s and 556Grad/s respetively. It is shwn in Fig. 4.5 that the theretial BWER f mre than an be ahieved when the input apaitane is small. The bandwidth reprted in this part is the Matlab simulatin f the transfer funtin f the small signal mdel using ideal indutrs with n parasiti elements [76]. In this simulatin the input apaitane is nly nsidered t be the phtdide apaitane and the feedbak apaitanes frm input and utput are ignred. This is the reasn the bandwidth reprted in this part is mre than the bandwidth reprted frm the atual bandwidth frm extrated simulatin. 4.6 Cnlusin In this hapter the thery f Bandwidth extensin fr small value f Phtdide (PD) was explained by means f apprximately nsidering the mplex njugate ples as dminant ples f the iruit. The behavir f the iruit an be realized by explaining that the harateristis f the mplex njugate ples are hanged using the indutive feedbak in rder t extend the bandwidth. The iruit ahieves -3dB bandwidth f almst 30 GHz by nly using ne indutr when draws.mw. The eye diagram f the system has been simulated t shw the effetiveness f the iruit t pass the high data rate withut ISI. In additin t that the disussin f theretial BWER fr bth the ases f large and small Phtdide (PD) was shwn. Fr the ase f the large PD, BWER f mre than.7 was ahieved and fr the ase f the small PD, BWER f mre than. These results are mpetitive with ther tehniques. Shunt peaking ahieved the BWER f 1.7 [30] and that fr indutr between the stages is.4 [37]. PIP tehnique ahieved 3.3 [34] and that fr series peaking is.5 [35]. 50

66 In hapter 3 indutive feedbak was used t extend the BW (zer-ple anellatin) when dminant ple was at the input f the iruit (large PD). In this hapter the ther ase was disussed when the input ple is nt dminant and BW extensin is dne by hanging the harateristis f the mplex njugate ples. The indutive feedbak tehnique based n the analysis and simulatin results shws that, it is apable f extending the BW effetively withut reduing the DC gain. In the next hapter anther tplgy f transimpedane amplifiers using indutive feedbak will be analyzed. The press f bandwidth extensin fr mmn sure based transimpednae amplifier will be disussed and a new 3 stage TIA will be intrdued. 51

67 Chapter 5 Wideband Cmmn Sure based TIAs Optial reeivers have a great rle in tday s high data rate (Gb/s) wireline data mmuniatin systems. T ahieve suh high data rate all the amplifiers in the signal path shuld be wideband enugh t be able t amplify the signals in thse high frequenies. Transimpedane amplifiers (TIAs) at the frntend f the ptial reeivers have the imprtant task f amplifying the small urrent reeived frm the phtdide t an aeptable level f vltage fr the next stage. The bandwidth f CMOS TIAs is limited by the phtdide (PD) apaitane and parasiti 5

68 apaitanes f the MOS transistrs. Attempts have been made reently t extend the bandwidths f TIAs t reah the data rate f 100Gb/s. In this hapter an attempt has been made t extend the bandwidth f s-based TIA using indutive feedbak mre by intrduing a new three- stage TIA t ahieve data rates f mre than 40Gb/s. In this hapter, indutive feedbak apprah fr BW extensin f mmn sure based Transimpedane amplifier has been applied [39]. The effet f parasiti apaitanes [51] f the MOS transistr has been redued using the mentined apprah. The press f zer-ple anellatin fr 3 different values f the phtdide apaitane (CPD) t extend the BW f the amplifier is explained. A new and very wideband three stage transimpedane amplifier based n mmn sure amplifier is intrdued. T demnstrate the feasibility f the tehnique transimpedane amplifiers are simulated in a well-knwn CMOS tehnlgy (i.e. 90nm STMireletrnis). Single stage mmn sure based transimpedane amplifiers ahieve 3-dB bandwidths f 3.1GHz, 1.8GHz, and 15.8GHz in the presene f a 50fF, 100fF, 150fF phtdide apaitanes and 5fF lading apaitane while nly dissipating.03mw. The new three stage amplifier ahieves bandwidths f 4.8GHz, 35.5GHz, and 8.5GHz in the presene f 50fF, 100fF, 150fF phtdide apaitanes. The pwer nsumptin fr the new transimpedane amplifier is 6.1mW. Fr all the strutures nise perfrmane is mpetitive in mparisn with ther wrks. Eye diagrams fr single stage and three stage transimpedane amplifiers have been simulated and shwn in this hapter. 53

69 5.1 Single stage mmn sure based TIA using indutive feedbak The idea in this part is t extend the bandwidth f the TIA by deliberately adding a zer t the transfer funtin f the TIA and hene anel the dminant ple f the amplifier thereby extending the BW. This an be dne by adding an indutr t the feedbak path f the TIA. The newly intrdued indutr in the feedbak path (indutive feedbak) adds ne zer and ne ple t the transfer funtin f the TIA and by an apprpriate design the newly added zer an anel the dminant ple f the amplifier and hene extend the BW [44]. In rder t disuss the tehnique in detail we nsider tw TIAs shwn in Figures 5.1 and 5.. In this hapter we refer t the iruit in Fig. 5.1 as the mmn sure based TIA (CS-based) [78] with resistive feedbak and the iruit in Fig. 5. as the mmn sure TIA with indutive feedbak [44], [39]. The small signal mdel fr the single stage mmn sure based TIA with indutive feedbak is shwn in Figure 5.3. The parasiti apaitanes f the transistr are shwn in this figure as well. This small signal mdel is used t derive the mathematial transfer funtin f the iruits. This mathematial mdel is used t analyze the iruits in this hapter. 54

70 Fig. 5.1 CS-TIA with resistive feedbak Fig. 5. CS-TIA with indutive feedbak 55

71 Fig. 5.3 Small signal mdel f the CS-TIA with indutive feedbak In the small signal mdel fr the TIA we have these definitins: Gm g m1 r ( r 1 RL) ds i gs 1 PD f gd1 db 1 L And the transfer funtin f this iruit is: as bs Z( s) 3 As Bs Cs D 56

72 57 In whih fr the ase f the Figure 5.1 (L=0) the effiients are shwn with the index 1 and we have: 1 0 a b R f 1 R G m A ) ( 1 f i f i R B ) ( 1 m f f i i G g g R C g G m D 1 Fr the ase f the iruit in Figure 5. we have the effiients as (shwn with the index ): a L f R f LG m b R G m 1 ) ( f i f i L A ) ( ) ( m f f i f i f i G g g L R B ) ( m f f i i G g g R C

73 D g G m Cnsidering the transfer funtin f the system in Figure 5.1, the dminant ple f the system whih defines the -3db BW, an be apprximately alulated as D1/C1 whih is P C i C g Gm R( C g C g C Gm) (5.) i f f In this apprah, the dminant ple is anelled by intrduing a new zer t the transfer funtin. This an be ahieved by adding an indutr in the feedbak path f the amplifier f Fig. 5.1 whih results in Figure 5.. As we an see adding an indutr t the feedbak path adds ne ple and ne zer t the transfer funtin and the amunt f newly added zer is apprximately R Z (5.3) L Frm the equatins (5.1) and (5.) by hie f the indutane we an anel the dminant ple f the iruit in Figure 5.1 hene extend the BW. An apprximate value fr the amunt f the indutr an be alulated by slving the equatin P=Z s we will have L R( C i C ) R g ( C g G i m C f G m ) (5.4) 58

74 5. Zer-Ple Canellatin Press In rder t shw the bandwidth extensin press in detail the iruit has been simulated using a well-knwn sub-mirn CMOS tehnlgy (i.e. 90nm CMOS STMireletrnis). Simulatins are dne with a single supply (i.e. Vdd=1. V). T shw the validity f the zer-ple anellatin press fr BW extensin, the simulatins were dne fr 3 different PDs f 50,100,150fF. The lad apaitane fr these 3 iruits is 5fF. This lading apaitane is used t mdel an n-hip limiting amplifier that wuld fllw a TIA. Based n the ple-zer analysis fr the iruit in Figure 5.1 (TIA with resistive feedbak), the iruit has tw ples and ne zer and the ples are lated in the LHP f the s-plane whih shws the iruit is stable. Cnsidering the ase in Figure 5. in whih we have added the indutr t the feedbak, the iruit will have tw zers and three ples. By hsing the indutr arding t (5.4) we an anel the dminant ple leaving a pair f mplex njugate ples in the iruit. The iruit after having anelled the single dminant ple will have tw mplex njugate ples with a damping fatr and natural frequeny whih an be designed fr the desired frequeny respnse. The zer-ple anellatin presses are shwn in the tables 5.1, 5., 5.3 fr CPD f 50,100,150fF and we an see that by hanging the value f the indutr in the iruit the newly added zer is mving twards the dminant ple f the iruit. In the end it reahes t that ple and anels it and hene this zer an extend the -3dB BW. We an als see that the psitins f the mplex njugate ples are hanging by sweeping the value f the indutr. 59

75 Table 5.1 Ple -Zer analysis fr the iruit (PD=50fF) L(nH) Zers (GHz) Ples (GHz) ±3.3j ±5.1j ±.1j ±0.1j In the table 5.1 fr the indutr amunt f 1.8nH the ple and the zer f the iruit beme equal and zer ple anellatin happens fr that value f the indutr. In this ase the mplex njugate ples will nstrut the -3dB bandwidth f the iruit. 60

76 Table 5. Ple -Zer analysis fr the iruit (PD=100fF) L(nH) Zers (GHz) Ples (GHz) ±35.9j ±13.8j ±10.9j ±6.9j In table 5. fr the indutr amunt f 3.5nH the ple and the zer f the iruit beme equal and zer ple anellatin happens fr that value f the indutr. 61

77 Table 5.3 Ple-Zer analysis fr the iruit (PD=150fF) L (nh) Zers (GHz) Ples (GHz) ±5.7j ±9.1j ±.8j ±.1j We an see that in the table 5.3 fr the indutr amunt f 4.5nH the ple and the zer f the iruit beme equal and zer ple anellatin happens fr that value f the indutr. In the tables 5.1, 5. and 5.3 zer ple anellatin press fr the single stage mmn sure based transimpedane amplifier fr different values f phtdide apaitane were shwn. In these tables the exat value f the indutr shwing the press an be fund. 6

78 5.3 Frequeny respnse fr single stage CS-based TIA Frequeny respnses (TIA-Gain vs. Frequeny) whih are reprted in this part are based n the extrated layut f the iruit. In these simulatins the spiral indutr was mdeled using the bradband RLC mdel fr the spiral indutr frm the EM-simulatin f the Virtus Passive Cmpnent Mdeler (VPCM) f adene whih is shwn in Figure 5.4. Fig. 5.4 Spiral indutr mdel used fr simulatin In Figure 5.4 the parasiti elements f the spiral indutr are very imprtant and shuld be nsidered fr alulatin f the bandwidth. The values fr the parasiti elements have been extrated frm the VPCM tl and tabulated in table

79 Table 5.4 Typial Values f the parasiti elements Cs Ls1 Rs1 Ls11 Rs11 Ls Rs Ls Rs Cx1 Cx Cx Csi1 Rsi1 Csi Rsi Csi Rsi.5 ff 1 nh 6.7 Ohms 176 ph 6.4 Ohms 1 nh 6.7 Ohms 176 ph 6.4 Ohms 6.5 ph 17.5 ff 5.1 ff 14.8 ff Ohms 19. ff Ohms 5.5 ff 1.7 KOhms The frequeny respnses based n different values f the indutr are shwn in Figures 5.5, 5.6, 5.7. In these figures tw ases are shwn. One ase is the simulatin fr the frequeny respnse withut the indutr L=0 and the ther ase is with the value f the indutr whih gives the bandwidth extensin fr the respetive phtdide apaitane. Fig. 5.5 shws the simulatin fr the phtdide apaitane f 50fF fr whih the value f the indutr is nh. Fig. 5.5 Frequeny respnse f the CS-TIA (PD=50fF) 64

80 Fig. 5.6 shws the simulatin fr the phtdide ase f 100fF fr whih the value f the indutr is 3nH. Fig. 5.7 shws the simulatin fr the phtdide apaitane f 150fF fr whih the value f the indutr is 5nH. In eah ase the extensin f the bandwidth an be bserved. Fig. 5.6 Frequeny respnse f the CS-TIA (PD=100fF) 65

81 Fig. 5.7 Frequeny respnse f the CS-TIA (PD=150fF) The frequeny respnses are summarized in Tables 5.5, 5.6, 5.7. The amunt f gain peaking has been shwn as well. Frm eah table it an be bserved that the bandwidth has been extended frm the value when L=0 t the value f that when L is nt 0. 66

82 Table 5.5 AC simulatin result f the TIA (CPD=50fF) M1 R(Ohms) RL(Ohms) L(nH) G(dB-Ohms) BW (GHz) Peaking(dB) 1/ n / n Table 5.6 AC simulatin result f the TIA (CPD=100fF) M1 R(Ohms) RL(Ohms) L(nH) G(dB-Ohms) BW (GHz) Peaking(dB) 1/ n / n Table 5.7 AC simulatin result f the TIA (CPD=150fF) M1 R(Ohms) RL(Ohms) L(nH) G(dB-Ohms) BW (GHz) Peaking(dB) 1/ n / n Frm tables it an be seen that Bandwidth Extensin Rati (BWER) f mre than has been ahieved. The tehnique ffers lw pwer dissipatin, high bandwidth, using nly ne indutr. 67

83 5. 4 Three Stage Cmmn Sure based Transimpedane amplifier Casaded amplifiers are ne f the mst mmn ways t widen the bandwidth f the amplifiers [37] and therefre, we an asade the mmn sure transimpedane amplifiers t get mre Gain*Bandwidth frm the amplifier. In this part we intrdue asaded three stage mmn sure Transimpedane amplifier with indutive feedbak as a very wideband struture fr high speed ptial reeivers. Figure 5.8 shws this new TIA. As an be seen in the iruit three single stage mmn sure TIAs using indutive feedbak have been asaded tgether t build a new TIA. Fig 5.8 Three stage mmn sure TIA using indutive feedbak 68

84 In figures 5.9, 5.10, 5.11 we an see the frequeny respnse fr the three-stage TIA fr different values f the indutrs fr the phtdide apaitanes (PD) f 50fF, 100fF, 150fF respetively. The bandwidth fr bigger values f the Phtdide is lwer. Fig 5.9 Frequeny respnse f the three stage TIA (PD=50fF) 69

85 Fig 5.10 Frequeny respnse f the three stage TIA (PD=100fF) Fig 5.11 Frequeny respnse f the three stage TIA (PD=150fF) 70

86 In tables 5.8, 5.9, 5.10, we an see the summary f the frequeny respnse results (bandwidth, gain, and gain peaking) f the three stage TIA fr different values f the phtdide apaitane. In the table 5.8 the results fr the PD f 50fF is shwn. Frm the table we an see that the -3dB bandwidth has been extended frm 10.7GHz t 4.8GHz and this rrespnds t BWER (Bandwidth Extensin Rati) f mre than 4 fr this iruit. In the table 5.9 the results fr the PD f 100fF are shwn. The -3dB bandwidth fr this ase has been extended frm 6.GHz t 35.5GHz. This rrespnds t BWER f arund 6. In the table 5.10 fr the PD f 150fF the bandwidth frm 4. GHz fr the ase f resistive iruit (all L=0) has been extended t 8.5GHz whih rrespnds t BWER f 7. Table 5.8 Three Stage CS based TIA with indutive feedbak (CPD=50fF) L1 L L3 Gain BW Peak (nh) (nh) (nh) (db-hms) (GHz) (db)

87 Table 5.9 Three stage CS TIA with indutive feedbak (CPD=100fF) L1 L L3 Gain BW Peak (nh) (nh) (nh) (db-hms) (GHz) (db) Table 5.10 Three stage CS TIA with indutive feedbak (CPD=150fF) L1 L L3 Gain BW Peak (nh) (nh) (nh) (db-hms) (GHz) (db) These results shw the effetiveness f the tehnique fr bandwidth extensin fr different values f the phtdide apaitane (CPD). By adjusting the value f the send resistr the amunt f the gain peaking an be adjusted. Fr the ase f 50fF, 100fF, 150fF R an be 700 hms, 800Ohms and 1.5Khms respetively t mitigate the peaking. 7

88 5.5 Nise Analysis The input referred nise urrent In, in is an imprtant issue fr TIA design, whih determines the sensitivity f the iruit. Als in asaded strutures nrmally the effet f the first stage in the nise perfrmane f the whle hain an be very imprtant beause the impat f the nise frm ther stages an be mitigated thrugh the gain f the previus stages. As fr the nise analysis f the CS-stage, studies shw that nise harateristis f the devie are dminated by the drain thermal nise [5], [53]. Based n the disussin abve we an mdel the input referred nise based n the equivalent mdel fr the nise perfrmane fr this iruit whih has been shwn in the Figure 5.8. Fig 5.1 Nise equivalent mdel f the CS-TIA In rder t analyze the input referred nise first we define the nise sures in the equivalent iruit. 73

89 V n, R 4 KTR V n, RL 4 KTR (5.5) L I n, M1 4KTg m 1 The value fr is apprximately mentined as /3 and the exat amunt fr this parameter is under ative researh [54]. In rder t analyze this, we an apply the superpsitin t nise sures and the result f the nise analysis will be the summatin f the urrent nise at the input. We an apprximately write the relatin fr the input referred nise as I n, in R 1 1 ( CPD ) Z 4KT gm g Z m 1 R 4KT R (5.6) Z R R Ls Based n the abve equatins, the indutive feedbak tehnique an imprve the nise perfrmane f the transimpedane amplifier. The reasn is that the indutive feedbak makes a frequeny dependent feedbak fatr whih redues the effet f the nise sures in the iruit. 74

90 It an be shwn that the nise ntributin frm the lad is very small. Fr the matter f simpliity we ignre the nise effet f the utput lad t the input. In equatin (5.5) fr the ase f regular TIA (L=0) by inreasing frequeny nly the numeratr will inrease and hene the nise urrent will inrease. Hwever, fr the ase f indutive feedbak the term inluding the frequeny appears in the denminatr as well whih dereases the nise ntributin referred t the input f TIA. Simulatins fr the nise analysis are dne n the iruit and the results an be seen in figures 5.13 and Figures shw the results fr the ne stage and als 3 stage CS- Based TIAs. In Fig the simulatins fr the input referred nise f the single stage mmn sure based transimpedane amplifier are shwn. Simulatins fr different values f the phtdide apaitanes and respetive values f the indutrs an be seen in this figure. The disussin in this part is related t nise PSD. In eah ase, it an be bserved that adding the indutr t the feedbak path an imprve the nise perfrmane f the iruit.. 75

91 Fig 5.13 Simulated In, in with different values f Cpd and L fr ne stage CS TIA In Fig the simulatins fr the input referred nise f the three stage mmn sure based transimpedane amplifier are shwn. Simulatins fr different values f the phtdide apaitane and respetive values f the indutrs an be seen in this figure. The simulatin shws the nise PSD. Fr eah ase, it an be bserved that adding the indutr t the feedbak path an imprve the nise perfrmane f the iruit. 76

92 Fig 5.14 Simulated In, in with different values f Cpd and L fr three stage CS TIA In table 5.11 we an see summary f the results and mparisn with ther wrks. The first six rws shw the results frm this hapter. The single stage and the three stage mmn sure TIA with indutive feedbak fr 3 different values f the phtdide apaitane have been simulated and the results fr the iruitries f this hapter are mpared in this table. As we an see the iruits are very lw pwer in mparisn with ther wrks. Despite having lw pwer the iruits have mpetitive nise perfrmane. There is n figure f merit [74] whih an define all the parameters invlved with the design f the transimpedane amplifiers. In this table, it an be seen the iruits in this hapter are lw pwer and high bandwidth in mparisn 77

93 with ther previusly published wrks. The number f indutrs used in the iruits in this hapter is lwer than the number f indutrs f mst f the TIAs. Table 5.11 Summary f the results and mparisn with ther wrks Tehnlgy TIA Gain (db-ohm) -3 db BW(GHz) i n, in (pa/ Hz) Pwer (mw) Number f Indutrs PD Cap (ff) This wrk [Fig. 5.8] 90nm-CMOS This wrk [Fig. 5.8] 90nm-CMOS This Wrk [Fig. 5.8] 90nm-CMOS This wrk [Fig. 5.] 90nm- CMOS This wrk [Fig. 5.] 90nm- CMOS This wrk [Fig. 5.] 90nm- CMOS Design[44] 90nm-CMOS Design[35] 180nm-CMOS Design[37] 180nm-BiCMOS Design[34] 180nm-CMOS Design[3] 80nm-CMOS Design[55] 180nm-CMOS N/A Design[39] 65nm-CMOS 8 9GHz N/A 6mW 1 N/A 78

94 5.6 Eye diagram The eye diagram fr the iruit in this hapter has been simulated and shwn as fllws. The main bjetive f bandwidth extensin is t pass high data rate. This data requires speifi perfrmane whih may nt be ahieved if the TIA des nt satisfy the neessary nditins t avid ISI. Therefre t make sure f the perfrmane, the eye diagram prdued by the iruit must be simulated and examined. If the eye is wide pen, it shws perfrmane is gd. Fig 5.15 shws the eye diagram fr the three stage mmn sure based Transimpedane amplifier using indutive feedbak with input apaitane f 50 ff. In this simulatin the value f L is nh the data rate f is 50Gb/S. Fig shws the eye diagram fr the ne stage mmn sure based transimpedane amplifier using indutive feedbak and fr the input apaitane f 50fF. In this simulatin the data rate f 40Gb/s and L f nh have been used. As we an see in these figures the eye is quite pen and therefre it shws that the perfrmane f the system is gd enugh t pass the high data rate. In mparisn between the tw tplgies, simulatins shw that the ne stage transimpedane amplifier is inapable f passing the data rate f 50Gb/s withut inter symbl interferene in ppsed t the three stage amplifier. 79

95 Fig Eye diagram fr the three-stage TIA (data rate=50gb/s) Fig Eye diagram fr the ne stage CS-TIA (data rate=40gb/s) 80

96 5.7 Disrete frequeny saled dwn experiment The nept f bandwidth extensin using indutive feedbak has already been prved by IC realizatin [39] in an advaned tehnlgy (65nm CMOS). In rder t shw the nept f bandwidth extensin using indutive feedbak tehnique, a sample iruit based n mmn sure amplifier using indutive feedbak is assembled. The disrete mpnents available in the eletrnis labratry are used t assemble the iruit. Tw ases f disrete iruits with and withut indutr have been assembled and -3db bandwidth fr bth the ases has been measured. Fig shws the iruit and its utput signal n the sillspe fr a sinusidal input. Fig Disrete iruit assembled and the utput signal 81