III. DESIGN OF CIRCUIT COMPONENTS

Transcription

1 ISSN: ISO 900:008 ertified Volume, Issue 5, November 0 Design and Analysis of a MOS 0.7V ow Noise Amplifier for GPS Band Najeemulla Baig, handu DS, 3 Satyanarayana hanagala, 4 B.Satish,3 Assoiate Proffesor, AE Engineering ollege, Hyderabad, A.P, India Assistant Professor, AE Engineering ollege, Hyderabad, A.P, India 4 Assoiate Professor, VR ollege of Engineering, Hyderabd, A.P, India Abstrat: - This paper presents a.5754 GHz low voltage ow Noise Amplifier for Global Position System arrier signal. This design is implemented using 90nm MOS tehnology. The ow Noise Amplifier is designed with a supply voltage of only 0.7V. The performane is then evaluated for Noise Figure, inearity and Sensitivity of the design under test. It is observed that the main trade-off is between Noise Figure and the size of indutor. For this purpose, a 7nH on-hip spiral indutane was used at the input end of the NA to ahieve a Noise Figure of 933.4mdB. The voltage gain and power dissipation fator are alulated and are in good agreement with the results obtained. The NA design is arried out using adene RF spetre simulator. Index Terms - Gain, Impedane Mathing, Indutive Soure Degenerated NA, ow Noise Amplifier, Noise Figure. indutive soure degeneration. asading transistor M is used to redue the interation of the tuned output with the tuned input, and to further redue the effet of the gate-drain apaitane gd of M. The indutors and are hosen to provide the desired input resistane (Rs). Indutor 3 and the apaitane of the transistors M form a tank iruit to tune the NA to.5754ghz. I. INTRODUTION The demand on urrent GPS appliations fores the design of high performane, low ost frequeny band (.575GHz entre frequeny) reeivers. The arrier frequeny of GPS signals for ivil appliations is.5754 GHz. Typially GPS signals reeived at an antenna near the surfae of the earth are in the order of 30 dbm while the SNR is 9 db for the MHz bandwidth. This extremely weak signal level puts a strong restrition on the noise performane of NA whih is the key omponent of GPS reeiver hain off the antennas. Sine the signal at the reeiver unit is very weak, noise performane and gain of the NA have to meet the standards. The main funtion of NA is to provide enough gain to overome the noise of subsequent stages (suh as mixer). NA should also aommodate large signals without distortion, and present 50Ω impedane to the input soure, i.e. an antenna. In this paper, a low voltage and low power MOS NA at.5754ghz is proposed whih is GPS band signal. As a design tool, sensitivity analysis gives a measure of sensitivity of the NA iruit performane to a hange in the iruit element values, there by assisting the designer in hoosing adequate iruit-element toleranes. Suh sensitivity analysis of the NA is very benefiial for making appropriate design tradeoffs. In this paper, the sensitivity, NF, and linearity analysis of the proposed NA iruit are evaluated. II. NA IRUIT DESIGN The omplete shemati of the.5754ghz NA is shown in Fig., where,, and 3 are all implemented with onhip spiral indutors. The method employed here is Fig. Shemati of the Proposed NA M3, Rref, and R form a bias iruit. Transistor M3 essentially forms a urrent mirror with M, where its width is a small fration of the width of M s in order to minimize the power overhead of the bias iruit. is a D bloking apaitor. The urrent through M 3 is set by the supply voltage and R ref (500-Ω) hosen to provide optimum noise figure and power dissipation in onjuntion with the V gs of M 3.The resistor R is hosen large enough that its equivalent noise urrent is small enough to be ignored. In a 50Ω system, values of several hundred ohms to Kilo-ohms or so are adequate. Here, let us selet a value of 4.6KΩ (optimized).to omplete the biasing, D bloking apaitor must be present to prevent upsetting the gate-to-soure bias of M.The value of is hosen to be as high as.0065pf to provide a negligible reatane at the frequeny of operation. As metal apaitane gives more noise figure, a bloking apaitor PMOS apaitane is used in this design instead of metal apaitane. III. DESIGN OF IRUIT OMPONENTS The design was made for.5754 GHz frequeny, this low noise amplifier has to amplify the signal by approximately 5 to 0dB. 7

2 ISSN: ISO 900:008 ertified Volume, Issue 5, November 0 STEP : Design using the real part mathing ondition. Applying the speifiation for NF as NF< db, using the NF Assume that the soure impedane (Rs) =50. R g f () m s T T gs 3 expression NF (4) Where is given by ft is unity gain frequeny of the MOS transistor and Solving yields 3 3 (5) g m f T Therefore, 50 ft () et =nh. STEP3: Design = gs and hene ( W / ) using imaginary part mathing ondition Using the mathing ondition ( ) With values. 9 (.5754)0 rad / s and using and onsidering ft Fig. Small Signal model of the NA 5GHz for 90nm tehnology, the value of ( ) the soure indutane is:, 50 9 (0 ) (3) (5) = (.5/ ) nh = 0.59 nh Sine the noise onsequenes of exessive indutane are muh less serious than for insuffiient indutane [4], the authors onsider a higher value for than the value alulated during simulation = fF 9 From the fat that, = = ox gs W 3 Taking =00nm as the minimum hannel length allowed for this 90nm proess, the apaitane per unit area an be formulated as: ox 3 ox / tox STEP: Design using NF speifiation 73

3 W ox = ISSN: ISO 900:008 ertified 5 ase : Assuming symmetri widths of the transistors, Volume, Issue 5, November 0 Assuming 3 and finding and adjusting the values for =8.3064mm. optimum results. Here 3 =0.34nH, =46.fF and using R to get R =4.6KΩ (after optimizing for gain). W W Result: Using this value for M and M results in large power dissipation of mw and NF=.33dB, for VDD=0.7V. Hene, seleting =7nH and redesigning bak from step 3 gives W=.3447mm, NF=933.4mdB and a power dissipation of 35mW. This shows that the Noise Figure dereases with inrease in hannel length. W W ase : Result: When W=*W, NA gives a better Noise Figure when ompared to the Noise Figure in ase, this also gives a better gain. W W ase 3: Result: Noise Figure and Gain both degrade drastially. et the width of the transistor M3 be fration of M width so as IV. RESUTS AND DISUSSIONS Using a standard MOS 90nm gpdk proess the NA is designed and implemented for.5754ghz with sensitivity analysis. The designed NA is simulated using adene RF spetre simulator. With an input signal whose amplitude is - 5.9dBm, Noise Figure and S-Parameters are alulated with respet to the fundamental frequeny. by mathing the input and output ports with 50Ω impedane. In this paper, a urrent mirror iruit is used to provide the biasing for M. Without urrent mirror iruit whih is used for biasing M transistor we an get better NF but extra power supply is required for biasing M. The results are ategorized into following subsetions. A. Noise Figure With minimum number of fingers for M and M that is for widths of M and M=.3447mm, minimum 45 fingers are required beause the maximum width allowed by the tool per finger is 30um. This gives a NF of 934.3mdB for M3=500µm. In Fig. 3 we an observe the NF variation with respet to frequeny. For low input power NF analysis in RF spetre simulator was used. For bloking apaitor PMOS apaitane is used instead of metal apaitane as metal apaitane giving more Noise Figure. B. inearity Ative RF devies are ultimately non-linear in operation. When driven with a large enough RF signal the devie will generate undesirable spurious signals. The amount of spurious signals generated by the devie is dependent on the linearity of the devie. db ompression point and IIP3 (III order input interept point) are the figure of merits for linearity of the NA. to overome the power overhead of the bias iruit [4]. STEP 4: Find 3,, R using parallel R tank iruit at resonant frequeny This is given by: 0 where f GHz, Fig.3. NF Vs frequeny 74

4 ISSN: ISO 900:008 ertified Volume, Issue 5, November 0 If an amplifier is driven hard enough the output power will begin to roll off resulting in a drop of gain known as gain ompression. The measurement of gain ompression is given by the db gain ompression point. IIP3 (III order input interept point) indiates how well a reeiver performs in the presene of strong nearby signals. Periodi Steady State Analysis (PSS) is used for large signal analyses, as the iruits are linearized around the periodi steady state operating point. The IIP3 is a measure of linearity, whih is a standard measure in RF iruits. The higher the IIP3 of NA, the better its linearity. For this NA iruit, the value of IIP3 obtained was.65db as shown below in Fig 4.. S-Parameters Simulation results for S-parameters are shown in Fig 5. and are plotted against frequeny. The return loss (S) is estimated for the design under test and is found to be loser to -6.4 db and the orresponding VSWR is <.7:. The initial speifiation of the design is expeted to yield a VSWR of <: and the results show a better performane Fig.4 Third Order Input Interept Point (IIP3) than the expeted. The gain (S) of the NA when measured with port is observed to be 4. 63dB. Port was given 50Ω impedane during simulation. ikewise, S and S are also alulated for the design. The results furnished in the above setion are summarized in the table. The table also gives a omparative study on the various parameters with respet to the literature [-4]. Fig. 5 S-parameters Vs Frequeny Table I: Speifiations of the proposed NA SPEIFIATION [] [3] [4] THIS WORK Tehnology 90nm 80nm 80nm 90nm Operating frequeny (GHz) S(dB) <-9 -. NA S(dB) <-5 NA NA -0 IIP3(dB).33 NA NF(dB) Power Supply (V) Gain(dB) Power dissipation (mw) NA

5 ISSN: ISO 900:008 ertified Volume, Issue 5, November 0 V. ONUSION A low voltage MOS NA at.5754ghz was designed using MOS 90nm gpdk proess with RF-spetre iruit simulator. The designed NA exhibits a gain of 4.63dB; S of db, and a positive IIp3 equal to.57db. This NA performane represents high voltage gain, low power supply voltage, low noise figure, and low power dissipation. The designed NA ould be fabriated without any off-hip omponents. REFERENES [] Boso eung, VSI for Wireless ommuniations, Prentie Hall Eletronis and VSI series harles G.Sodini. [] Vaithianathan Venkatesan, A 3 4 Ghz ow Noise Amplifier For Ultra Wide Band Appliations, International Journal of VSI design & ommuniation Systems (VSIS) Vol.3, No., February 0. [3] Ravinder Kumar, Design and Noise Optimization of RF ow Noise Amplifier for IEEE Standard 80.a WAN, International Journal of VSI design & ommuniation Systems (VSIS) Vol.3, No., April 0. [4] Srinivas Jagarapu A.4 GHz ow Noise Amplifier in 0.8µm MOS Tehnology International onferene on VSI, ommuniation & Instrumentation (IVI) 0 Proeedings published by International Journal of omputer Appliations. [5] B. Razavi, MOS tehnology haraterization for analog and RF design, IEEE J. Solid-State iruits, vol. 34, pp , Mar [6] Baimei iu, et al.,009, An Ultra-ow Voltage and Ultra- ow Power.4GHz NA Design, Radio Engineering, vol.8, No.4, pp [7] Wei-Hung hen; Gang iu; Zdravko, B.; Niknejad, A.M.; A Highly inear Broadband MOS NA Employing Noise and Distortion anellation, Radio Frequeny Integrated iruits (RFI) Symposium, 007, IEEE, vol., no., pp.6-64, 3-5 June