5.8 Gb/s 16:1 multiplexer and 1:16 demultiplexer using 1.2 m BiCMOS

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1 Downloaded from orbit.dtu.dk on: Mar 13, Gb/s 16:1 multiplexer and 1:16 demultiplexer using 1.2 m BiCMOS Midtgaard, Jaob; Svensson, C. Published in: Proeedings of the IEEE International Symposium on Ciruits and Systems Link to artile, DOI: 1.119/ISCAS Publiation date: 1994 Doument Version Publisher's PDF, also known as Version of reord Link bak to DTU Orbit Citation (APA): Midtgaard, J., & Svensson, C. (1994). 5.8 Gb/s 16:1 multiplexer and 1:16 demultiplexer using 1.2 m BiCMOS. In Proeedings of the IEEE International Symposium on Ciruits and Systems (Vol. Volume 4, pp ). IEEE. DOI: 1.119/ISCAS General rights Copyright and moral rights for the publiations made aessible in the publi portal are retained by the authors and/or other opyright owners and it is a ondition of aessing publiations that users reognise and abide by the legal requirements assoiated with these rights. Users may download and print one opy of any publiation from the publi portal for the purpose of private study or researh. You may not further distribute the material or use it for any profit-making ativity or ommerial gain You may freely distribute the URL identifying the publiation in the publi portal If you believe that this doument breahes opyright please ontat us providing details, and we will remove aess to the work immediately and investigate your laim.

2 43 5.8Gb/s 16: 1 Multiplexer and 1 : 16 Demultiplexer Using 1.2pm BiCMOS Jaob Midtgrtvd Center for Integrated Eletronis Inst. of Computer Siene Bld. 344 Tehnial University of Denmark Denmark (45) jaob@id.dth.dk Christer Svensson Eletroni Devies Dept. of Physis 'and Measurement Tehnology Linkoping Institute of Tehnology S Linkoping Sweden (46) hs@ifm.liu.se ABSTRACT High speed time-division multiplexers 'and demultiplexers are important omponents of modem optial ommuniation systems. They are needed to parallelize the d m to allow most of the system to operate at muh lower speeds. This p'aper desribes a 16:l multiplexer and a 1:16 demultiplexer implemented on one IC in a 1.2pm BiCMOS proess. The IC ombines fast ECL iruits with CMOS iruits, demonstrating that by utilizing the ombination of bipolar 'and MOS transistors, a VLSI iruit with very high speed interfae is feasible. INTRODUCTION In high speed optial ommuniation systems multiplexers 'and demultiplexers are used to redue the part of the system whih must operate at the very high speed of the serial link. Most of the system will proess the dm several bits in parallel. With the inreasing requirements for omplex real time proessing of the tr'ansmitted d m that omes with the adv'aned low level ommuniation protools. suh as ATM (Asynhronous Tr'ansfer Mode), the size of the hardware part of the ommuniation system that works diretly with the transmitted data inreases. The bipolar 'and GaAs proesses that offer the speed needed in the multiplexers and demultiplexers do not offer the very high levels of integration needed to h'andle the ommuniation protool. On the other hand CMOS, whih offers the high integration, is apable of operating at the speed (1-4OOMHz) needed for handling the protools on parallel data [ 11, [2], but does not offer the speed needed in the multiplexers 'and demultiplexers. From this viewpoint an obvious hoie would be BiCMOS, whih offers both the high speed of bipolar iruits 'and the high level integration of CMOS iruits. The hoie of a BiCMOS proess is not without penalty. The performane of the bipolar transistors in presently available BiCMOS proesses is not omparable to that of advraned Rb j js ft B 1SSJ 67fF 78fF 7.8GHz 8 Table 1: Typial BJT parameters at VCB = 1.6V 'and V(.S = 4v. bipolar proesses. BiCMOS proesses with transition frequenies up to 15GHz have been reported [3], [41, while advaned bipolar proesses reah transition frequenies of more than 4SGHz [SI. But even with these BiCMOS proesses both all urrently used ommuniation speeds and the next generation (logb/s) are reahable. The proess used in the design presented here is not advaned, with an ft of only 7.8GHz. Table 1 summarizes some of the dmi for the bipolar tr'ansistors with two base ontxts 'and a 1.2pm x lpm emitter. The "xmum speed of both the multiplexer (S.8Gb/s) and the demultiplexer (6.9Gb/s), relative to the ft of the transistors, ompares very losely with other published results [SI. MULTIPLEXER ARCHITECTURE The multiplexer output is not retimed and therefore the lok frequeny need only be half the output bit rate, limiting the frequenies that need to be h,andled when pakaging. Figure 1 shows a simplified blok diagr'm of the multiplexer. The stippled line represents the approximate borderline between CMOS 'and ECL iruits. Inserted in figure 1 the topology of the 2:l multiplexers is shown. The 2:l multiplexing is performed by first retiming the two signals from the previous multiplexer, then skewing one of them half a lok yle, 'and finally seleting eah in turn with the lok signal. The 6rst olumn of 2:l multiplexers ontain extra layers of lathes to obtain a flip-flop like funtion for all inputs. These inputs are first lathed in CMOS, and then onverted to ECL levels in the seletor of the 6rst stage. This seletor is an

3 a CMOS ; ECL 2:i 2:l v) 3 a.- m (II n 2:l Multiplexer p y k Q Clk out * Clok Figure 1: Multiplexer arhiteture. MCSL gate (Merged Current Swith Logi) providing both CMOS,and ECL inputs, and ECL outputs. The lok divider generating lok signals for this SUge has outputs for both CMOS and ECL levels. as the MCSL seletor needs ECL levels on the lok inputs. All following stzzges are implemented fully in ECL. The maximum speed of the omplete multiplexer is determined by the seletor in the last 2:l multiplexer. This seletor, the output driver, and the lok input buffer, are the only p ms swithing at the full lok frequeny. SL-l on-hip, termination was used for all high speed inputs and outputs. This has been shown to effiiently redue refletions and the importane of pakaging parasitis as ompared to off-hip termination [6]. 44 Both the lathes in the first 1:2 demultiplexer and in the 6rst lok divider are loked at the full lok frequeny. All other parts of the demultiplexer are loked at a lower frequeny. The maximum input data rate is therefore set by the highest lok frequeny that an be applied to a hain of lathes. Delaying the lok signal between eah level of lathes in the input demultiplexer would not improve the speed, as the lok divider still sets the same limit. As for the multiplexer, on-hip termination was used for both data and lok inputs. GATE DESIGN Several different logi types are used in the design. For all logi types automati optimization was used to guide the gate design. To shorten the design time a limited number of speed/power lasses of the gates was used. This has of ourse resulted in exessive power onsumption and area For the fastest stzzges of both multiplexer and demultiplexer ECL gates with double emitter followers were used. This allows a redution of the load on the intemal nodes where the onversion from urrent to voltage signal ours, and inrease the olletor-base voltage of following stages. Figure 3 shows a shemati for the fastest seletor used in the multiplexer. To redue the delay in this ritial gate, a signal swing of only 3OOmV was used, ompared to the minimum of 4mV used for all other ECL gates. Two weak urrent soures were added to draw a small urrent through eah of the two top-most urrent swithes, reduing the swing on the ommon emitter nodes. Where the highest speed was not needed simpler gates 1 :2 Demultiplexer IQ ECL CMOS DEMULTIPLEXER ARCHITECTURE The demultiplexer onsists of a tree of 1:2 demultiplexer bloks with 4 levels as shown in figure 2. The stippled line indiates the borderline between ECL and CMOS iruits. The 1:2 demultiplexers all have the topology shown inserted in figure 2. The atual demultiplexing is done by leading the input to two lathes loked on opposite edges. An extra lath in one half aligns the signals to have the same phase at the outputs. As both edges of the lok signal are used, a lok frequeny of only half the bit rate is needed, as was the ase for the mu1 tiplexer. In Clok * Figure 2 Demultiplexer arhiteture.

4 45 Figure 3: Fast ECL seletor!i YE 5 G " d Figure 5: ECL-CMOS interfae iruits; (a) MCSL seletor, (b) ECL-CMOS onverter (4 (b) Figure 4: CMOS lathes: (a) TSPC lathes, (b) two phase lath. with only one emitter follower was used. Differential signals were used in all the ECL gates. For most of the CMOS p'ms the TSPC lathes (True Single Phase Clok) shown in figure 4(a) were used. These are exarnples of a family of CMOS iruits that 'an work at high speeds using only one lok phase (in this ase 36OMHz) [7]. Beause of the large delay in onverting the lok signal from ECL to CMOS signal levels, a lath with a smaller delay and a lower load on the lok signal was needed for the lathes just before the onversion to ECL in the multiplexer. This lath, shown in figure 4(b), needs to lok phases. These are easily generated in parallel when onverting from ECL to CMOS lok signals, and are only distributed loally with very good ontrol over the setup 'and hold times of the input signals to these lathes. The onversion from CMOS to ECL signal levels is the fastest and least power onsuming of the two onversions involved in the ECL/CMOS interfae. It is performed by using M MCSL gate. Figure S(a) shows the shemati for the MCSL seletor. used in this design. It is a simple replaement of some of the bipolar transistors in an ECL gate, with MOS transistors. The speed of this gate is very lose to that of the fully bipolar gate. The onversion from ECL to CMOS signal levels is the weakest part of the ECLKMOS interfae. It is both slow and power onsuming. Figure 5(b) shows the shemati for the onverter I used in this design. It is not the fastest onfiguration, but it is also not the most power onsuming. The input omes from M ECL lath with a large output swing of 1.6V. As used in the last lok divider of the multiplexer, it diretly drives the last CMOS lath of every input, plus a driver, whih in turn drives the rest of the CMOS lathes. This 'approah is only feasible for very small iruits. For large iruits an effiient <appro,?h ould be to buffer the onverted signal heavily, then reonvert to ECL and use a phase lok to adjust the phase of the buffered CMOS signal to be very lose to the ECL lok signal. SIMULATED PERFORMANCE For simulations a single ended lok signal with a sinus waveform,and a peak to peak amplitude of 8mV was use for both multiplexer and demultiplexer. When fabriated, the IC's will be pakaged in multilayer erami pakiges with SOQ transmission lines from the pakage bond pad to the pakage lead. To take into aount mounting parasitis, a die bond pad apaitane of SO@, a bonding wire indutane of 2n, and a pakige bond pad apaitane of lp were added to all inputs <and outputs. Spie simulations under typial onditions predit that at 5.8Gb/s the minimum output amplitude of the multiplexer is only redued by 15%. The demultiplexer is simulated to work up to 6.9Gb/s with a4mv swing <and 14OpS rise time on the ditzi inputs. Table 2 lists the power onsumption in various parts of the design. The lok dividers are inluded in the stage they drive. CONCLUSIONS The design presented here ombines very high speed bipolar iruits with high speed CMOS iruits, demonstrating that very high speed on-hip bipolar interfaes to CMOS iruits

5 46 Slow Toti-- Multiplexer Demultiplexer 97mW 37mW 32mW 27mW 2SmW 49mW 37mW (24mW) 23mW (14mW) 1.91W 1.36W Table 2: Power onsumption. Numbers in parenthesis are without ECL U buffers. [6] J. Himenshild and H.-M. Rein, Influene of u,msmission-line interonnetions between gigabit-perseond IC s on time jitter and instabilities, IEEE Jurnal of Solid State Ciruits, vol. 25, pp , June 199. [7] J. YU I and C. Svensson, High speed CMOS iruit tehnique, IEEE Jurnal of Solid State Ciruits, vol. 24, pp. 62-7, Feb may be onstruted using present BiCMOS tehnologies. The power onsumption is omparable to other bipolar designs designed for the highest possible speed. To really utilize the high integration apability of the CMOS,,an IC might need several high speed inputs md outputs. This puts some onstraints on the available power for e xh high speed interfae. But as the power onsumption an be redued drastially when just reduing the speed slightly, a single IC with severd 2.SGbls inputs and outputs is possible even in the proess used in this design. With the more adv,aned.8pm and.spm BiCMOS proesses, IC s with several inputs and outputs asgb/s or more would be possible with reasonable power onsumption. With the present tehnologies BiCMOS iruits <an not replae pure bipolar iruits at the speeds of the future generations of optial ommuniation systems. But BiCMOS iruits ould have an important plae in ommuniation systems at speeds from SOOMb/s to 1Gb/s. REFERENCES R. H. Hofmann and R. Muller, A multifuntional high-. speed swith element for ATM appliations, IEEE Jurnal of Solid State Ciruifs, vol. 27, pp O4, July K. S,&aue et al., A.8pm BiCMOS ATM swith on,an 8Mb/s asynhronous buffered b,any,an network, IEEE Jurnal of Solid State Ciruits, vol. 26, pp , Aug A. A. Iranm,ulesh et al., A O.8pm advaned singlepoly BiCMOS tehnology for high-density and highperform appliations, IEEE Jurnal of Solid State Ciruits, vol. 26, pp , Mar J. D. Hayden et al., Integration of a double-polysilion emitter-base self-digned bipolar transistor into a.5pm BiCMOS tehnology for fast 4Mb SRAM s, IEEE Transationson Eletron Devies, vol. 4, pp , June A. Felder et al., 25 to 4Gb/s Si IC s in seletive epimid bipolar tehnology, in ISSCC 93 Digest of Tehnial Papers, pp ,1993.