IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 2, FEBRUARY

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1 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 2, FEBRUARY A Global Interonnet Optimization Sheme for Nanometer Sale VLSI With Impliations for Lateny, Bandwidth, and Power Dissipation Man Lung Mui, Kaustav Banerjee, Senior Member, IEEE, and Amit Mehrotra, Member, IEEE Abstrat This paper addresses the ritial problem of global wire optimization for nanometer sale very large sale integration tehnologies, and eluidates the impat of suh optimization on power dissipation, bandwidth, and performane. Speifially, this paper introdues a novel methodology for optimizing global interonnet width, whih maximizes a novel figure of merit (FOM) that is a user-defined funtion of bandwidth per unit width of hip edge and lateny. This methodology is used to develop analytial expressions for optimum interonnet widths for typial FOMs for two extreme senarios regarding line spaing: 1) spaing kept onstant at its minimum value and 2) spaing kept the same as line width. These expressions have been used to ompute the optimal global interonnet width and quantify the effet of inreasing the line width on various performane metris suh as delay per unit length, total repeater area and power dissipation, and bandwidth for various International Tehnology Roadmap for Semiondutors tehnology nodes. Index Terms Bandwidth, ritial indutane, delay per unit length, global interonnet optimization, interonnet power dissipation optimization, International Tehnology Roadmap for Semiondutors (ITRS), optimal buffering, tehnology saling. I. INTRODUCTION WITH aggressive saling of CMOS tehnology, gate delay, and loal wire delay dereases rapidly [1]. However, the delay of global interonnets inreases with tehnology saling [1] [4] beause the global interonnet lengths tend to inrease with saling. Repeater insertion is generally used to redue the delay of long global interonnets [5]. However, with aggressive saling of global interonnet dimensions to meet the inreased onnetivity demands in a high performane system-on-a-hip (SoC), the interonnet delay per unit length of optimally buffered minimum sized global wires is also inreasing with tehnology saling [6]. Therefore, global interonnets tend to limit the performane of high-performane SoCs. Manusript reeived February 24, 2003; revised September 23, This work was supported in part by the University of Illinois and by the University of California-MICRO program. The review of this paper was arranged by Editor R. Singh. M. L. Mui and A. Mehrotra are with the Coordinated Siene Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL USA ( manmui@uiu.edu; amehrotr@uiu.edu). K. Banerjee is with the Department of Eletrial and Computer Engineering, University of California at Santa Barbara, Santa Barbara, CA USA ( kaustav@ee.usb.edu). Digital Objet Identifier /TED In order to ahieve improvement in performane, designers tend to use wires whih are wider than minimum-sized global interonnets presribed by the tehnology. Inreasing the width of the interonnet proportionally redues its resistane per unit length and also inreases the line apaitane per unit length. However, for global interonnets in nanometer tehnologies, the aspet ratio of wires is approximately 2 2.5, the inrease in width results in a redution in the resistane apaitane (RC) time onstant of the line and therefore improves delay per unit length [7]. However, these fat wires take up a lot of routing resoures and using fat wires an adversely affet the wireability of the hip. For further improvement in performane, the spaing of global interonnets an also be inreased whih, to some extent, offsets the inrease in line apaitane due to inreasing line width. However, this inrease in spaing will further degrade the wireability of the hip. Furthermore, the delay per unit length for wide wires may degrade due to indutane effets as well. Therefore, in determining the wire widths at the global tier, the number of interonnets per unit hip edge should also be taken into aount along with the delay per unit length. For instane, the ratio of the number of interonnets per unit hip edge and the delay per unit length, whih represents the rate of data transfer per unit hip edge, an be a useful metri to optimize. This paper introdues a new methodology for determining the optimum width of global interonnets for a given tehnology, whih maximizes a user-defined figure of merit (FOM), whih is a known funtion of delay per unit length and the rate of data transfer per unit hip edge. As a first step, we develop semi-analytial expressions for line apaitane per unit length as a funtion of line width and spaing. Using these models, in Setion II we obtain the funtional dependene of delay per unit length of an optimally buffered interonnet online width. This, in turn, results in the funtional dependene of the given FOM on the line width whih is analytially optimized to yield the optimum interonnet width. We arry out this optimization for various FOMs and various International Tehnology Roadmap for Semiondutors (ITRS) tehnology nodes for two extreme senarios: 1) Interonnet spaing is kept at its minimum, and 2) interonnet spaing is kept equal to the interonnet width. The optimization results indiate that the rate of data transfer per unit hip edge is very lose to optimum when the line width is minimum as presribed by the ITRS. However, in order to optimize a different FOM, line width needs to be inreased. We also quantify the improvement in delay per unit length, total repeater /04$ IEEE

2 196 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 2, FEBRUARY 2004 R tr rh h V st V tr C P h C L (a) (b) Fig. 1. Interonnet of length h between two idential inverters. (a) Shemati representation. (b) Equivalent RC iruit. area and power dissipation and the degradation in the per unit width bit transfer rate for this optimum width ompared to minimum width lines. We show that these improvements are fairly insensitive to tehnology saling. Metal n + 1 C intralevel W II. METHODOLOGY Consider a uniform interonnet of resistane per unit length and apaitane per unit length buffered by idential repeaters as shown in Fig. 1. Assume that for a minimum sized repeater, the input apaitane is, the output parasiti apaitane is and output resistane is. Therefore for a repeater of size, the total output resistane, the total output parasiti apaitane and the total input apaitane is. If the line segment is of length and the repeater size is, then the time-onstant of that segment is [8] and the lateny or the delay of that setion is. Now onsider a long interonnet of a given length whih is uniformly buffered with inter-buffer interonnet length. Therefore the total number of segments is. The total delay through that line is given by is the delay per unit length whih is given by Note that optimizing the delay of the interonnet of a fixed length is equivalent to optimizing. This delay per unit length is optimal when and is given by Note that this optimal delay per unit length is a funtion of interonnet parameters and whih in turn are a funtion of interonnet width and spaing. In the present study we are not expliitly onsidering ross-talk. The effet of ross-talk would be to hange the value of depending on whether the neighboring interonnets are quiet or are making a transition. For Fig. 2. Metal n Metal n 1 C interlevel VLSI interonnet ross setion (not to sale). global interonnets, this assumption is somewhat justified beause long global interonnets would be properly shielded to yield preditable delays and therefore an be assumed to be a funtion of interonnet geometry only. Earlier studies for quantifying the optimal buffering shemes for optimal delay per unit length [5] always onsidered minimum sized global wires. However, for further improvement in performane, the designers have a option of inreasing the wire width and/or spaing. This inrease in for a given will result in a derease in line resistane per unit length and an inrease in line apaitane per unit length. However, the derease in is muh more than the inrease in and therefore the optimal delay per unit length will derease. However, inreased pith will imply a derease in wireability of the hip. Some previous work suh as [9] an be found in the literature on wire sizing for delay and power optimization. However, these authors onsidered a disrete set of wire widths and also negleted both the leakage and the short-iruit power in their power estimations. Wire width optimization has also been onsidered by [10], and [11]. However, as pointed out in the next paragraph, the model for interonnet tehnology in [10] is not realisti and the metri for optimization in both these approahes is also not flexible and is not appliable for a wide variety of design harateristis and hene their optimization results may not be meaningful. Furthermore [11] do not provide any model for the interonnet delay and power dissipation and therefore their formulation is not very transparent. We will onsider two senarios. In the first ase, line width an be hanged but the line spaing is kept onstant at.in this ase, inreasing the wire width will not strongly degrade the wireability of the hip. In the seond ase, the line spaing will be kept the same as line width for all. The seond ase is a less popular option for designers but will at as a limiting ase. We assume that the line thikness and the interlayer dieletri thikness (Fig. 2) annot be hanged. This is in ontrast S T Tins

3 MUI et al.: GLOBAL INTERCONNECT OPTIMIZATION SCHEME FOR NANOMETER SCALE VLSI 197 with [10] it was assumed that and an be arbitrarily varied, whih is not realisti, sine, for a given proess tehnology and a given layer, and typially annot be hanged by the designers while they are free to hoose any and. It has been shown that with ITRS saling sheme, the minimum sized global interonnets are beoming inreasingly resistive and the indutive effets are dereasing rapidly [12]. It was also shown that indutive effets on delay may beome signifiant only if line widths are greater than. Therefore, initially we will assume that indutane effets an be ignored for the purpose of delay and power dissipation alulation and verify for the omputed optimum line widths whether this is indeed the ase or not. Let denote the bandwidth, i.e., the rate at whih bits an be transmitted aross a unit length of interonnet in a given hip edge or width. The rate at whih bits an be transmitted per unit length by one interonnet is inversely proportional to the delay per unit length, i.e., rate bit of transmission Line apaitane per unit length is also a funtion of, i.e.,. Using the above, the expression for the optimal delay per unit length in terms of an be written as is a onstant for the given metal layer. Therefore FOM Setting the derivative of this with respet to that satisfies the following equation to zero, it follows We assume that the lines are always optimally buffered for a given line width. Therefore rate bit of transmission The number of suh lines present in a given hip edge is Note that the optimum width is only dependent on line apaitane and line spaing. The optimum delay per unit length for this optimum line width is given by (1) hip edge metal pith and metal pith. Therefore The aim of a global interonnet design sheme is to have a large while having a small delay per unit length. As an example, an appropriate FOM to maximize an be for some. Larger values of would imply more importane to delay per unit length at the expense of the rate of bit transfer per unit width. In our study we arry out the analysis for, 1, and 2. In other words FOM As expeted, as inreases, the delay dereases and asymptotes to a onstant value for large values of. The interbuffer interonnet length an be written in terms of interonnet width as As the optimum line width inreases, the interbuffer interonnet length inreases initially and then asymptotes to a onstant. This implies that for a given line length, the number of repeaters redues. The buffer size is given by The repeater area of a single interonnet is proportional to and is inversely proportional to, i.e., Line resistane per unit length width is inversely proportional to line repeater area of a single interonnet The total repeater area for a given metal layer is the produt of the number of interonnets and the repeater area of a single

4 198 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 2, FEBRUARY 2004 interonnet. The number of interonnets on a metal layer is inversely proportional to the pith. Therefore Power dissipation per unit length for a single line is given by [13] short iruit Here, is the power supply voltage, is the lok frequeny, is the swithing fator (or ativity fator), whih is the fration of repeaters on a hip that are swithed during an average lok yle, is the leakage urrent per unit NMOS (PMOS), is the width of the NMOS transistor in minimum sized inverter, and short iruit is the per unit width short iruit urrent. We assume, short iruit and. The total power dissipation per unit length in global interonnets of a given layer is the produt of the above quantity with the number of global lines whih is inversely proportional to. The total power dissipation an be expressed as of minimum sized global interonnets is two to three, the interlayer dieletri thikness is 2 3 times larger than the minimum inter-wire spaing on a given metal layer and the adjaent metal layers are orthogonal to eah other [1] it implies that is typially muh larger than (Fig. 2). Therefore, inreasing the line width without hanging the spaing is not going to signifiantly inrease the interonnet apaitane. For instane, as shown in Fig. 3, for the 130 nm tehnology, if the global line width is inreased from to, the interonnet apaitane per unit length inreases only by 22%. This is due to the fat that the parallel plate omponent of to the upper and lower metal layers, whih is proportional to line width, is a small fration of the total line apaitane for a minimum sized wire (Fig. 2). Line apaitane per unit length an be written as represents the total fringing apaitane and sidewall apaitane whih is independent of and represents the parallel plate apaitane to the top and bottom layers. Also. Therefore from (1) Note that for, the FOM is the rate of bit transfer per unit width itself. Therefore for minimum spaed lines, the rate of bit transfer per unit width itself has a maximum for a partiular line width given by the above expression. This is in sharp ontrast to the findings in [10], it was reported that asymptotes to a fixed value as width dereases. B. Line Spaing Equal to Line Width This ase is similar to the previous one exept that the line apaitane is given by Note that this has the same form and the dependene of total repeater area on line width. Therefore inreasing the line width dereases both total repeater area and power dissipation by the same amount. We now onsider the following two ases separately. 1) Minimum-spaed lines. 2) Line spaing is the same as line width. A. Minimum-Spaed Lines In an interonnet system, the tehnology determines the interlayer dieletri thikness, the metal line thikness, minimum metal width and the minimum spaing at a given metal layer. For higher performane or throughput, one an inrease the line width in order to derease the line resistane. However, in order not to severely limit the wireability of the hip, the wires should be minimum spaed. This is speially true for deep submiron tehnologies the designs are mostly wire-limited at the global tiers. Sine the aspet ratio the first term represents the onstant fringing apaitane, the seond term represents the parallel plate apaitane to top and bottom layers of metal whih is proportional to the width and the last term represents the parallel plate apaitane to the neighboring wires whih is inversely proportional to the spaing. Also. For this ase, from (1) For, the optimum width is zero, whih means that the FOM whih is also the rate of bit transfer per unit width keeps inreasing as redues and should be kept minimum sized for maximum. III. PARAMETER EXTRACTION We used FASTCAP [14] to extrat the apaitane per unit length for global interonnets for ITRS2001 tehnology nodes up to 45 nm. For both ases, (i.e., when lines are assumed to be minimum spaed and when line spaing is equal to

5 MUI et al.: GLOBAL INTERCONNECT OPTIMIZATION SCHEME FOR NANOMETER SCALE VLSI FASTCAP simulated model TABLE I TECHNOLOGY AND EQUIVALENT CIRCUIT MODEL PARAMETERS FOR TOP LAYER METAL FOR DIFFERENT TECHNOLOGY NODES BASED ON THE ITRS 2001 (ff/mm) line width (nm) Fig. 3. FASTCAP simulated and fitted data for as a funtion of W for 130-nm global line with S = W. (ff/mm) FASTCAP simulated model line width (nm) Fig. 4. FASTCAP simulated and fitted data for as a funtion of W for 130-nm global line with S = W. line width), apaitane per unit width was extrated using FASTCAP for a dense three layer interonnet mesh and,,, and were obtained by urve fitting. Figs. 3 and 4 show the FASTCAP and the urve fitted values for the 130 nm tehnology node. It an be observed that the line apaitane model fits the FASTCAP simulated data very well. Similar agreement was obtained for other tehnology nodes. Devie parameters were extrated using SPICE simulation similar to [12]. A five stage ring osillator with a given length of global interonnet of width in between eah stage was simulated. The interonnet length and inverter size were varied to obtain the minimum stage delay per unit length., and were alulated from these values of, and. IV. RESULTS The methodology outlined above was used to optimize global interonnet width for maximum FOM for ITRS 2001 tehnology nodes up to 45 nm. Devie models were found to be extremely unreliable at 32 nm and 22 nm nodes and therefore were not inluded in this study. NMOS and PMOS off urrents Teh. node (nm) width (nm) thikness (nm) t ins (µ) r a (ff/mm) (ff/µ 2 b ) ' a (ff/mm) ' (ff/µ 2 b ) (ff) r s (kω) (ff) p (ff) V DD (V) I off n (µa/µ) I off p (µa/µ) f lk (GHz) TABLE II RATIO OF OPTIMUM INTERCONNECT WIDTH FOR VARIOUS TECHNOLOGY NODES WITH W Teh. S = W min S = W node (nm) i = 0 i = 1 i = 2 i = 1 i = were estimated similar to [15]. The relevant tehnology parameters are shown in Table I. was assumed to be equal to aross all tehnology nodes. Table II shows the alulated optimum width as a ratio of for various tehnologies for all ases. Note that for minimum spaed lines the optimum value of whih maximized is approximately 13% less than for all tehnologies. This is learly not feasible, however, as shown in Fig. 5, is only 0.3% lower at than the optimal value. This was also found to be true aross all the tehnologies onsidered. Also note that for all ases, the optimum interonnet width is less than so indutane effets are not signifiant. To further verify this, Fig. 6 plots the ritial indutane (see Appendix) as a funtion of line indutane for minimum width and 7.5 minimum width global line for 130 nm tehnology node. As pointed out in [12], if line indutane is less than then the interonnet system is overdamped and indutive effets are negligible. From Fig. 6, we observe that even for, the interonnet is overdamped for most pratial range of line indutane values nh/mm). However, this may not be true for. Further, note that values are similar aross all tehnology nodes when line spaing is kept minimum for

6 200 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 2, FEBRUARY 2004 data rate per unit width (ψ/ψ(w min )) line width ratio (W/W min ) Fig. 5. Data rate per unit width as a funtion of line width for minimum spaed lines in 180-nm tehnology node. Fig. 6. l rit (nh/mm) lrit for w=w opt l 0.5 rit for w=w min line indutane line indutane (nh/mm) Critial indutane as a funtion of line indutane for minimum spaed 130-nm global interonnet of W = W and W = 7:5 W. TABLE III RATIO OF OPTIMUM DELAY PER UNIT LENGTH AT W = W WITH OPTIMUM DELAY PER UNIT LENGTH AT W = W Teh. S = W min S = W node (nm) i = 1 i = 2 i = 1 i = and 2, while they inrease with tehnology saling when line spaing is equal to line width. Also note that we have not inluded the trivial and infeasible result for and. Also for and, the FOM at is only 0.3% lower than the optimal value at whih is approximately. In the following series of results (shown in Tables III VI) we always report the ratio of performane metris at and the orresponding value at. Therefore we will exlude ase for from now on. Table III shows the optimum delay per unit length at as a fration of the optimum delay per unit length when TABLE IV RATIO OF TOTAL REPEATER AREA AT A GIVEN LEVEL AT W = W WITH TOTAL REPEATER AREA AT A GIVEN LEVEL AT W = W Teh. node (nm) S = W min S = W i = 1 i = 2 i = 1 i = TABLE V RATIO OF AT W = W WITH AT W = W Teh. S = W min S = W node (nm) i = 1 i = 2 i = 1 i = TABLE VI RATIO OF OPTIMIZED FIGURE OF MERIT AT W = W WITH FIGURE OF MERIT AT W = W Teh. S = W min S = W node (nm) i = 1 i = 2 i = 1 i = As expeted, inreasing the width of the wires redues the delay per unit length signifiantly. Note that when the line width is inreased from to, (orresponding to for both ases in Table II), the delay improvement is signifiant. However, as the line width is inreased further to 7 8 (orresponding to for both ases in Table II), the inremental improvement in delay is not as signifiant. This is expeted sine and as beomes very large, the line apaitane is dominated by the parallel plate omponent of, i.e.,. Also note that the relative improvements in delay are not very sensitive to tehnology saling. Table IV shows the total repeater area for all interonnets at the global tier when as a fration of the total repeater area for all interonnets at the global tier when. As pointed out earlier, this fration is also the ratio of the total power dissipation of all repeaters at the global tier when and the total power dissipation of all repeaters at the global tier when. It an be observed that as the line width is inreased (as inreases as per Table II), the total repeater area (and power dissipation) dereases dramatially, even though the

7 MUI et al.: GLOBAL INTERCONNECT OPTIMIZATION SCHEME FOR NANOMETER SCALE VLSI 201 size and therefore the area (and power dissipation) of a single repeater inreases. This is due to the fat that the wider wires result in a large inrease in optimal interbuffer interonnet length and also fewer number of interonnets at a given tier. Therefore the total repeater power dissipation redues dramatially. Table V shows the rate of bit transfer per unit width at as a fration of at. As indiated in Fig. 5 peaks at and is only 0.3% lower at. Therefore if the primary goal of the design is to maximize, then minimum sized, minimum spae wires as presribed by the ITRS should be used. However, if the delay needs to be improved, then wire width should be inreased at the expense of. Note that the ratio of with and is fairly insensitive to tehnology saling. Table VI shows the ratio of the optimized FOM when and the FOM when. If this ratio was very lose to 1, it would imply that the above-mentioned optimizations were not signifiantly improving the user-speified FOM and therefore were not very useful. However, in Table VI we find that these ratios are very different from 1, indiating a nontrivial improvement in the FOM at ompared to whih further emphasizes the utility of these optimizations. Also note that exept for the seond ase with, the improvement in FOM at the optimum width is fairly insensitive to tehnology saling. V. CONCLUSION In onlusion, we have developed a new methodology for optimizing global interonnet width whih maximizes a userspeified FOM, whih is a funtion of the data-rate per unit hip edge and interonnet delay per unit length. Using this methodology we have developed expressions for optimum interonnet widths for typial FOMs for two extreme senarios regarding line spaing: 1) spaing kept onstant at its minimum value and 2) spaing kept the same as line width. We have used these expressions to ompute the optimal global interonnet width and quantified the effet of inreasing the line width on delay per unit length, total repeater area and power dissipation and bandwidth. As expeted, an inrease in the line width dereases the optimal delay per unit length (i.e., dereases lateny), total buffer area and power dissipation, but severely degrades the rate at whih bits an be transmitted per unit hip edge, i.e., bandwidth. We also observed that in most ases, the relative inrease in the line width (from to ), the relative improvement in delay per unit length, total repeater area and power dissipation, and the relative degradation in the datarate per unit hip edge are fairly insensitive to tehnology saling. Rs v i (t) C p rd ld d h rd ld d v o (t) C L Fig. 7. Equivalent iruit of a driver-interonnet-load segment. The interonnet is uniform with resistane, apaitane and indutane per unit length of r, and l respetively. This work will have signifiant impliations for signaling and design optimization for global interonnets in future nanometersale tehnologies. APPENDIX CRITICAL INDUCTANCE Consider a uniform line with resistane, apaitane and indutane per unit length of,, and, respetively, driven by a repeater of series resistane and output parasiti apaitane, and driving an idential repeater with load apaitane (Fig. 7). For a given tehnology, let the output resistane, output parasiti apaitane and input apaitane of a minimum-sized repeater be, and respetively. Therefore if the repeater size is times the size of a minimum sized repeater,, and. The transfer funtion derivation is outlined here from [12] for ompleteness. The ABCD parameter matrix for a uniform transmission line of length is given by [12] is the omplex frequeny, and Therefore the ABCD parameter matrix of the onfiguration in Fig. 7 is given by the equation shown at the bottom of this page, and the input-output transfer funtion is given by the first equation shown at the top of the next page. The step response of this system is given by in the Laplae domain. However, omputing the response in the time domain is

8 202 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 2, FEBRUARY 2004 analytially intratable. The above transfer funtion is therefore approximated by a seond order Padé approximation as The 50% delay is given by This transfer funtion an be used to alulate the 50% delay [16]. Long VLSI interonnets are typially broken up into buffered segment of equal lengths and driven by idential repeaters. For minimum total delay in these long interonnets, the delay per unit length in the optimally buffered segment should be minimized. The driver size and interonnet length an be numerially optimized to give minimum delay per unit length [16], [17]. The seond order transfer funtion given by (2) and disussed in [16], [17] an be ritially damped, overdamped, and underdamped when is equal to, greater than, or less than zero respetively. The response of an overdamped system is very similar to an RC line as for an underdamped system, the behavior is signifiantly different from an RC line, i.e., indutive effets are signifiant. Sine and are funtions of and and is a funtion of, it has been shown [16] that for optimum values of and interonnet delay is minimum for a given line indutane, a value an be obtained for whih the system will be ritially damped [16]. If line indutane is less than, the system will be overdamped as if line indutane is greater than, the system will be underdamped, as speified in the seond equation shown at the top of the page. (2) REFERENCES [1] International Tehnology Roadmap for Semiondutors (ITRS), [2] W. J. Dally, Interonnet-limited VLSI arhiteture, in Pro. IEEE Int. Conf. Interonnet Tehnology, 1999, pp [3] M. T. Bohr, Interonnet saling the real limiter to high performane ULSI, in IEDM Teh. Dig., 1995, pp [4] J. D. Meindl, Beyond moore s law: The interonnet era, Comput. Si. Eng., pp , [5] R. H. J. M. Otten and R. K. Brayton, Planning for performane, in Pro. Design Automation Conf., 1998, pp [6] K. Banerjee and A. Mehrotra, Indutane aware interonnet saling, in Pro. Int. Symp. Quality Eletroni Design, 2002, pp [7] C.-K. Cheng, J. Lillis, S. Lin, and N. Chang, Interonnet Analysis and Synthesis. New York: Wiley, [8] H. B. Bakoglu, Ciruits, Interonnetions and Pakaging for VLSI. Reading, MA: Addison-Wesley, 19. [9] J. Cong and C.-K. Koh, Simultaneous driver and wire sizing for performane and power optimization, IEEE Trans. VLSI Syst., vol. 2, pp , Apr [10] A. Naeemi and J. D. Meindl, Optimal global interonneting devies for GSI, in IEDM Teh. Dig., 2002, pp [11] T. Lin and L. T. Pileggi, Throughput-driven IC ommuniation fabri synthesis, in Pro. IEEE/ACM Int. Conf. Computer Aided Design, 2002, pp [12] K. Banerjee and A. Mehrotra, Analysis of on-hip indutane effets for distributed RLC interonnets, IEEE Trans.Computer-Aided Design, vol. 21, pp , Aug [13], A power-optimal repeater insertion methodology for global interonnets in nanometer designs, IEEE Trans. Eletron Devies, vol. 49, pp , Nov [14] K. Nabors and J. K. White, FASTCAP: a multipole-aelerated 3-D apaitane extration program, IEEE Trans. Computer-Aided Design, vol. 10, pp , Nov [15] V. De and S. Borkar, Tehnology and design hallenges for low power and high performane, in Pro Int. Symp. Low Power Eletronis and Design, 1999, pp [16] K. Banerjee and A. Mehrotra, Analysis of on-hip indutane effets using a novel performane optimization methodology for distributed RLC interonnets, in Pro. Design Automation Conf., 2001, pp [17], Aurate analysis of on-hip indutane effets and impliations for optimal repeater insertion and tehnology saling, in Pro. IEEE Symp. VLSI Ciruits, vol. 2001, pp Man Lung Mui was born in Hong Kong, China. He reeived the B.S. degree in eletrial engineering from the University of Illinois, Urbana-Champaign, in May 2002 and is urrently pursuing the M.S. degree in eletrial engineering with an emphasis in integrated iruit design. In 2002, he joined the Illinois Center for the Integrated Miro-Systems group, Coordinated Siene Laboratory, University of Illinois, as a Researh Assistant. His researh is fousing on interonnet performane and modeling for VLSI iruit designs.

9 MUI et al.: GLOBAL INTERCONNECT OPTIMIZATION SCHEME FOR NANOMETER SCALE VLSI 203 Kaustav Banerjee (S 92 M 99 SM 03) reeived the Ph.D. degree in eletrial engineering and omputer sienes from the University of California at Berkeley, CA, in He is an Assistant Professor in the Eletrial and Computer Engineering Department, University of California, Santa Barbara (UCSB), CA. He has held various aademi and industrial researh/visiting positions at Stanford University, Stanford, CA, Swiss Federal Institute of Tehnology (EPFL), Fujitsu, Intel and Texas Instruments. His present researh interests fous on a wide variety of nanometer sale issues in high-performane VLSI and mixed-signal designs, as well as on iruits and systems issues in emerging nanoeletronis. He is also interested in some exploratory interonnet and iruit arhitetures inluding 3-D ICs. At UCSB, he mentors six dotoral and two masters students. He also oadvises graduate students at Stanford University, University of Illinois at Urbana-Champaign, and EPFL-Switzerland. He has odireted two dotoral dissertations at Stanford University, and the University of Southern California. He has published over 85 sientifi papers in international journals and onferenes, and has presented numerous invited talks and tutorials. Dr. Banerjee served as Tehnial Program Chair of the 2002 IEEE International Symposium on Quality Eletroni Design (ISQED 02), and is the Conferene Chair of ISQED 04. He has also served on the tehnial program ommittees of the ACM International Symposium on Physial Design, the EOS/ESD Symposium, and the IEEE International Reliability Physis Symposium. He is the reipient of a Best Paper Award at the 2001 ACM Design Automation Conferene, and is listed in Who s Who in Ameria. Amit Mehrotra (S 96 M 99) reeived the B. Teh. degree in eletrial engineering from the Indian Institute of Tehnology, Kanpur, in 1994 and the M.S. and Ph.D. degrees from the Department of Eletrial Engineering and Computer Siene, University of California at Berkeley, in 1996 and 1999, respetively. In 1999, he joined the University of Illinois, Urbana-Champaign, he is urrently an Assistant Professor with the Department of Eletrial and Computer Engineering and a Researh Assistant Professor with the Illinois Center for Integrated Miro-Systems group at the Coordinated Siene Laboratory. His researh interests inlude RF, analog and mixed signal iruit design, for mobile ommuniation systems, simulation tehniques for RF and mixed signal iruits and systems, interonnet performane and modelling issues in VLSI and novel iruits and physial design issues for high performane VLSI designs, model-order redution of linear and nonlinear iruits. He has authored and oauthored over 30 tehnial papers in arhival journals and refereed international onferenes. Dr. Mehrotra has served as the Tehnial Program Committee member of International Symposium on Quality Eletroni Design in 2002 and He reeived best paper awards at the 1997 International Conferene on Computer Design and 2001 Design Automation Conferene.