A Novel Small-Signal Knowledge-Based Neural Network Modeling Approach for Packaged Transistors

Transcription

1 SR Journal o Eletrial and Eletronis Engineering (SR-JEEE) e-ssn: ,p-SSN: -, Volume, ssue 5 Ver. (Sep. t. 8), PP A Novel Small-Signal Knowledge-Based Neural Network Modeling Approah or Pakaged Transistors Shuxia Yan,, Xiaoyi Jin,, Yaoqian Zhang,, Weiguang Shi,, Jia Wen, Shool o Eletronis and normation Engineering, Tianjin Polytehni University, Tianjin, China Tianjin Key Laboratory o ptoeletroni Detetion Tehnology and System, Tianjin, China Corresponding Author: Weiguang Shi Abstrat : This paper proposes a novel small-signal knowledge-based neural network modeling method or pakaged transistors. Separate neural networks are proposed to represent the behaviors o pakages overing the ore transistor. An advaned training method is developed by utilizing the dierent parameters to adjust the dierent harateristis o the pakaged transistors, whih avoid parameter adjustment repeatedly and speed up the modeling proess. The proposed model ombing the neural networks with the ore transistor model is trained to present the entire small-signal behavior o the pakaged transistors. Measurement data o the radio requeny (RF) power laterally diused metal-oxide semiondutor (LDMS) transistor are used as the appliation example to veriy the apability o the proposed method. The results demonstrate that the proposed model is more aurate than existing models. Keywor - small-signal model, transistors, neural network, modeling Date o Submission: Date o aeptane: ntrodution With the development o eletroni tehnology, the aurate omputer-aided design (CAD) models o pakaged transistors play a deisive role in the iruit/system design [, ]. The equivalent-iruit-based model [] and Eletromagneti (EM) - based model [4] are good or modeling mature tehnologies and existing transistors. However, with the inreasing design omplexities and shorter design yles, the onventional CAD approahes are diiult to satisy the requirements o preision and speed at the same time. New semiondutor tehnologies and materials ontinue to evolve making it neessary to develop eiient modeling algorithms or pakaged transistors. Reently, Knowledge-based neural network modeling tehniques have been reognized as useul alternatives to onventional tehnologies in mirowave modeling [5-7]. The knowledge-based model exploit existing knowledge in the orm o empirial or equivalent iruit models together with neural networks to develop a more aurate model. The evaluation rom input to output o a knowledge-based model is also very ast. Knowledge-based tehniques have been utilized in transistors modeling when the mathematial model is not available [8]. However, the existing knowledge-based neural network metho or transistors modeling mainly ous on the ore transistor without modeling the pakage iruit [9, ]. Systemati and ast modeling metho or pakaged transistors are still an open researh topi. n this paper, a novel small-signal modeling method using knowledge-based neural networks or pakaged transistors is proposed. Separate neural networks are adopted to represent the nonlinear relationship between the requeny and the S-parameters. An advaned training method is proposed or the model development. The proposed model an math the devie well and exeed the urrent apabilities o existing devie models.. Proposed Modeling Method or Pakaged Transistors Pakages o transistors typially ontain a metal lange and a dieletri window rame. The ore transistor is bonded to the die-bond area inside the avity o the window rame. Metal lea are provided at the input and output sides o the window rame to allow or onnetion to external iruitry. Based on the physial struture o the pakaged transistor, we propose to divide the total struture into three parts: the input pakage iruit, the ore transistor iruit and the output pakage iruit, and reate the CAD modules or these three parts respetively... Proposed DC model n general, the pakaged iruit is omposed o linear devies, whih does not aet the DC harateristis o the devie. The DC harateristis o the devie are aeted only by the ore iruit. n this D:.979/ Page

2 A Novel Small-Signal Knowledge-Based Neural Network Modeling Approah or. paper, we proposed to use the modeling method in literature [9] to reate the ore iruit model. We deine the knowledge model in this paper to represent the existing transistor model. Beause the DC harateristis o the existing transistor model and that o the ore iruit are not the same, we propose to establish a mapping network to map the inputs o the knowledge model onto the ore iruit. Beause the mapping network is nonlinear and unknown, neural networks ( ) are proposed to be use as the mapping network. The proposed DC model ontains the knowledge model and the input mapping network, shown in Fig.. Ater training the T neural networks, the proposed DC model an represent the behaviors o the ore iruit. Let Vs [ Vgs, V ] and s [ gs, ] T represent the voltage and urrent signals o the knowledge model respetively. Let T T Vs [ Vgs, V ] and s [ gs, ] represent the voltage and urrent signals o the ore iruit respetively. The proposed DC model exee the knowledge model urrent apabilities by adding more ree variables. When the knowledge model operates with the signals ( Vgs, V ) instead o the signals ( Vgs, V ), the output urrent o the knowledge model an math that o the modeled devie aurately. The neural network is used to desribe the nonlinear relationship between the signals o the knowledge model ( Vgs, V ) and the signals o the modeled devie ( Vgs, V ) as where ( V, V ) ( V, V, w ) () gs gs represents a multilayer eedorward neural network, and w is a vetor ontaining all internal synapti weights in the neural network V. () V Knowledge Model Figure. DC model struture... Proposed S-parameters model struture n the pakaged transistors, both the ore iruit and the pakage iruits aet the small-signal harateristis o the devie. When the ore iruit and the pakage iruits are modeled in terms o their sattering parameters, sattering-matrix analysis an be appliable to small-signal modeling o the pakaged transistor. We proposed to reate the small signal model or the input pakage iruit, the ore iruit and the output pakage iruit respetively, and alulate the S-parameters or the model devie. The struture o the proposed small signal model is shown in Figure. The ore module onsist o the knowledge model and a neural network represent the small-signal harateristis o the ore iruit. The ore module an ensure the DC as well as the S-parameters harateristis. Two neural networks are proposed to represent the behaviors o the input and output pakage iruits respetively. The pakaged module an be ahieved only using the terminal signals, instead o the internal and physial struture inormation o the transistor. The S-matrix module based on the literature [5] is onstruted realizing the alulation o S-parameters between the pakaged transistor and its three parts. Re( S ) m( ) S-Matrix Calulation S Re( S ) m( ) S Re( S ) m( S ) Re( S ) m( ) S nput Pakaged Module h ( ) V () Core Module utput Pakaged Module g ( ) V req Figure. Proposed small-signal model struture. D:.979/ Page

3 A Novel Small-Signal Knowledge-Based Neural Network Modeling Approah or. n Figure, the modules and respetively represent the perormane o the input/output pakage iruits whih onsist o passive omponents suh as bond wires, MS apaitors and so on. Beause the input/output pakage iruit onsists o linear omponents, the unique input o the pakaged modules is the requeny. The output signals o the Re( S ) and m( S ) are the real and imaginary parts o S, S and S o the input pakaged iruit. Similarly, Re( S ) and m( S ) are the output signals o the output pakage iruit respeted by the. For the ore module, bias voltages and requeny are the input signals, and the real and imaginary parts o S-parameters Re( S ) and m( S ) are the output signals. The S-parameters o the modeled devie Re( S ) and m( S ) an be alulated with S-matrix alulation module. n the proposed model, the pakaged modules represent the nonlinear relationship between the requeny and the S-parameters, whih an be desribed as (Re( S ),m( S )) h ( req, w ) () (Re( S ),m( S )) g ( req, w ) () where h and g represents multilayer eedorward neural network, and w and w are vetors ontaining all internal synapti weights in the neural network h and g respetively. Usually, the mathematial relationship between the requeny and the S-parameters o the pakaged iruit is not available. When more bond wires, MS apaitors and integrated apaitor are added into the pakage iruit to ease external mathing-iruit design, the relationship between the requeny and the S- parameters is more ompliated. The proposed small-signal model with high preision and high speed an be ahieved only using the terminal signals, instead o the internal and physial struture inormation o the transistor. To make the proposed knowledge-based neural network model represent the DC and small-signal harateristis o the atual devie, we propose a new training method in the next subsetion... Proposed training method A knowledge-based neural network model annot represent the pakaged transistor aurately until it learns the related data. Thereore, the neural network training is an important step during the model development. The training proess automatially adjusts the weights in the neural network so that the output o the model an it the devie data aurately. The training error represents the dierene between the devie data and the model. Equation (4) and (5) represent the training error o DC, and S-parameters harateristis, respetively: N, n, n n E( w) ( Vgs, Vd, w ) D (4) n N, n, n n n E( w) S( Vgs, V, req, w, w) S D (5) n where D and (.) represent the DC responses o the pakaged transistor data and the proposed model, respetively. The supersript n represents the training data index, and N represents the total number o the training data. S D and S (.) represent the S-parameters o the pakaged transistor data and the proposed model, respetively. n order to improve the modeling eiieny, we propose a our-stage training method. n the irst stage, we initialize the weight value o the s avoiding the proposed model degrading the knowledge model perormane. n the seond stage, we adjust the weight w o the neural network in Figure making the DC model math the devie data in the DC simulation. n the third stage, we adjust the weights w and w o the neural networks in Figure making the proposed small-signal model math the devie data in the S-parameters simulation. n the ourth stage, we train the proposed overall model by simultaneously train the DC model and the small-signal model again to inally ahieve the modeling auray. The proposed method ontrols the DC and small-signal perormane o the model with dierent weight parameters, whih redue the mutual intererene o the optimized parameters and avoid hanging the optimized parameters repeatedly. Ater training, the proposed model an be more aurate than the existing model, and it an replae the atual devie to plug into an original iruit or design and simulation. The details o the steps or the proposed training proess are shown as ollows: Step ) nitialize the by solvingvgs Vgs andv V, and obtain the initial variables w. nitialize the by solving Re( S ) Re( S) and other S-parameters equals, and obtain the initial D:.979/ Page

4 (A) A Novel Small-Signal Knowledge-Based Neural Network Modeling Approah or. o o variables w. nitialize the by solving Re( S ) Re( S) and other S-parameters equals, and obtain the initial variables w. This step an avoid degrading the knowledge model perormane. Step ) Adjust the weight w to * w by solving the equation (4) and obtain the bias voltage o the knowledge model Vgs andv, whih make the proposed model math the devie data in the DC simulation. Step ) Adjust the weights w to * w and w to * w by solving the equation (5) and obtain the Re( S ) / m( S ) and Re( S ) / m( S ), whih make the proposed small-signal model math the devie data in the S-parameter simulation. * * * # # # Step 4) Fine tune the weights ( w, w, w ) to ( w, w, w ) making the training error as small as possible, whih an improve the perormane o the proposed model urther.. Experimental Veriiation n this experiment, measured data o the laterally diused metal-oxide semiondutor (LDMS) pakaged transistor AFT8S are used as the training data and test data. The range o them used in this example is showed in Table. The LDMS transistor AFT8S9 model in Advaned Design System (ADS) is used as the knowledge model. The mismath between the knowledge model and the measured data annot be ignored. The proposed model is trained using the proposed our-stage training method whih has been introdued in setion.. The proposed model learns the training data by automatially adjusting the weight o the neural networks. Test data whih are dierent with the training data are used to validate the auray o the onstruted model. Table gives the test error o the knowledge model and the proposed model. This result demonstrates that the proposed method improves the urrent apabilities o the knowledge model. n order to urther show the detailed results, the -V and S-parameters omparison between the measured data and the models are shown in Fig. and Fig.4, respetively. Good agreements between the proposed model and the measured data an be observed. DC Simulation S-Parameters Simulation Table. Training data and test data or DC and S-parameters modeling. (V) V (V) req (GHz) Training Data.55:.:.5 -.5::.5 Test Data.6:.:. :: Training Data.5:.:.45.68:.5: ::9.5.7:.5:. Test Data.4,.7, :.5:. Error (%) Knowledge Model Proposed Model Table. Test error o the models or DC and S-parameters simulation. S m( S ) Re( S ) m( S ) Re( S ) m( S ) Re( S ) S Re( ) m( ) 8 Measured Data Proposed Model V (V) Figure. -V omparison between the measured data and the models or the LDMS transistor. D:.979/ Page

5 PAE (%) Gain (db) S S S S A Novel Small-Signal Knowledge-Based Neural Network Modeling Approah or Measured Data Proposed Model Frequeny (GHz) Frequeny (GHz) Frequeny (GHz) Frequeny (GHz) Figure.4 Comparison o S-parameters between the measured data and the models or the LDMS transistor at the typial work bias point ( V.75 V, V 8V ). gs n this example, the proposed model are operated in hamoni balane (HB) simulation to urther veriy the eetiveness o the advaned modeling methodology. The models work at the undamental requeny.85ghz, the soure impedane.55 j4., the load impedane.4 j.748, the bias voltage (.75 V, 8 V) and the dierent input powers ( P in : rom 4.5 to 6.5dBm, step dbm). The omparison results o the gain and the power added eiieny (PAE) between the measured data and the models are shown in Fig.5, demonstrating that the HB respons o the proposed model is muh loser to the measured data than that o the knowledge model. This result provides a good oundation or the large signals modeling in the uture work Measured Data Proposed Model Gain PAE Gain P in (dbm) Figure.5 Comparison o the gain and PAE between the measured data and the models or the LDMS transistor. V. Conlusions n this paper, the novel model ombing the separate neural networks with the ore transistor model is proposed to present the entire small-signal behavior o the pakaged transistors or the irst time. The advaned training method an ind the appropriate parameters eiiently, and the trained model an represent the linear harateristi o the pratial devie aurately. The proposed model is ahieved only using the terminal signals, instead o the internal and physial struture inormation o the pakaged transistor. This advantage makes the novel method suitable or more and more omplex devies meeting the demand o modern tehnology development. D:.979/ Page

6 A Novel Small-Signal Knowledge-Based Neural Network Modeling Approah or. Aknowledgements This researh was unded by [the National Natural Siene Foundation o China] grant number [66]; [the Sientii Researh Projet o Tianjin Eduation Commission] grant number [7KJ88]; [the Tianjin Natural Siene Foundation] grant number [7JCQNJC4]. Reerenes [] Rudolph M, Fager C, Root D E, Nonlinear Transistor Model Parameter Extration Tehniques (UK: Cambridge University Press, ). [] P. K. Singya, N. Kumar, V. Bhatia, Mitigating NLD or wireless networks: eet o nonlinear power ampliiers on uture wireless ommuniation networks, EEE Mirowave Magazine, 8(5), 7, 7-9. [] P. H. Aaen, J. A. Plá, J. Wood, Modeling and Charaterization o RF and Mirowave Power FETs (UK: Cambridge University Press, 7). [4] L. Dan, Z. Lei, H. Rueda, et al, Devie Physis and EM Simulation Based Modeling Methodology or LDMS RF Power Transistors, EEE Mtt-S nternational Conerene on Numerial Eletromagneti and Multiphysis Modeling and ptimization or R, Mirowave, and Terahertz Appliations. EEE, 7, [5] Q. J. Zhang, K. C. Gupta, Neural Networks or RF and Mirowave Design (Boston : Arteh House, ). [6] H. Kabir, L. Zhang, M. Yu, Smart modeling o mirowave devies, EEE Mirowave Magazine, (),, 5-8. [7] W. C. Na, Feng F, C. Zhang, A Uniied Automated Parametri Modeling Algorithm Using Knowledge-Based Neural Network and l₁ ptimization, EEE Transations on Mirowave Theory & Tehniques, 65(), 7, [8] L. Zhang, J. J. Xu, M. C. E. Yagoub, Eiient analytial ormulation and sensitivity analysis o neuro-spae mapping or nonlinear mirowave devie modeling, EEE Transations on Mirowave Theory and Tehniques, 5(9), 5, [9] L. Zhu; Q. J. Zhang; K. H. Liu. A novel dynami neuro-spae mapping approah or nonlinear mirowave devie modeling. EEE Mirowave & Wireless Components Letters, 6(), 6, -. [] L. Zhu; J. Zhao; Z. Li. A general neuro-spae mapping tehnique or mirowave devie modeling. Eurasip Journal on Wireless Communiations & Networking, 8(), 8, 7. SR Journal o Eletrial and Eletronis Engineering (SR-JEEE) is UGC approved Journal with Sl. No. 498, Journal no Shuxia Yan "A Novel Small-Signal Knowledge-Based Neural Network Modeling Approah or Pakaged Transistors" SR Journal o Eletrial and Eletronis Engineering (SR-JEEE).5 (8): D:.979/ Page