Voltage Scalable Switched Capacitor DC-DC Converter for Ultra-Low-Power On-Chip Applications

Transcription

1 Voltage Salable Swithed Capaitor DC-DC Converter for Ultra-ow-Power On-Chip Appliations Yogesh K. amadass and Anantha P. Chandrakasan Mirosystems Tehnology aboratory Massahusetts Institute of Tehnology Cambridge, MA 039 USA Abstrat- This paper presents a voltage salable swithed apaitor (SC) DC-DC onverter whih employs on-hip hargetransfer apaitors. The DC-DC onverter makes use of multiple topologies to ahieve salable voltage generation while minimizing ondution loss and a tehnique alled divide-by-3 swithing to minimize the loss due to bottom-plate parasitis. It also uses automati frequeny saling to redue swithing losses. The onverter employs an all digital ontrol whih onsumes no stati power. The voltage salable SC DC-DC onverter with integrated on-hip harge-transfer apaitors was implemented in a 0.8µm CMOS proess and ahieves above 70% effiieny over a wide range of load powers from 5µW to mw, while delivering load voltages from 300mV to.v. The ative area onsumed by the onverter is 0.57mm. I. INTODUCTION Minimizing the energy onsumption of battery powered systems is a key fous in integrated iruit design. Dynami voltage saling (DVS) [] is a popular method to ahieve energy effiieny in systems that have widely variant performane demands. As V DD dereases, transistor drive urrents derease, bringing down the speed of operation of a iruit. A DVS system operates the iruit at just enough voltage to meet performane, thereby ahieving overall savings in total power onsumed. y introduing the apability of subthreshold operation these same systems an operate at their minimum energy operating voltage [] in periods of very little ativity, leading to further savings in total energy onsumed. This way ultra-dynami voltage saling (U-DVS) an be ahieved. U-DVS systems require a variable voltage supply that an deliver sub-threshold voltages (~300mV) at low load powers (µw) when idling, and lose to the battery voltage (~.V) at high load powers ( - mw) when performing ative operation. Supply voltage dithering, whih uses disrete voltage and frequeny pairs, was proposed as a solution to ahieve U-DVS []. However, dithering requires an effiient system ontroller that an time share between the different voltage levels adding to the overall omplexity of the system. This is of speifi onern in ultra-low-power appliations. Also, voltage dithered systems that ahieve U-DVS require at least voltage levels different from the battery voltage to ahieve the stated power savings. This inreases the number of DC-DC onverters to supply these voltage levels. This paper fouses on a voltage salable DC-DC onverter that an deliver a ontinuous voltage supply quantized to 0mV. U-DVS systems often require multiple on-hip voltage domains with eah domain having speifi power requirements. A swithed apaitor (SC) DC-DC onverter is a good hoie for suh battery operated systems beause it an minimize the number of off-hip omponents and does not require any indutors. Previous implementations of SC onverters have ommonly used off-hip harge-transfer apaitors [3] to output high load power levels. A SC DC-DC onverter whih integrates the harge-transfer apaitors was desribed in [4]. In this work, we desribe a 0.8µm CMOS voltage salable SC DC-DC onverter with integrated on-hip harge-transfer apaitors that ahieves >70% effiieny at a wide range of load powers from 5µW to mw and an deliver load voltages ranging from 0.3V to.v. II. SCAA VOTAG GNATION This setion desribes how salable load voltages are generated from a.v off-hip battery. Consider the T6 topology in Figure. It shows a simple swithed apaitor voltage divide-by-two iruit. The harge-transfer apaitors are equal in value and help in transferring harge from the battery to the load. During phase, the harge-transfer apaitors get harged from the battery (V ). In the phase of the lok, they dump the harge gained onto the load (). The reason behind the swithes marked by3 or by3 is explained in setion V (ii). Throughout this setion assume that all swithes shown in Figure turn ON either in or (i.e. by3 = ; by3 = ). At no load, the T6 topology iruit tries to maintain the output voltage at V / (0.6V), where V is the battery voltage. The atual value of that the iruit settles down to is dependent on the load urrent I O, the swithing frequeny and C. et the T6 topology deliver a load voltage = V N V, where V N is the no-load voltage for this topology. The SC onverter limits the maximum effiieny that an be ahieved in this ase to lin = ( V/V N ). Thus, the farther away is from V N (i.e. higher V), the smaller the maximum effiieny that an be ahieved by this topology. This is a fundamental problem with harge transfer using only apaitors and swithes. Thus, to improve effiieny, it is neessary to swith in different topologies whose no-load /07/$ I 353

2 by3 V T4 V N = 0.4V by3 V T9 V N = 0.9V by3 by3 by3 by3 by3 V T8 V N = 0.8V by3 by3 V by3 Topology Swithes T b T6, T a V T V N =.V C T6 V N = 0.6V by3 6C T4, T6, T8, T d T4, T8, T T4, T8, T 6C C C C Figure. Topologies used to generate effiiently a wide range of load voltages from a.v supply. The topology swithes help form the topologies. output voltage is loser to the load voltage desired. Fig. shows the different topologies that were employed in the SC DC-DC onverter. The output load voltage is salable between 0.3V to.v. The topologies are named based on the no-load voltage they deliver. For example, the T9 topology delivers a no-load voltage of 0.9V and T4, a no-load voltage of 0.4V. ah topology is loked by two non-overlapping phases and of a system lok. In the first phase, the hargetransfer apaitors are harged from the battery. In, this harge gained is passed on to the load. The T topology provides.v at no-load. This topology behaves essentially like a linear regulator and it is used to provide load voltages between 0.9V and.v. The T6 topology is a simple voltage divide-by- iruit, where apaitors of equal value 6C are harged in series and disharge to the load in parallel. This topology aters to load voltages below 0.6V. The T4 topology is a divide-by-3 iruit and it aters to load voltages of 0.4V and below. The T8 topology shown on the top-right in Figure has a no-load voltage of 0.8V and it provides a /3 voltage ratio output. The T8 topology funtions as follows: During, two apaitors of value and 8C are harged in series from the battery. In steady state, the top apaitor of value gets harged to 800mV or /3 of the battery voltage and the bottom apaitor of 8C to 400mV or /3 of the battery voltage. During, the top apaitor is onneted diretly to the load while the bottom 8C apaitor is split into two and onneted in series with the load. This way the total voltage aross the series ombination is 800mV. The T8 topology is used to deliver load voltages below 800mV. The T9 topology is a ratio 3/4 ths iruit and has a no-load voltage of 0.9V. Its operation is similar to the T8 topology, exept that the harge-transfer apaitors are broken down into and 9C during. T6, T9 T6, T9 The speifi topology to be used is determined based on the load voltage desired. et the total apaitor budget for hargetransfer apaitors given a hip area onstraint be C. The individual apaitors used in the different topologies are obtained by joining fragments of the C apaitor using topology swithes as shown on the right hand orner of Fig.. A topology swith represented by a two-headed arrow joins two apaitors. It onsists of swithes, one to onnet the top plates and one for the bottom plates. The topology swith is turned ON for the topologies marked on top of the arrow. Apart from the topology swithes, harge-transfer swithes are employed within eah topology as shown in Fig.. These swithes are driven by either or or one of their divided versions by3 or by3. All the harge-transfer swithes used in the individual topologies are realized from a total of only 3 swithes as an be seen from the swith array in Fig.. ah box in the array is representative of a swith whih is turned ON depending on the topology in use and the phase of the V GND GND A 8,9 4, ,6 8 9 a TOP 4,8,9 b MID 4,6 8 OT 8,9, 4,6 4, T Figure. Charge-transfer swith array (eah box represents a swith) X d T9 T8 T6 T4 9 TOP C 6C MID by3 by3 OT 6C GND X 354

3 V ref COMP Non-Overlapping Clok Generator DAC by3 7 ITCH by3 MATIX lk V ref by3 by3 lk4x AUTOMATIC FQUNCY SCA lk enw Vp8 V (.V) C load I O lok. For instane, the swith whih onnets the top plate of apaitor TOP to the battery is turned ON in phase for all topologies while the swith that onnets the bottom plate of apaitor TOP to ground (GND) turns ON during for topologies T8, T9 and during by3 for topologies T4, T6. The table inside Fig. shows the value of the individual apaitors used in the different topologies. The nodes marked a, b, and d orrespond to the similarly named nodes in the right hand orner of Fig.. The harge-transfer swithes are realized using PMOS or NMOS transistors or a ombination of them depending on the loation of the swith in the array (see setion V (iii)). A very simple digital ontrol is utilized to turn ON the swithes depending on the topology in use. This arrangement of the swith array enables effiient sharing of harge-transfer swithes between multiple topologies. III. ITCHD CAPACITO DC-DC CONVT SYSTM ACHITCTU Figure 3 shows the arhiteture of the SC DC-DC onverter. At the ore of the system is the swith matrix whih ontains the harge-transfer apaitors, and the topology, hargetransfer swithes. A suitable topology is hosen depending on the referene voltage V ref, whih is set digitally. The digital referene is onverted to an analog value using an on-hip harge redistribution digital-to-analog onverter. The entire iruit exept for the topology swithes operates from a.v voltage supply. A.8V supply (Vp8) is used only for the topology swithes. In steady state, as there is no swithing involved in the topology swithes, negligible power is onsumed from the.8v supply. A pulse frequeny modulation (PFM) mode ontrol is used to regulate the output voltage to the desired value. A dynami omparator loked by the signal lk is used for this purpose. When the output voltage is above V ref, the swithes are all set to the mode. When falls below V ref, the omparator triggers a pulse, whih Figure 3. Arhiteture of the swithed apaitor DC-DC onverter system harges up the output load apaitor C load. The nonoverlapping lok generator blok prevents any overlap between the and ON phases. A lok divider is used to generate by3 and by3 phases. Typial waveforms of these phases are shown in the inset in Fig. 3. To minimize gate-swithing losses, the iruit automatially adjusts the swithing frequeny depending on the load power demand. The automati frequeny saling (AFS) blok that performs the frequeny seletion is shown in Figure 4. An additional omparator alled the overload omparator is used in the AFS blok. The referene voltage of the overload omparator is set to V ref - V off, where V off is an offset voltage (~0mV) whih again is set digitally. When the DC-DC onverter, operating in steady state, annot supply the desired load power at a given swithing frequeny, begins to fall below V ref (see equation 3). As falls below V ref V off, the overload omparator triggers the go_up signal. This signal is used to double the swithing frequeny whih in turn doubles the width of the harge-transfer swithes. At low load powers, the swithing frequeny is brought down using a ounter mehanism. If the number of pulses for every 4 lk yles is found to be less than 3, the go_down signal is triggered whih halves the swithing frequeny and the width of the hargetransfer swithes. The signals enw and determine the swithing frequeny. When only enw is high, X the minimum lok frequeny is used and when is high, 4X the minimum lok frequeny is used. The signals enw and are fed into the swith matrix to suitably size the hargetransfer swithes. While the PFM mode ontrol effetively redues the frequeny of pulses as load power dereases, the AFS blok helps in bringing down the overall system swithing frequeny together with the width of the hargetransfer swithes, thereby reduing the swithing losses in the gate-drive and the ontrol iruitry. The entire ontrol iruitry is digital and onsumes no stati power, whih is a ritial 355

4 V ref V off DAC COMP go_up D Q enw go_up D Q COUNT reset < 3 lk D Q go_down reset go_downw go_down lk4x enw 0 0 lk Delay Delay 4 th lk yle feature to ahieve good effiieny at ultra-low load power levels. It is extremely salable in terms of omplexity to suit the load power and voltage demands of the target appliation. IV. POW DIVY This setion presents an analysis of the power delivered to the load by the DC-DC onverter. Consider the T6 topology shown in Fig.. et the T6 topology deliver a load voltage = V N V, where V N = V / (0.6V) for this topology. Assume again that all the swithes turn on in or. While operating in steady-state, during phase, both the 6C harge-transfer apaitors disharge down to when the load apaitor is muh larger than 6C. When they are onneted bak in series again during phase, both these apaitors get harged bak to V /. The energy extrated from the battery during this proess is given by 6C V V () During, this exess harge is transferred to the load apaitor. The harge-transfer apaitors transfer twie the harge gained from the battery during. However, this harge is delivered at a voltage and hene the energy delivered to the load every yle is a linear saled version of the energy extrated from the battery and is given by VN V CVO V () V N The maximum power that an be delivered to the load by this topology when swithing at a frequeny f s is then given by TA I POW DIVD TO OAD Topology lin T C V V /. T9 V V /0.9 T8 V V /0.8 T6 6C V V /0.6 T4 V V /0.4 Figure 4. Automati Frequeny Saling blok P f C V Vf f (3) s O s s where lin is the linear effiieny loss. From this expression it an be seen that to deliver more load power at a given load voltage, C or f s need to be inreased. Inreasing C inreases the energy extrated from the battery every swithing yle, whereas inreasing f s inreases the rate of delivery of the harge pakets. The power delivered to the load also depends on the topology being used. Table I gives a breakdown of and lin for the various topologies. It an also be noted that the larger V is, i.e. the farther is from the no-load voltage, the more power that the onverter an deliver. This again is due to inreased. Thus, if a given topology is unable to meet the load power requirement even at the highest swithing frequeny, the next higher topology is used. This is the reason that even at moderate load power levels of 00µW, the T8 topology delivers a load voltage of 590mV and not the T6 topology. This leads to a drop in the linear effiieny than that ould have otherwise been ahieved had the load power requirement been low. V. FFICINCY ANAYSIS ffiieny of a power onverter is a key metri for battery operated eletronis and energy starved systems. The prinipal ontributors to effiieny loss in the SC DC-DC onverter are: i) Condution oss in transferring harge from battery to load This is a fundamental loss mehanism whih arises from harging a apaitor through a swith. To minimize ondution loss, different topologies (Fig. ) are swithed in to redue the differene between the no-load voltage (V N ) of a topology and. Assuming that a load voltage less than 600mV is being supplied by the T8 topology, ondution loss imposes a limit on the maximum effiieny that an be ahieved to lin = / 0.8. y swithing to the T6 topology, this effiieny limit an be improved to lin = / 0.6. ii) oss due to bottom-plate parasiti apaitors The seond main ontributor to effiieny loss after the linear ondution loss is that due to parasiti bottom-plate apaitors. lin 356

5 This arises due to harging the bottom-plate parasiti apaitane [5] of the harge-transfer apaitors every harge yle. This is of speifi onern for on-hip apaitors in digital CMOS proesses. The bottom-plate apaitane C P, sales with the apaitor area and an be expressed as C P = C, where an be as high as 5% for the apaitors used. Consider the T6 topology. During the phase when the harge-transfer apaitors are harged to one-half the battery voltage, the bottom-plate parasiti apaitane of the top apaitor also gets harged to V /. In phase when these apaitors are onneted in parallel to harge the load, the energy stored in the bottom-plate parasiti apaitane is lost by onneting it to ground. Assuming that normal swithing is employed (i.e. all the swithes are driven by or ), the energy lost per yle in steady-state due to C P of the top apaitor is P V.5C (4) while the energy extrated from the battery per yle, is given by equation (). et the ratio of P to be given by the following equation: P V V K p 0.5 (5) V V where K p is a parasiti-loss parameter. For normal swithing the fator K p is 0.5. The fator 0.5 in K P is a topologydependent parameter (Table II) while is a tehnologydependent parameter whih depends on proess parameters and the type of apaitor being used. Our proposed sheme to address the bottom-plate parasiti loss is to use divide-by-3 swithing. For every topology (see Fig. ) the apaitane that leads to signifiant bottom-plate parasiti loss is identified and it is swithed one every 3 yles. This way, the fration of the energy lost due to bottom-plate parasitis is dereased. For the T6 topology, the top apaitor 6C is swithed on to the load only one every 3 yles. The swithing waveforms are shown in the inset in Fig. 3. The energy extrated from the battery over 3 yles is,3 6C.75V V 0.5C V V (6) while the energy lost due to C P remains approximately the same as given by equation (4). Thus, there is a.75x improvement in K p when divide-by-3 swithing is employed. A similar strategy is employed for the other topologies and the improvements obtained in K p an be seen from Table II. TA II IMPOVMNT IN K P Y DIVID-Y-3 ITCHING Topology K p K p, divby3 T 0 n/a T T8 0. n/a T T For the T4 topology, the top apaitor ontributes the most to bottom-plate loss and is swithed only one in 3 harge transfer yles. Sine no marked improvement was observed in the T8 topology, the divide-by-3 swithing sheme wasn t employed. For the T9 topology, the bottom apaitors are swithed one in every 3 yles. This is different from the other topologies beause in T9 topology the top apaitor ontributes 3/4 th to the energy transfer per yle but the bottom apaitors ontribute more to the parasiti loss. Thus by swithing the bottom apaitors one in 3 yles, a signifiant fration of the energy an still be transferred per yle while reduing the bottom-plate parasiti loss. While divide-by-3 swithing improves effiieny by reduing the ontribution of bottom-plate losses, it requires a higher swithing frequeny for a given load power level due to dereased energy transfer per yle. While this inreases gate swithing losses in topologies T4 and T6, the divide-by-3 swithing sheme dereases swithing losses in T9 beause of the redution in the number of swithes being swithed every yle (see Table III). iii) Gate-drive oss The energy expended in swithing the gate apaitanes of the harge-transfer swithes every yle an be approximately given by ox nc WV (7) where n is the number of swithes used, C ox is the gate-oxide apaitane per unit area, W and are the width and length of the harge-transfer swithes. The width of eah swith is however proportional to the harge-transfer apaitane and the frequeny of swithing. This is beause the resistane of the swithes needs to be low enough to allow settling of the harge-transfer apaitors within the time period of swithing. an then be expressed as s nc f V (8) where the onstant depends on C ox,, the mobility µ and the threshold voltage of the devies. The ratio of to an be expressed by equation (9), where K s is a swithing-loss parameter. Here again n is topology-dependent while is tehnology-dependent. V V K sfs n fs (9) V V To minimize the gate-swithing loss, depending on the loation of the harge-transfer swith and the topology in use, either only a PMOS or an NMOS swith is used instead of a transmission gate omprising both PMOS and NMOS devies. For example, the swith onneting the battery to the top plate of apaitor TOP in Fig. is a PMOS-only swith, while all the swithes onneting the bottom-plates of the apaitors to GND were NMOS-only. Also, while the swith onneting the top-plate of apaitor TOP to the load () omprises of both PMOS and NMOS devies, only the PMOS part of the swith is ativated for T topology, while only the NMOS part of the same swith is ativated for the T4 topology. The automati 357

6 90 85 V = 0.5V o V o = V Measured - divby3 swithing Measured - normal swithing Theoretial ffiieny (%) ffiieny (%) oad Power (µw) Figure 6(a). ffiieny plot with hange in load power frequeny saling tehnique desribed in setion III sales the width of the harge-transfer swithes as the swithing frequeny hanges. This way, if the load power dereases by half, the AFS blok halves both the swithing frequeny and the width of the harge-transfer swithes, thereby effetively halving the ratio of to. iv) Power loss in the ontrol iruitry The power lost in the ontrol iruitry is of speifi onern while delivering ultralow load power levels. The energy lost in the ontrol iruitry every swithing yle an be broken into a swithing and a leakage omponent and is given by CONT C Swithes Figure 5. Die Photo of the swithed apaitor DC-DC onverter K V I V T (0) where K is the average apaitane swithed in the ontrol iruitry every harge yle, I leak is the total leakage urrent onsumed by the ontrol iruitry and T is the average timeperiod of a harge yle. The ontrol iruitry does not onsume any stati power (no analog bias urrents) other than the subthreshold leakage urrents in the digital iruitry. leak Control oad Voltage (V) Figure 6(b). ffiieny plot with hange in load voltage The overall effiieny taking into aount all the above mentioned losses an be expressed as the ratio between the total energy delivered to the load per yle to the sum of the energy extrated from the battery and the energy losses / yle. P V VN K p CONT V V V IleakT K sfs K V V C V C V () On dividing the numerator and denominator by, the overall effiieny an be expressed in a more ompat form where the pre-fator is due to the linear effiieny. The nd term in the denominator is due to the bottom-plate parasiti loss. The next term is due to gate-drive swithing loss, and the 4 th and 5 th terms are due to swithing and leakage loss in the ontrol iruitry. We see that while the linear ondution loss inreases as V inreases, the other losses derease with V. Thus, for go_up Figure 7. Waveform showing transient response 358

7 any given topology there is an optimum V where the effiieny is maximized. The ontribution of the swithing losses in the ontrol iruitry and the gate-drive an be minimized by inreasing C. The leakage loss however is independent of C for a given load power beause as C inreases, the swithing period T also inreases. In ultra-low load power levels, this leakage power omponent an be signifiant as the last term in the effiieny equation is just a ratio of the leakage power to load power. VI. MASUD SUTS A swithed apaitor DC-DC onverter test-hip, inorporating all the features explained in the setions above, was fabriated in National Semiondutor s 0.8µm CMOS proess. Fig. 5 shows a die-photo of the implemented hip. The die area oupied was.6 x.6mm with the ative iruitry onsuming just 0.57mm, bulk of whih was oupied by the harge-transfer apaitors. Gate-oxide apaitors were used for harge-transfer beause of their high density and low bottomplate parasitis. A total of.4nf of harge-transfer apaitane was used. The maximum lok frequeny (lk4x in Fig. 4) employed was 5MHz. The DC-DC onverter was able to deliver load voltages from 300mV to.v. The effiieny of the SC onverter with hange in load power is shown in Figure 6a. The T topology was used to deliver V and T6 topology was used to deliver 0.5V. At 0.5V, the DC-DC onverter was able to ahieve lose to 74% effiieny over a wide range of load powers. The effet of swithing losses in bringing down the effiieny an be seen at load power levels above 50µW. The effiieny of the SC onverter with hange in load voltage while delivering 00µW to the load from a.v supply is shown in Fig. 6b. The onverter was able to ahieve >70% effiieny over a wide range of load voltages. An inrease in effiieny of lose of 5% due to the divide-by-3 swithing sheme an be seen at voltages delivered by the topologies T9 and T4. The measured effiieny plot losely mathes the theoretial effiieny values as obtained by using equation. The topology swith into the T9, T8, T6 and T4 topologies was made at 850mV, 750mV, 570mV and 350mV respetively, when divide-by-3 swithing was employed. When normal swithing was employed, the swith into the T9 topology was made at 85mV. The swithing between topologies does not our at the no-load voltages of the individual topologies. This TA III AKDOWN OF TH DIFFNT OSS MCHANISMS WHI DIVING 00µW AT 0.8V (T9) ( normal =0.77, divby3 = 0.763) oss Mehanism Power oss Normal Div-by-3 Condution.45µW.45µW ottom-plate 4.68µW 7.47µW Gate-drive 8.3µW 6.38µW Control 4µW 4.69µW is beause at very low V s the effiieny is low due to the bottom-plate and swithing losses. Also, the load power delivered is very low at low V s. The optimum load voltage where effiieny is maximized for eah topology an also be seen from the peaks in Figure 6(b). The reason for this was explained in the previous setion. Table III shows a breakdown of the power lost in the different loss mehanisms while delivering 00µW at 0.8V through the T9 topology. A quantitative estimate of the redution in bottom-plate losses due to divide-by-3 swithing an be seen. Figure 7 shows a measured plot of the transient in load voltage when the referene voltage is raised from 0.3V (T4) to V (T). The SC DC-DC onverter takes lose to 6µs to raise the output voltage to V when 00µA is being delivered to the load. The waveforms orresponding to the and go_up signals show the operation of the automati frequeny saling blok explained in setion 3. The signal remains high till the desired load voltage is reahed, thereby enabling a fast transient response. One, the onverter settles lose to V, the signal goes low to redue the swithing losses. VII. CONCUSION This paper has presented a swithed apaitor DC-DC onverter with on-hip harge-transfer apaitors that an deliver salable load voltages from 300mV to.v. Multiple topologies were employed in the SC DC-DC onverter to minimize ondution losses. These topologies were obtained by suitably ombining fragments of the harge-transfer apaitors. A divide-by-3 swithing sheme was employed to minimize losses due to parasiti bottom-plate apaitors. This sheme was able to provide lose to 5% improvement in effiieny. An automati frequeny saling sheme was utilized to minimize swithing losses. The onverter employs ompletely digital ontrol with no stati power losses. The swithed apaitor DC-DC onverter test-hip was fabriated in a 0.8µm digital CMOS proess and was able to ahieve >70% effiieny over a wide range of load voltages. ACKNOWDGMNT The authors would like to aknowledge DAPA for funding and National Semiondutor for hip fabriation. FNCS []. H. Calhoun and A. P. Chandrakasan, "Ultra-dynami voltage saling using sub-threshold operation and loal voltage dithering in 90nm CMOS," I International Solid-State Ciruits Conferene, pp , Feb [] Y. K. amadass and A. P. Chandrakasan, Minimum nergy Traking oop with mbedded DC-DC Converter Delivering Voltages down to 50mV in 65nm CMOS, I International Solid-State Ciruits Conferene, pp , Feb [3] A. ao, W. MIntyre, U. Moon and G. C. Temes, Noise-Shaping Tehniques Applied to Swithed-Capaitor Voltage egulators, I J. Solid-State Ciruits, vol. 40, no., pp. 4-49, Feb [4] G. Patounakis, Y. i and K.. Shepard, A Fully Integrated On-Chip DC-DC Conversion and Power Management System, I J. Solid- State Ciruits, vol. 39, no. 3, pp , Mar [5] D. Maksimovi and S. Dhar, Swithed-Capaitor DC-DC onverters for ow-power On-Chip Appliations, I PSC, 999 eord, pp