Design and Implementation of a 2-GHz Low-Power CMOS Receiver for WCDMA Applications

Transcription

1 Design and Implementation of a 2-GHz Low-Power CMOS Reeiver for WCDMA Appliations Dennis Yee, David Sobel, Chinh Doan, Brian Limketkai, Johan Vanderhaegen, and Robert Brodersen Berkeley Wireless Researh Center Dept. of EECS, University of California, Berkeley {dyee, dasobel, doan, bnl, jpv, rb}@ees.berkeley.edu Abstrat This paper desribes the design and implementation of a 2-GHz single-hip 0.25-µm CMOS reeiver for a ustom WCDMA system. A system-level simulation framework is used to explore the trade-offs between analog front-end impairments and system performane. System speifiations are hosen in order to failitate a low-power highly-integrated implementation. The reeiver is based on a diret-onversion arhiteture and implements all RF omponents, inluding the low-noise amplifier, frequeny synthesizer, and mixers. The reeiver also integrates all baseband omponents along the in-phase and quadrature signal paths, eah of whih inludes a first-order high-pass filter, a seond-order Sallen and Key low-pass filter, and a 7-bit, 25-MS/s Σ analog-to-digital onverter operating at 200 MHz. The reeiver prototype ahieves an 8.5-dB noise figure, provides 41-dB voltage gain, and dissipates 106 mw. I. ITRODUCTIO The desire for ubiquitous information aess ontinues to drive the development of appliations and servies for new wireless systems. The suess of these systems will depend heavily on the ability to provide high apaity while maintaining low ost, small form fator and low power onsumption in the portable devies. These harateristis may be ahieved by adhering to three design strategies. First, at the system level, implementation issues must be onsidered even during the earliest stages of system definition. Seleting system features whih allow for relaxed hardware requirements is paramount to ahieving single-hip low-power reeiver implementations. Seond, effiient implementations require areful partitioning of reeiver funtions between analog and digital hardware. The rapid improvements in mainstream CMOS tehnology failitate the integration of inreasingly more funtionality onto a single hip. In partiular, advaned signal proessing algorithms, whih are very amenable to low-power digital design tehniques, an be used to relax the analog hardware requirements without sarifiing overall system performane. Third, low-power implementation tehniques are required to minimize the power onsumption of the analog front-end. Despite efforts to simplify the analog hardware, the analog front-end an still dominate overall reeiver power onsumption. This paper desribes the design and implementation of a low-power CMOS reeiver whih is intended to be used as the analog front-end of a wideband ode-division multiple aess (WCDMA) system with a arrier frequeny of 2 GHz [1]. System speifiations are hosen in order to failitate the use of a diret-onversion arhiteture, whih is amenable to high levels of integration [2] [4]. All reeiver omponents, inluding the low-noise amplifier (LA), frequeny synthesizer, mixer and analog-to-digital onverter (ADC), are integrated onto a single hip. System speifiations are also hosen in order to relax the performane requirements of the analog hardware without signifiantly degrading overall system performane. Low power onsumption is ahieved by taking advantage of these relaxed performane requirements as well as by using low-power implementation tehniques. Setion II provides an overview of the system design, fousing primarily on the trade-offs between analog front-end impairments and system performane. Setion III provides a brief desription of the system-level simulation framework used to explore these trade-offs, while Setion IV desribes the implementation of the reeiver prototype. Experimental results are presented in Setion V, followed by a brief onlusion in Setion VI. II. SYSTEM OVERVIEW By taking into aount implementation issues during the earliest stages of system definition, system features an be hosen whih relax hardware requirements without sarifiing overall performane [5]. Code-division multiple aess (CDMA) is hosen as the multiple-aess strategy for this system. This diret-sequene spread-spetrum tehnique is attrative from the system performane perspetive sine it provides immunity against multipath distortion [6]. In addition, beause of the wide bandwidth of the CDMA signal, RF Input (f ) RF Filter LA 0 LO (f ) 90 Fig. 1. Diret-onversion reeiver arhiteture. ADC ADC I Q

2 a simple, diret-onversion arhiteture an be used for the reeiver front-end [7], [8]. This arhiteture is illustrated in Fig. 1. The RF signal appearing at the antenna is filtered and amplified before being downonverted to baseband along parallel in-phase (I) and quadrature (Q) signal paths. The frequeny translation is performed using two mixers and a loal osillator (LO) fixed at the arrier frequeny and operating in quadrature. The I and Q baseband signals are then amplified and low-pass filtered prior to analog-to-digital onversion. Beause the RF signal is onverted diretly to baseband, this arhiteture eliminates all intermediatefrequeny omponents and their assoiated design hallenges, inluding the image-rejet problem. The wideband nature of the desired signal helps mitigate one key problem often assoiated with diret-onversion arhitetures: the DC-offset issue. DC offsets are problemati in diret-onversion reeivers sine the desired signal is downonverted diretly to baseband. DC offsets an be aused by systemati offsets in the baseband iruitry, but a potentially more signifiant soure of DC offsets is LO selfmixing. Due to imperfet isolation between the LO and RF ports of the mixer, the LO signal an ouple to the RF signal path and mix with itself, resulting in a DC omponent. For this system, a transmission bandwidth of 32 MHz allows DC offsets to be eliminated with on-hip high-pass filtering. System-level simulations onfirm that the degradation in system signal-to-noise ratio (SR) is less than 1 db for a high-pass orner frequeny of 500 khz. A similar approah is not feasible for most narrowband signals beause a signifiant portion of the desired signal would be removed. Although a wide transmission bandwidth failitates the use of a diret-onversion arhiteture, it also presents design hallenges in the ADC due to the high yquist rate requirement. A transmission bandwidth of 32 MHz offers a good ompromise sine a diret-onversion arhiteture an still be used without signifiantly exaerbating the performane requirements of the ADC. The diret-sequene spread-spetrum signaling sheme also relaxes the noise requirements of the analog front-end, sine the system proessing gain enhanes the SR of the reeived signal. Fig. 2 illustrates the effet of proessing gain on the onstellation diagram of a quadrature phase-shift keying (QPSK) signal in the presene of additive white Gaussian noise (AWG). This additional noise budget is partitioned between the various analog front-end omponents, relaxing the thermal noise requirements of the LA as well as the quantization noise requirements of the ADC. Moreover, the system proessing gain also mitigates the effets of frequeny synthesizer phase noise, reduing the impat of reiproal mixing aused by out-of-band phase noise as well as the amount of phase variation due to lose-in phase noise. Finally, in CDMA systems, all users transmit simultaneously in the same frequeny band. For this system, hannel seletion is performed using multiuser detetion (MUD) tehniques, whih are highly amenable to low-power digital design tehniques [9]. Sine hannel seletion is performed by the baseband digital signal proessing, the analog front-end does not need to provide hannel-selet filtering. In addition, the frequeny synthesizer needs to generate only a single frequeny, whih further simplifies the frequeny synthesizer design requirements after proessing gain before proessing gain Fig. 2. QPSK onstellation diagrams before and after proessing gain. III. SYSTEM-LEVEL SIMULATIO FRAMEWORK The trade-offs between analog front-end impairments and system performane disussed in the previous setion were explored using a system-level simulation framework implemented in Simulink, whih easily interfaes with MATLAB, a popular tool used for ommuniations systems development. Sine short simulation times are ritial for rapid evaluation, a modeling framework whih simulates the analog front-end at the arrier frequeny is unaeptable. For suh a simulation, the maximum step size must be based on the arrier frequeny whereas the total number of steps must be based on the symbol rate. Sine the arrier frequeny is typially muh higher than the symbol rate in wireless ommuniations systems, suh a simulation would be prohibitively slow. In order to derease the simulation time, the simulation framework desribed here relies on baseband-equivalent models for the analog RF building bloks. The method is similar to envelope simulation tehniques used in some RF iruit-level simulators [10]. The baseband-equivalent model for a mixer is desribed below as an example. First, let any real signal be represented by the following expression: s( t ) = s DC [ s In ( t ) os( nω t) s ( t ) sin( nω t )], where s DC (t), s In (t), and s Qn (t) are baseband signals with bandwidths muh less than ω /2. The Fourier transform of s(t) is Qn (1)

3 S(ω) ω ω 0 ½S I2 (ω2ω ) ½S I1 (ωω ) j½s Q2 (ω2ω ) j½s Q1 (ωω ) S DC (ω) Fig. 3. Example spetrum of s(t) in (1). (2) and an example spetrum is illustrated in Fig. 3. Seond, let the transfer funtion of the mixer be expressed as where y i (t), y LO (t), and y o (t) are the input, LO, and output signals, respetively. ext, let y i (t), y LO (t), and y o (t) have the same form as (1): y y = y LO i ( t ) = y y = y o idc LODC odc [ y [ y [ y iin Finally, solve for y odc (t), y oin (t), and y oqn (t) in terms of y idc (t), y iin (t), y iqn (t), y LODC (t), y LOIn (t), and y LOQn (t). By pre-omputing the relationship between these time-varying oeffiients instead of keeping trak of the atual signals, y i (t), y LO (t), and y o (t), the dependene on the arrier frequeny is removed. Consequently, the maximum step size of the simulation is now determined by the symbol period rather than the arrier frequeny. The additional simulation omplexity of this model depends on the number of harmonis,, whih must be hosen in order to aurately model the effets of analog iruit impairments suh as distortion. For typial wireless ommuniations systems, the number of harmonis should be hosen to be at least three. Although the baseband-equivalent model presented above applies only to mixers, a similar method an be used to derive baseband-equivalent models for other analog RF omponents suh as amplifiers and osillators. System-level simulations of RF omponents using these baseband-equivalent models 2ω TABLE I RECEIVER SPECIFICATIOS FOR SYSTEM-LEVEL SIMULATIO Center Frequeny 2 GHz oise Figure (DSB) 13.5 db Gain db I/Q Gain Mismath 4% PLL Phase oise MHz I/Q Phase Mismath 2.5 IIP2 11 dbm IIP3 18 dbm HPF Corner Frequeny 500 khz ADC 7-bit, 25-MS/s Σ ω y = y y, o i os( nω t) y LOIn oin ω ½S I1 (ω ω ) ½S I2 (ω 2ω ) j½s Q1 (ω ω ) j½s Q2 (ω 2ω ) 1 S( ω) = S DC ( ω) {[ SIn( ω nω) SIn( ω nω )] 2 j[ S ( ω nω ) S ( ω nω )]} Qn LO iqn ( t ) os( nω t) y os( nω t ) y Qn sin( nω t)], LOQn oqn ( t ) sin( nω t )], sin( nω t)]. (3) (4) (5) (6) result in rapid simulation times without sarifiing auray. By speifying appropriate funtions for the time-varying oeffiients, these baseband-equivalent models inherently aount for many iruit impairments in the RF omponents, inluding distortion, phase noise, quadrature phase offset, frequeny offset, and DC offsets. This simulation framework was used to explore the design trade-offs disussed in Setion II. A omplete system-level simulation was performed with the speifiations listed in Table I. Fig. 4 illustrates the signal onstellation diagrams at the output of the analog front-end and at the output of the digital signal proessing blok whih implements the MUD algorithm. Even with these relaxed speifiations, the reeiver still ahieves the required output SR of 15 db, whih orresponds to an average bit-error rate of digital output analog output Fig. 4. Constellation diagrams from system-level simulation. IV. RECEIVER PROTOTYPE The diret-onversion reeiver is integrated onto a single hip and implements all ritial reeiver funtions, inluding low-noise amplifiation, LO signal generation, frequeny translation, and analog-to-digital onversion. All iruits on this hip use a 2.5-V supply. A fully-differential signal path is used in order to mitigate the oupling between different reeiver omponents as well as to redue the amount of evenorder distortion. The RF input signal and frequeny synthesizer rystal referene are both onverted to differential signals using external baluns. The LA is apaitively oupled to the RF ports of the I and Q mixers, while the frequeny synthesizer onnets diretly to the LO ports. In addition, the frequeny synthesizer outputs are loated immediately adjaent to the mixer LO ports in the layout, reduing the load apaitane to about 30 ff, and thus avoiding the use of lok buffers. Along eah baseband signal path, a high-pass filter is used to eliminate DC offsets, while a Sallen and Key low-pass filter attenuates out-of-band signals

4 before the I and Q signals are eah digitized by a sigma-delta (Σ ) ADC. Eah iruit blok will now be desribed in more detail. A. Low-oise Amplifier The LA is implemented using the indutivelydegenerated ommon-soure amplifier topology [11], [12] illustrated in Fig. 5. Indutors L 3 and L 4 help to ahieve 50-Ω input mathing while load indutors L 5 and L 6 provide additional filtering at the LA output. These four indutors are realized as on-hip spiral indutors whih use the top three layers of metal to maximize indutor quality fator. Input tuning is performed through indutors L 1 and L 2, eah of whih is realized as a ombination of the input bond wire and an external hip indutor. The LA input bond pads are reessed about 300 µm from the edge of the hip in order to aommodate longer input bond wires, and onsequently, higher indutane values. The LA is biased at 4.5 ma and is powered by a separate 2.5-V supply, whih helps to isolate the LA from the potentially noisy supplies of the other reeiver iruits. While the asode transistors M 3 and M 4 slightly degrade the noise performane of the LA, they provide inreased reverse isolation, reduing the amount of LO leakage from the mixer to the reeiver input. V out - V bias L 5 L 6 M 3 V out V in M V - 1 M 2 in L 1 L 2 L 3 L 4 Fig. 5. Low-noise amplifier. B. Frequeny Synthesizer The 2-GHz I and Q LO frequenies are generated using a fully-differential, wide-bandwidth phase-loked loop (PLL) depited in Fig. 6. The PLL has a loop bandwidth of 3 MHz. An external 50-MHz rystal referene is used to lok the output signal from the voltage-ontrolled osillator (VCO) to 2 GHz. The VCO is implemented as a 4-stage ring osillator, whih inherently provides the I and Q outputs required for quadrature demodulation. The VCO I and Q outputs are onneted diretly to the mixer inputs, while a third output is onneted to the divider. Dummy divider iruits are onneted to the remaining VCO output in order to provide load mathing for improved quadrature generation. The phase noise of the ring osillator VCO is suppressed by the widebandwidth PLL [13], thus improving the overall phase noise performane of the frequeny synthesizer. M 4 Both the VCO and the high-frequeny stages of the divider are realized using soure-oupled logi. Although these iruits onsume stati power, this logi style minimizes the amount of high-frequeny urrent noise injeted into the substrate, whih would be detrimental to the operation of other RF iruit omponents, suh as the LA. Finally, a separate 2.5-V supply is used for the phase-frequeny detetor (PFD) and the last stage of the frequeny divider in order to prevent digital swithing noise from oupling into the analog iruit omponents. f ref = 50MHz PFD Fig. 6. Phase-loked loop. CP/LF 40 VCO f out = 2GHz C. Mixer Frequeny translation from RF to baseband is performed by a pair of double-balaned Gilbert ell mixers, illustrated in Fig. 7. This topology provides exellent isolation between the LO and RF ports of the mixer, whih is further improved by adding asode transistors M 3 and M 4. The sizes of transistors M 5 M 8 are hosen as a ompromise between fliker noise performane of the mixer and power onsumption in the VCO. Sine the VCO outputs are diretly onneted to these transistors, small devie dimensions are desirable in order to redue the apaitive loading on the VCO. On the other hand, large devie dimensions are desirable for improved fliker noise performane. Beause of the wideband nature of the desired signal, the mixer s fliker noise performane is relaxed in favor of redued power onsumption in the frequeny synthesizer. The load devies M 9 and M 10 are biased in the linear region and their resistanes an be hanged by adjusting their gate bias voltages to provide variable gain apability. Eah of the I V load V LO V asode V in Fig. 7. Gilbert ell mixer. M 5 M 1 M 9 V out M 10 M 6 M 7 M 8 M 3 M 4 M 2

5 and Q mixers is biased at a tail urrent of 420 µa. D. Baseband Amplifiation and Filtering A blok diagram of the baseband setion [12], [14] is illustrated in Fig. 8. Immediately after frequeny translation, shunt 1-pF apaitors in ombination with the mixer output impedane provide first-order low-pass filtering of eah of the baseband I and Q signals. A noninverting amplifier then provides moderate gain in order to redue the impat of noise ontributed by subsequent stages. Eah of the baseband signals then passes through a firstorder high-pass filter, whih removes DC offsets and fliker noise from previous reeiver stages. Eah filter is realized using on-hip passive strutures, whih inlude a pair of 40-pF apaitors and a pair of 45-kΩ resistors, plaing the high-pass orner frequeny at about 90 khz. The 32-MHz bandwidth of the desired signal makes this method of DCoffset ompensation pratial sine the high-pass orner frequeny an be relatively high, whih permits the use of only moderately sized on-hip passive strutures. ext, the output of the high-pass filter is buffered before passing through a seond-order Sallen and Key low-pass filter. The poles of the Sallen and Key filter in ombination with the pole at the mixer output provide an overall thirdorder Butterworth low-pass frequeny response, whih offers a good ompromise between linear phase and maximally flat gain. This low-pass filter provides attenuation of out-of-band signals as well as anti-alias filtering for the subsequent Σ ADC. amplifier HPF buffer Sallen and Key LPF Vin Vout Vin- devies to maximize speed. The devie sizes and bias points of eah amplifier are optimized for minimum power onsumption. In addition, dynami omparators are used to implement the single-bit quantizers for redued power onsumption. 1/3 3/5-2/5 DAC 5/6-1/2 DAC 1/3 DAC Fig asade Σ arhiteture. V. MEASUREMET RESULTS The diret-onversion reeiver was fabriated in a 0.25-µm, single-poly, 6-metal CMOS proess and oupies an area of 5.0 mm 5.2 mm inluding bond pads. The iruit ative area is about 5 mm2. A die photo is shown in Fig. 10. The reeiver prototype is diretly attahed to the testboard using hip-on-board pakaging tehnology. An external balun provides a differential RF input signal to the reeiver and a pair of hip indutors omplete the LA input tuning. The reeiver performane measurements are summarized in Table II. The reeiver input provides an exellent math to 50 Ω with an S11 better than 30 db at 2 GHz, and the reeiver noise figure is 8.5 db, whih inludes approximately Vout- Fig. 8. Baseband amplifiation and filtering. E. Sigma-Delta Analog-to-Digital Converter Sine oversampling failitates digital timing reovery, a Σ onverter beomes a natural hoie for analog-to-digital onversion [15]. The baseband I and Q signals are digitized using a pair of 7-bit, 25-MS/s Σ ADCs operating at 200 MHz. Sine the high yquist rate of the baseband signals restrits the Σ onverter to a low oversampling ratio of 8, the required dynami range is ahieved by using a asade arhiteture with single-bit quantization in eah stage (Fig. 9). Eah of the 200-MHz output signals from the three stages is multiplexed into three slower output streams before being brought off the hip. The swithed-apaitor integrators are implemented using folded-asode operational amplifiers with MOS input I Σ Q Σ baseband filters PLL mixer LA Fig. 10. Chip mirograph.

6 1 db of insertion loss from the external balun. The reeiver gain is 41 db with less than 0.5-dB gain mismath between the I and Q paths, indiating exellent gain mathing along the baseband signal paths. The frequeny synthesizer phase noise is 85 db/hz at a 2.5-MHz offset, and the Σ ADC has a dynami range of 42 db when operating at a frequeny of 200 MHz. The reeiver input 1-dB ompression point is 31.1 dbm while the out-of-band IIP2 and IIP3 are 6.7 dbm and 18.3 dbm, respetively (Fig. 11). The reeiver s total power onsumption is 106 mw. Baseband Output Power (dbm) TABLE II RECEIVER PERFORMACE MEASUREMETS Center Frequeny 2 GHz oise Figure (DSB) 8.5 db S11 < 30 db Voltage Gain 41 db 3-dB Bandwidth 89.8 khz < f < 17.9 MHz 1-dB Compression 31.1 dbm IIP2 (27 MHz, 37 MHz) 6.7 dbm IIP3 (35 MHz, 60 MHz) 18.3 dbm PLL Phase oise MHz LO-to-RF Leakage 81 dbm Σ Dynami Range MHz Power Dissipation LA 12 mw LO 25 mw I/Q Mixers 3 mw I/Q Baseband 7 mw I/Q Σ ADCs 59 mw Total 106 mw Fundamental 2nd Order IM 3rd Order IM Reeiver Input Power (dbm) Fig. 11. Measured gain and distortion. VI. COCLUSIO By taking into aount implementation issues during the earliest stages of system definition, system features an be hosen whih relax hardware requirements without sarifiing overall performane. A system-level simulation framework is presented whih failitates the exploration of suh trade-offs. This framework is used to determine speifiations for a ustom WCDMA system and a 2-GHz diret-onversion reeiver is designed to meet these speifiations. The prototype reeiver is implemented in a 0.25-µm CMOS proess and integrates all ritial reeiver omponents, inluding the LA, frequeny synthesizer, mixers, baseband filters, and ADCs, onto a single hip. Low power onsumption is ahieved by taking advantage of the relaxed performane requirements as well as by using low-power implementation tehniques. ACKOWLEDGMET The authors would like to thank J. Rudell, J. Ou, A. iknejad, C. Teusher, and K. Kundert for their advie and support. The authors would also like to aknowledge S. Alalusi and D. Coates for helping with the testboard and STMiroeletronis for wafer fabriation. This researh was funded by DARPA and the industrial members of the Berkeley Wireless Researh Center. REFERECES [1] C. Teusher, D. Yee,. Zhang, and R. Brodersen, Design of a Wideband Spread Spetrum Radio Using Adaptive Multiuser Detetion, IEEE ISCAS, May 1998, pp [2] A. Abidi, Diret-Conversion Radio Transeivers for Digital Communiations, IEEE JSSC, vol. 30, no. 12, Deember 1995, pp [3] C. Hull, J. Tham, R. Chu, A Diret-Conversion Reeiver for 900 MHz (ISM Band) Spread-Spetrum Digital Cordless Telephone, IEEE JSSC, vol. 31, no. 12, Deember 1996, pp [4] T. Cho, E. Dukatz, M. Mak, D. Manally, M. Marringa, S. Mehta, C. ilson, L. Plouvier, S. Rabii, A Single-Chip CMOS Diret- Conversion Transeiver for 900 MHz Spread-Spetrum Digital Cordless Phones, IEEE ISSCC, 1999, pp [5] S. Sheng and R. Brodersen, Low-Power CMOS Wireless Communiations: A Wideband CDMA System Design. Boston: Kluwer Aademi Publishers, [6] J. Proakis, Digital Communiations. ew York: MGraw-Hill, [7] B. Razavi, A 2.4-GHz CMOS Reeiver for IEEE Wireless LA s, IEEE JSSC, vol. 34, no.10, Otober 1999, pp [8] A. Pärssinen, J. Jussila, J. Ryynänen, L. Sumanen, and K. Halonen, A 2-GHz Wide-Band Diret Conversion Reeiver for WCDMA Appliations, IEEE JSSC, vol. 34, no. 12, Deember 1999, pp [9]. Zhang, A. Poon, D. Tse, R. Brodersen, and S. Verdu, Trade-offs of Performane and Single Chip Implementation of Indoor Wireless Multi-Aess Reeivers, IEEE Wireless Communiations and etworking Conferene, September 1999, pp [10] K. Kundert, Introdution to RF Simulation and Its Appliation, IEEE JSSC, vol. 34, no. 9, September 1999, pp [11] D. Shaeffer and T. Lee, A 1.5-V, 1.5-GHz CMOS Low oise Amplifier, IEEE JSSC, vol. 332, no. 5, May 1997, pp [12] J. Rudell, J.-J. Ou, T. Cho, G. Chien, F. Brianti, J. Weldon, and P. Gray, A 1.9-GHz Wide-Band IF Double Conversion CMOS Reeiver for Cordless Telephone Appliations, IEEE JSSC, vol. 32, no. 12, Deember 1997, pp [13] L. Lin, L. Tee, and P. Gray, A 1.4GHz Differential Low-oise CMOS Frequeny Synthesizer using a Wideband PLL Arhiteture, IEEE ISSCC, February 2000, pp [14] T. Cho, G. Chien, F. Brianti, and P. Gray, A Power-Optimized CMOS Baseband Channel Filter and ADC for Cordless Appliations, Symposium on VLSI Ciruits, 1996, pp [15] H.-K. Yang and M. Snelgrove, Symbol Timing Reovery Using Oversampling Tehniques, IEEE International Conferene on Communiations, June 1996, pp