Current-Mode Control Stability Analysis For DC-DC Converters (Part 2)

Transcription

1 ISSUE: July 24 urrent-mode ontrol Stability Analysis For D-D onverters (Part 2) by Timothy Hegarty, Silion Valley Analog, Texas Instruments, Phoenix, Ariz. In this artile, part 2 o 2, e disuss urrent-mode ontrol loop ensation [] or industrial and automotive appliations. Starting rom the small-signal model, simple expressions are derived that yield an intuitive proedure or designing the ensator or a urrent-mode-ontrolled buk onverter. Even ith an error ampliier o inite gain-bandidth, the simpliity and onveniene o this design proedure makes it viable or everyday use by the pratiing poer eletronis engineer. To bolster the theoretial analysis, an atual design example based on a ommerially available PWM regulator is presented here ith simulation used to veriy the results obtained rom the aorementioned design proedure. This disussion assumes some understanding o urrent-mode ontrol and ho it s modeled. For those ho ant to revie urrent-mode operation and small-signal modeling, hek out Part again. [] ompensator Transer Funtion A type-ii ensator using an error ampliier (EA) ith transondutane, g m, is shon in Fig.. V out Error Ampliier Model b2 OMP FB g m + V re h pea2 zea pea b b Fig.. Small-signal representation o an operational transondutane EA. The onent ombinations representing to poles and one zero are irled. The dominant pole o the EA open-loop gain harateristi is set by the EA output resistane,, and the eetive bandidth-limiting apaitane, b, as in equation : G ( ) (s) gm s. () EA openloop The inluene o any EA high-requeny poles, hether parasiti or inluded by design, is negleted in the above expression. The ensator transer untion rom output voltage to OMP, inluding the gain ontribution rom the eedbak resistor divider netork, is given by b v (s) G (s) AbgmZ (s) (2) v (s) out 24 Ho2Poer. All rights reserved. Page o

2 ith Z (s) g m s s s h b (3) and the eedbak attenuation ator is A b Vre b V out b b2. (4) Evaluating equation 3 gives an expression o the orm Z (s) s zea 2 pea pea pea2 s s. (5) As pea and pea2 are ell separated in requeny, the lo-q approximation applies and equation 5 beomes Z (s) s zea s s pea pea2 (6) here zea ; pea pea2 Typially,, h b h b h b and the approximations set orth in equation 7 are valid. irled in Fig. are the onents to provide to ensator poles and one ensator zero. Fig. 2 gives an example o the typial requeny response o both the open-loop EA and the ensator. h ; ;. and (7) 24 Ho2Poer. All rights reserved. Page 2 o

3 pea 2 pea( openloop) 2 b pea2 2 h g m 6 EA Open-Loop Gain Gain (db 2 EA Open-Loop Phase ompensator Gain 45 Phase ( -2 ompensator Phase Frequeny (khz) zea 2 Fig. 2. Small-signal requeny responses o open-loop EA and ensator. GBW gm 2 In this example, the eedbak attenuation is unity, and the EA has 5 db o open-loop d gain and a 5-MHz bandidth. Again, the poles and zeros are denoted ith x and o symbols, respetively, and a + symbol indiates the EA bandidth. Not inluded in the phase plots is the 8 phase lag ontribution related to the EA in the inverting oniguration. ompensator pole pea appears at very lo requeny and is easily replaed by an integrator term. The ensator transer untion simpliies to b s A G (s) s s zea pea (8) here the integrator gain term, A, is given by A g m Ab. (9) 24 Ho2Poer. All rights reserved. Page 3 o

4 Note that both eedbak resistors, b and b2, ator into the ontrol-loop gain hen a transondutane-type EA is used. In ontrast, i an operational ampliier-type EA is employed, the FB node is eetively at a ground and the loer eedbak resistane bears no inluene on the loop dynamis. ompensator Design A requently used ensation strategy that generally applies to peak, valley, and emulated urrent-mode iruits is to equate the ontrol-to-output transer untion to the ensator transer untion term-by-term to attain a single-pole ( 2 db/deade) roll o o the loop response. To demonstrate, onsider one ensator pole, pea, positioned to provide high gain in the lo-requeny range, minimizing output steady-state error or best load regulation; one ensator zero loated to oset the dominant load pole, zea = p, hih typially is the minimum load resistane (maximum load urrent) ondition used; and one ensator pole positioned to anel the output apaitor ES zero, pea2 = esr. The loop gain is expressed as the produt o the ontrol-to-output and ensator transer untions. From equation 5 in part and equation 8, the loop gain is d zea esr v. () 2 T(s) G (s) G (s) s A s A s s s s s 2 pea p Qωn n Selet the rossover requeny = 2 (here the loop gain is db) beteen one-tenth and one-ith o the sithing requeny. I zea = p and pea = esr, the loop gain redues to T s AA d 2 s s s 2 Qωn n. () Assuming a ell-designed urrent loop (.5 Q ), the sampling gain ontribution is insigniiant at requenies up to the rossover requeny. This assumption preludes the ase here too muh slopeensating ramp is added. The magnitude o the loop gain at the dominant pole requeny is zea Using basi Bode plot priniples, it is apparent that T j T j A A g A A. (2) p d m b d T j p Thus derived, a straight-orard solution or the rossover requeny is. (3) p pgmab Ad. (4) 24 Ho2Poer. All rights reserved. Page 4 o

5 Finally, ensator onent values are alulated sequentially as g A A m b d p h 5 esr b (5) b b2 V V out re. The ensator zero is positioned at one-ith o the target rossover requeny. An initial value is seleted or b2 based on a pratial minimum urrent level loing in the divider hain. Note that the ensation zero requeny represents the dominant time onstant in a load-transient response. A large apaitor is thus antithetial to a ast transient response settling time. is adjusted mainly to tradeo phase margin and settling time. A phase margin target o 5 to 6 is ideal. Furthermore, a smaller ensation apaitane is advantageous, i the transondutane EA has a lo output-drive-urrent apability. ompensator Design Example The iruit operating onditions, key onent values and ontrol iruit parameters or the LM235 peakurrent-mode synhronous-buk PWM regulator [2] are speiied in the Table. A sithing requeny o 4 khz provides a suitable tradeo o eiieny versus size. [3] Table. Buk onverter parameters or a peak-urrent-mode synhronous-buk PWM regulator (LM235). V in 8 V to 8 V s 4 khz b 38 pf V out 5 V d 36 m V slope.462 V I out 5 A esr 7 m S e.85 V/s D.43 i 5 m S n.245 V/s L 3.3 H 43 k m.754 out F g M 2.4 ms Q Ho2Poer. All rights reserved. Page 5 o

6 With 2-V nominal input, the relevant gains and orner requenies are alulated using expressions rom part as K M T V s slope.5 D i L V in 2.5μs.462V.5.435m 3.3μH 2V 22.4 A d p esr KMout K out d s M i m m 2πout out KMi 2π 55μF m kHz 43kHz 2 2π 7m 55μF esr out. (6) I the output apaitor is erami, a apaitane derating or applied voltage is neessary. In these alulations, a derating o 45% is used. Given a target rossover requeny o 6 khz, using the equations in 5, the ensation onent values are ound as gm Ab Ad p 6kHz 8.4k.598V 4.kHz 2.4mS 6.9 5V 5 5.6nF 2π 6kHz 8.4k h b esr 2π 43kHz 8.4k 38pF = 8pF (7) V out V re 5V = k 73.6k.598V b b2. 24 Ho2Poer. All rights reserved. Page 6 o

7 Fig. 3 shos Mathad-derived loop gain and phase plots or the example onverter. The equivalent plots ith an ideal EA are also shon ith dashed lines. (The nonideal EA has a bandidth-limiting apaitane, b, hih appears in parallel ith h as shon above in Fig..) The phase margin (PM or M ) is the dierene beteen the loop phase and 8 (EA inversion phase lag ontribution not inluded). Note that i h is not installed, the EA itsel provides high-requeny attenuation by virtue o its inite gain-bandidth. 8 Loop Gain, Ideal EA ompensator Pole 9 Gain (db Loop Gain, Non-Ideal EA Loop Phase, Non-Ideal EA Loop Phase, Ideal EA Load Pole ompensator Zero Sampling Gain Pole Phase ( M = Frequeny (khz) = 6kHz ompensator Pole -225 Output apaitor ES Zero Fig. 3. Buk onverter loop gain and phase plots based on the LM235. ontrol Loop Simulation Using an LM235 PWM regulator in a buk onverter oniguration per Table, a SIMetrix/SIMPLIS [4] sithing model iruit simulation is run to substantiate the just-leted analysis. Fig. 4 presents the model shemati. The loop gain T v (s) o the system is measured by breaking the loop at the upper eedbak resistor, injeting a variable-requeny osillator signal, and analyzing the requeny response. The element ith reerene designator X in Fig. 4 is the SIMPLIS lok edge trigger to ind the iruit s periodi operating point (POP) beore running the a analysis. POP analysis orks on the ull nonlinear sithing time-domain model o the iruit and enables subsequent a or transient analyses. The a soure ith reerene designator V inj in Fig. 4 is the input stimulus or the a seep and its amplitude is automatially ontrolled to keep the a response in the linearized small-signal region. Fig. 5 illustrates a Bode plot simulation result that aligns losely ith the analytial result in Fig Ho2Poer. All rights reserved. Page 7 o

8 Vin 2 m s X D S High-side MOSFET urrent sense amp i=gi*s 5 Gi Vslope Slope PWM arator Vramp Mod lok U S Q D QN Vlok T = 2.5 us PWM lath 3.3u 5m L dr S2 Lo-side MOSFET IN OUT =OUT/IN Vo = 5V A Vinj 55u o 7m esr Output ontrol o Vo Itran Loop injetion: Vinj is input stimulus or A seep External 8p h V 8.4k 38p 43k.598 b 24u Vre.5n g m amp gm FB 73.6k b2 k b Fig. 4. SIMPLIS a and transient analysis simulation shemati or the LM235-based buk onverter. Lo-requeny loop gain, A d Y Y EA dominant pole Loop Gain 4 Gain / db 2-2 Phase / degrees 5 5 Loop Phase rossover requeny Phase margin k 2k 5k k 2k 5k k 2k 5k M req / Hertz Fig. 5. esults o Bode plot simulation. Using a SIMPLIS time-domain transient analysis, load-on and load-o transient responses are obtained (see Fig. 6) ith high (3.9 nf) and lo (.5 nf) ensation-apaitor values hosen so that the ensator zero is 24 Ho2Poer. All rights reserved. Page 8 o

9 loated diretly at the load pole and the poer stage resonant requenies, respetively. The load step is rom 5% to % ull load at A/s. It is evident that the loer ensation apaitane results in a muh more avorable settling time. Interestingly, this is ahieved ith very little relative hange in the Bode plot approximately -khz derease in rossover requeny and 4 less phase margin using the.5-nf apaitor. Y2 Y Output urrent V out ith =.5nF IOUT / A 3.5 VOUT / V V out ith = 3.9nF time/mses Fig. 6. Load-step transient response simulation ith.5-nf and 3.9-nF ensation apaitane. 2uSes /div onlusion Simple expressions or urrent-mode ontrol yield an easy and straightorard outline or ensating a buk onverter. Understanding the requeny-domain Bode plot inormation helps to optimize the time-domain load transient response aveorm. The reader is enouraged to onsider the appliation to other peak-urrent-modeontrolled onverter topologies like boost or lybak, and to onsult orks suh as reerene 5, hih provide urther bakground and analysis o urrent-mode ontrol. eerenes. urrent-mode ontrol Stability Analysis For D-D onverters (Part ), by Timothy Hegarty, Ho2Poer Today, June 24 issue. 2. LM235 5-A urrent-mode Synhronous Buk egulator EVM. 3. The Buk egulator Eiieny/Size Tradeo Dilemma, Poer House, Texas Instruments, Deember 2, SIMetrix/SIMPLIS simulation sotare. 5. urrent-loop ontrol In Sithing onverters, by Dennis Feuht, Ho2Poer Today, September 2 through Marh 22 issues. Ater revieing the history o urrent-loop ontrol theory (i.e. ho to aurately model urrent-mode ontrol), this artile series attempts to lariy established onepts, identiy problems ith the existing theories or models o urrent-mode ontrol, and oer hat might be the irst truly uniied model o urrent ontrol. 24 Ho2Poer. All rights reserved. Page 9 o

10 About The Author Timothy Hegarty is a systems engineer ith the Texas Instruments Silion Valley Analog group. He reeived his bahelor s and master s degrees in eletrial engineering rom University ollege ork, Ireland. His area o interest is integrated PWM sithing regulators and ontrollers or ide input voltage range industrial and automotive appliations. He is a member o the IEEE Poer Eletronis Soiety. You an reah Tim at ti_timhegarty@list.ti.om. For urther reading on poer supply ontrol methods, see the Ho2Poer Design Guide, selet the Advaned Searh option, go to Searh by Design Guide ategory and selet ontrol Methods in the Design Area ategory. 24 Ho2Poer. All rights reserved. Page o