THE specifications for modern microprocessor voltage regulation modules (VRM s) require that the microprocessor

Transcription

1 7 Fast VRM Arhiteture with Estimate Loa Current Feeforwar I. INTRODCTION THE speifiations for moern miroproessor voltage regulation moules (VRM s) require that the miroproessor supply voltage follows a loa line [], () where is a referene voltage, is the esire loa line slope (or regulator output impeane), an is the urrent supplie to the miroproessor loa. This approah is also known as aaptive or optimal voltage positioning [2]. Table I gives sample miroproessor VRM speifiations refleting urrent inustry trens. One of the main hallanges of VRM esign is hanling the large, high-slew-rate loa urrent steps, at low miroproessor supply voltages, an tight regulation tolerane. For fast loa urrent transients, the regulator output impeane epens on both the size of the output apaitors an the elay of the VRM ontroller [3]. In fat, given a finite loa urrent slew rate an a ontroller response fast ompare to the loa slew time, the onverter lose-loop output impeane an be mae smaller than the output apaitor effetive series resistane (ESR). Thus, it is benefiial to evelop ontrollers with very fast response in orer to avoi the nee for very large output apaitors. II. CONTROLLER ARCHITECTRE Fig. shows the blok iagram of a typial miroproessor multi-phase VRM. In the analysis below the multi-phase onverter is moelle as a single phase onverter for simpliity, while in Setion III a full four-phase onverter is simulate. A. Fast Response with Output Current Feeforwar The problem of following aurately a loa line an be approahe as a referene traking problem, where has to trak the right-han sie of (). A ommon approah in traking problems is to use feeforwar from the referene signal to the output to hanle the bulk of the regulation ation, an use the feebak only to ompensate for the imperfetions of the feeforwar []. This approah an generally hanle better fast referene signal hanges ompare to pure feebak regulation, sine the gain an banwith of the feeforwar are not limite by stability onsierations. Inee, with ieal loa urrent feeforwar, a swithing onverter an have zero output impeane [5]. B. VRM moelling A ontrol blok iagram of the VRM with loa urrent feeforwar is shown in Fig. 2, where! #" %$&(' #)+ %,.-/' 0) 2$3 ) $&0' 5)6 (2) In this isussion we are assuming that 8: is onstant. In moern miroproessor systems 89?;= an be ajuste uring operation, but this happens at slow rates ompare to hanges an hene traking it oes not present a substantial hallenge. In fat, a simple an effetive referene voltage feeforwar, proviing goo traking up to the BDC utoff frequeny, an be aomplishe by iretly aing 8>9?;= to the input of the PWM moulator, 8E. TABLE I PROTOTYPE VRM SPECIFICATIONS FFGIH input voltage 2 V referene output voltage V J P ALK J MDNO ma loa urrent 00 A ARQ PS ma loa slew rate 50 A/T s X 9?;= F lose-loop output impeane.25 V/W A output tolerane ban 50V F?Y[Z%Y

2 ^ A e e ] ` Vref Vin L L2 _ A?A Power Train \ A L3 L I L Co Vo \ E feeforwar =L= Ca=R= 9?;= =Lb feebak C =b \ ; \ 9?;= Fig.. Four-phase VRM blok iagram. Fig. 2. VRM ontrol blok iagram with loa urrent feeforwar. is the transfer funtion between the ontroller omman an the output voltage, with parameters efine in Table II, -f"+-#g?hi, an $ 3 "+jk2$:gml ) $no g hip ) jqr$%sto g hi ) $ g<hi moelling respetively the total power train inutane an series resistane. The open-loop output impeane is u# 0" $ 3 %$&0' 5)+.-/h$ 3 )+,-/' 0) 2$!3 ) $!&#' 5)+ an v is the esire lose-loop output impeane. Transfer funtions ' w an ' : represent the feebak an feeforwar ontrol laws, respetively. The elay an banwith of the feebak an feeforwar paths are moelle by w!" y{z}~% K =b!h 5 ƒ )+ an : 0" yz}?~% K =L=!h 5 ƒ )+ with parameters efine in Table II. Base on the Fig. 2 the onverter lose-loop output impeane is alulate to be u# " u0 #)f ) (3) () (5) :w ' w0 : ' % w ' w (6) C. Feebak Control Law The feebak ontrol uses a stanar PID law with an aitional high-frequeny pole, ' w #"+ ˆ ) The erivative term zero is plae slightly above the -/' Š J ) Šƒ Œ!Ž )+ (7) utoff frequeny to provie v B/e rolloff. The high frequeny pole [Ž is esigne to approimately anel the output apaitor ESR zero, thus maintaining the B/e slope. The feebak ontrol law parameters for the present esign are given in Table II.

3 & K K ˆ TABLE II PROTOTYPE VRM DESIGN Power train ƒ G number of phases phase inutane 80 nh G phase in. resistane V W A output apaitane 800 T F (erami) G H output apaitor ESR V/W G input soure impeane V W G low-sie sw. on-resistane 3.2 V/W high-sie sw. on-resistane 8.6 V W r >š efault uty ratio /2 swithing frequeny 500 khz proportional gain 5 ~œ integral time 32 T s ~! erivative time 2.9 T s ž 7 high freq. pole 0.6 T s ~ K =L= feeforwar elay 00 ns ~ K =b feebak elay 767 ns Ÿ ontroller banwith 2 2 Mra/s D. Feeforwar Control Law The feeforwar ontrol law an be erive by setting the lose-loop output impeane (6) equal to the esire value, ' : 0 % u0 Œ+", ' - ª«) :& ) $ 3 ' % :& )+ : ªD ) where & " $ & ' is the output apaitor time onstant. The above epression an be simplifie base on a few assumptions: The seon orer term in the numerator is small an an be ignore if $ &±. It an also be ignore if $&6², resulting in a small unershoot of % from the esire trajetory. In the first orer numerator term the time onstant -/h ³ ominates the other time onstants in a typial esign, so the latter an be neglete. The DC term in the numerator an be ignore sine $ µ 3 : an sine the feebak ontrol eliminates steay state errors. Further, the term in the enominator an be neglete if the feeforwar path has small elay an high banwith. PWM moulation shemes that satisfy the latter will be isusse in Setion II-G. Finally, with the above assumptions (8) beomes ' : ± 9?;= ª -/h % & )+ (9) Thus, the esign of the feeforwar ontrol law requires knowlege only of the onverter inutane an output apaitor time onstant. E. Estimating the Loa Current The ontrol strategy isusse above assumes that the loa urrent is measure. Sensing the loa urrent iretly is not pratial sine it will require inserting a sensing resistor after the output apaitor, thus inreasing the output impeane, or using an epensive Hall-effet urrent sensor. Alternatively, the loa urrent an be reonstrute from &. estimates of the inutor an apaitor urrents [3], sine I " The inutor urrent an be estimate with an ' network onnete in parallel to the inutor. This approah has been use suessfully in ommerial prouts [6]. In the VRM implementation blok iagram in Fig. 3 the four phases have been moele as a single phase with quarter of the inutane an inutor an swith resistane. An estimator onsisting of o an ' o is onnete aross the inutor. If the time onstant of the estimator mathes the time onstant of the inutor, o ' o " + "6-/h$, the voltage aross ' o $ is equal to the voltage aross. The inutor urrent an then be estimate by iviing the voltage aross ' o by an estimate of the inutor resistane $. For goo mathing the temperature epenene of $ has to be ompensate for in the sensing amplifier [6]. Further, in an atual four phase onverter the phase urrents have to be summe, whih an be ahieve by splitting o in four resistors onnete to the four swithing noes, an terminating on a single ' o. Analogously, the apaitor urrent & an be estimate from the output voltage with an ' network mathing the time onstant of the output apaitor [3]. In Fig. 3, & o an '/& o are hosen suh that & o ' & o " :&¹ + :&. The apaitor urrent is erive by iviing the voltage rop aross & o by an estimate of the output apaitor ESR, $&. " In the ase of perfet mathing of the estimator an power train parameters,, the injetion of in the ontroller oes not affet the lose-loop poles an zeros of the system. In pratie, there typially is some mismath between the estimator an power train parameters, resulting in beoming a funtion of the onverter state variables (8)

4 È ÛÜ Ø ½pÑIÒ É ÃÊ PWM Moulator ½pÎ ½pÙ Ï Á Power Train ºRÁ ½» º РϼРÄ5» º¼» É ÃÊD Ë?Ì.Ì Å ÆÇ Ä5Ì.Ì feebak Ä5Ì.Ú feeforwar ½ Ë À Õ Ë?Ì ½» ºR» º Ð ºLÁ Estimator Ó Ô ÕrÖ Ó Ô Õr À Á à Ä(ÁÂ Ã Ä Ð Â Ã À Ð Â Ã ½ Õ Ë?Ì Fig. 3. VRM implementation blok iagram. an hene altering the system pole an zero loations. For small mismathes this effet is small, an an be tolerate in a robustly esigne ontroller. However, this assumption shoul be verifie at esign time base on epete omponent an iruit toleranes. F. Critial Inutane The above isussion assumes that the onverter uty ratio oes not saturate, i.e., >Ý in Fig. 3 oes not reah or groun. In pratie satisfying this assumption is hallenging ue to the small inutor voltage rop ( V) available uring unloaing transients. For the uty ratio to remain unsaturate uring large unloaing transients, the total onverter inutane -f"+-þžßtß¼àààßtß -#á has to be below ertain ritial value - Ý g S [3], [7]. The ritial inutane alulation has previously been one assuming an infinite-slew-rate loa urrent step [3]. Taking into aount the finite slew rate of the loa urrent, a less onservative value for - Ý g S an be erive. (Derivation will be shown in the omplete paper). For the speifiations in Table I, - Ý g S " nh eah. 23 nh, hene phase inutors were esigne for â G. PWM Moulator The implementation of a swith moulation sheme having a very short elay is essential for ahieving a very fast ontroller response. A stanar PWM moulation sheme without lathing appears a suitable hoie in this respet. It ompares the ontrol signal!ý to a triangular or sawtooth moulating waveform at the swithing frequeny (Fig. 3). Multi-phase operation is ahieve by using phase-shifte moulating waveforms for the ifferent phases. The ontrol signal fe into the PWM moulator is the sum of the outputs of the feeforwar an feebak ontrol laws. The loa urrent feeforwar signal ieally has no ripple relate to the onverter swithing sine it is erive from an eogenous variable. Thus, the output of the feeforwar ontrol law ' % an be fe iretly into a non-lathe PWM moulator without ausing unesirable high-frequeny behavior. The feebak signal, however, an have a substantial ripple resulting from the swithing ation an the erivative term in ' w. Swithing frequeny ripple in the ontrol signal an lea to unesirable limit yling an haoti behavior o : " [8]. hi To prevent this from happening, a samplean-hol (S/H) operating at the effetive swithing frequeny ã <ä ã <ä is introue in the feebak path, thus eliminating swithing ripple from the ontrol signal. The sample-an-hol is preee by a resettable integrator (å ) gml

5 V o V o V V (a) nominal power train (b) æ ç«è¼é[ê an B çìëé.ê power train variations Fig.. Simulate response of VRM esign from Table II to a 00 A, 50 A/í s loaing an unloaing transient. averaging the feebak signal over eah effetive swithing perio ( h ã ), an thus proviing goo DC auray <ä of the feebak ontrol. The sample-an-hol an the resettable integrator introue some aitional elay in the feebak path, however this is not ritial to the overall spee of response sine fast loa hanges are hanle by the feeforwar path. As pointe out in Setion II-A, the feebak path only ompensates for imperfetions in the feeforwar ontrol, an ensures DC auray. o : III. SIMLATION RESLTS Fig. shows a simulation of the onverter esign in Table II. A ouple-inutor struture is use in orer to reue the inutor urrent ripple [9]. The feebak an feeforwar ontrol laws follow (7) an (9), respetively. The top plots show the output voltage response to a { A, î A/ï s loaing an unloaing transient, while the bottom plots give the ontroller output going to the PWM moulator. Part (a) orrespons ò to simulation with nominal power train parameters, ò while part (b) shows four waveforms orresponing to ðñî variation in the apaitor ESR, ombine with ð variation in the total inutane. Notie that ue to the inutane value seletion below the ritial inutane, the ontroller output oes not go negative, i.e., the uty ratio oes not saturate. Finally, eperimental prototype esign is unerway to orroborate the propose arhiteture funtionality. REFERENCES [] Intel Corp., Voltage regulator own (VRD) 0.0, [Online]. Available: April [2] R. Rel, B. P. Erisman, an Z. Zansky, Optimizing the loa transient response of the buk onverter, in Pro. IEEE Applie Power Eletron. Conf., 999, vol., pp [3] A. V. Peterhev, Jinwen Xiao, an S. R. Saners, Arhiteture an IC implementation of a igital VRM ontroller, IEEE Trans. on Power Eletron., vol. 8, no., pp , Jan [] J.-J. E. Slotine an W. Li, Applie Nonlinear Control, New Jersey: Prentie-Hall, 99. [5] R. Rel an N. O. Sokal, Near-optimum ynami regulation of DC DC onverters using fee-forwar of output urrent an input voltage with urrent-moe ontrol, IEEE Trans. on Power Eletron., vol. PE-, no. 3, pp. 8 92, July 986. [6] International Retifier Corp., IR308: XPHASEó{ô VR 0.0 ontrol IC, Data Sheet. [Online]. Available: April [7] A. V. Peterhev an S. R. Saners, Low onversion ratio VRM esign, in Pro. IEEE Power Eletron. Spe. Conf., [8] S. Banerjee an G. C. Verghese (Eitors), Nonlinear Phenomena in Power Eletronis: Attrators, Bifurations, Chaos, an Nonlinear Control, New York: IEEE Press, 200. [9] Jieli Li, C. R. Sullivan, an A. Shultz, Couple-inutor esign optimization for fast-response low-voltage DC DC onverters, in Pro. IEEE Applie Power Eletron. Conf., 2002, vol. 2, pp