A Carrier-Based Neutral Voltage Modulation Strategy for Eleven Level Cascaded Inverter under Unbalanced Dc Sources

Transcription

1 International Journal of Researh (IJR) e-issn: , p- ISSN: X Volume 2, Issue 12, Deember 2015 Available at A Carrier-Based Neutral Voltage Modulation Strategy for Eleven Level Casaded Inverter under Unbalaned D Soures Yarramsetti Veera Manikanta Swamy PG Sholar, Nova College Of Engineering And Tehnology Jangareddy Gudem, Department Of Eletrial And Eletronis Engineering, JNTUK Andhrapradesh, India Mr.A.SuryanarayanaBabu Nova College Of Engineering And Tehnology Jangareddy Gudem, Department Of Eletrial And Eletronis Engineering, JNTUK Andhrapradesh, India. Abstrat This paper proposes a pulsewidth-modulation strategy to ahieve balaned line-to-line output voltages and to maxi- mize the modulation index in the linear modulation range where the output voltage an be linearly adjusted in the multilevel asaded inverter (MLCI) operating under unbalaned d-link onditions. In these onditions, the linear modulation range is redued, and a signifiant output voltage imbalane may our as voltage referenes inrease. In order to analyze these effets, the voltage vetor spae for MLCI is evaluated in detail. From this analysis, the theory behind the output voltage imbalane is explained, and the maximum linear modulation range onsidering an unbalaned d-link ondition is evaluated. After that, a neutral voltage modulation strategy is proposed to ahieve output volt- age balaning as well as to extend the linear modulation range up to the maximum reahable point in theory. In the proposed method, too large of a d-link imbalane preludes the balaning of the output voltages. This limitation is also disussed. Both the simulations and the experiments for a Eleven-level phase-shifted modulated MLCI for eletri vehile tration motor drive show that the proposed method is able to balane line-toline output voltages as well as to maximize the linear modulation range under the unbalaned d-link onditions. Index Terms Harmoni injetion; multilevel asaded invert- ers (MLCIs); neutral voltage modulation (NVM); phase-shifted (PS) modulation; spae vetor pulsewidth modulation (PWM) (SVPWM) I. INTRODUCTION MULTILEVEL inverters enable the synthesis of a sinusoidal output voltage from several steps of voltages. For this reason, multilevel inverters have low dv/dt harateristis and generally have low harmonis in the output voltage and urrent. In addition, the swithing of very high voltages an be ahieved by staking multilevel inverter modules. Due to these advantages, multilevel inverters have been applied in various appliation fields. Among various topologies for multilevel inverters, the multilevel asaded inverter (MLCI) struture is one of the prominent topologies beause of its simple struture for modularization and faulttolerant apability. Therefore, MLCIs are used for many appliations, suh as dynami voltage restorer, stati synhronous ompensator (STATCOM), high-voltage energy storage devie, photovoltai inverters, medium-voltage drives, eletri vehile (EV) tration drives, and so on. In MLCI appliations, a modulation strategy to generate gating signals is very ruial to ahieve high-performane ontrol. Regarding this issue, many studies have been onduted, and they are roughly ategorized into multilevel seletive harmoni elimination pulse width modulation (PWM) (SHEPWM), multilevel arrier-based PWM, and multilevel spae vetor PWM (SVPWM) methods. Generally, a arrier-based PWM or SVPWM is preferred in appliations suh as motor drives, where dynami properties are very important, whereas SHEPWM is preferred in some high-power stati power onversion appliations. An SVPWM method Available online: P a g e 628

2 International Journal of Researh (IJR) e-issn: , p- ISSN: X Volume 2, Issue 12, Deember 2015 Available at has been studied to over the over modulation range in the multilevel inverter. To redue the ommon-mode voltage, a multilevel SVPWM has been proposed. The series SVPWM method has been reported to easily implement SVPWM for the MLCI. An SVPWM is proposed for hybrid inverters onsisting of neutral point lamp and H-bridge inverters to improve output voltage quality and effiieny. As with two-level inverters, it is also possible to implement arrier-based SVPWMs whih are equivalent to traditional SVPWMs by injeting a ommon offset voltage to the threephase referenes. Some methods to alulate the offset voltages to ahieve the optimal spae vetor swithing sequene are addressed. The performanes of a arrier-based PWM and an SVPWM are ompared, and a PWM sheme is proposed to obtain an optimal output voltage in the multilevel inverter. On the other hand, MLCIs require separated d links. Therefore, if there is one or more faults present in the d links in eah phase, or if the voltage magnitudes of the d links are unequal, the output voltage of the MLCI an be unbalaned without proper ompensation. To resolve this issue, some studies have been onduted. It is shown that the available modulation index is redued under faulty onditions on swith modules in multilevel inverters, and ompensation algorithms are proposed for phasedisposition PWM and phase-shifted (PS) PWM ases. For a STATCOM appliation, a zero sequene voltage to deouple a three-phase MLCI into three single-phase MLCIs is applied as well as zero average ative power tehniques to operate the MLCI under unbalaned soure or load onditions. Referene explains why the optimum angles and modulation indexes are neessary to obtain maximum balaned load voltages in the MLCI undergoing a fault on swithing modules. A neutral voltage shifting tehnique has been introdued for balaning the state of harge in the MLCI-based battery energy storage system. A duty yle modifiation method has been proposed to ompensate an output voltage imbalane aused by single-phase power flutuations. Referene has shown that a zero sequene omponent helps to obtain the maximum balaned output voltages in a fault ondition. An offset voltage injetion tehnique is studied to balane the output voltage of the MLCI, but the use of an integrator in the ompensation method may redue dynami harateristis in appliations suh as EV motor drives. Reently, the multilevel multiphase feed forward spae vetor modulation tehnique alled MFFSVM is proposed to ompensate the voltage imbalanes in MLCIs. In this paper, a arrier-based PWM strategy to balane line to line output voltages and to maximize the linear modulation range where the output voltage an be linearly ontrolled in the MLCI operating under unbalaned d-link onditions is proposed. In unbalaned d-link onditions, the maximum synthesizable voltage in eah phase is not uniform. Consequently, the linear modulation range is redued, and a signifiant output voltage imbalane may our as output voltage referenes inrease. In order to analyze the imbalane effet, the voltage vetor spae for the MLCI is evaluated in detail. From this analysis, the theory behind the output voltage imbalane is explained, and the maximum linear modulation range onsidering unbalaned d soures is evaluated. After that, a neutral voltage modulation (NVM) strategy is proposed to ahieve output voltage balaning as well as to extend the linear modulation range up to the maximum reahable point in theory. In the proposed method, the neutral voltage referene, whih onsiders a zero sequene voltage to ompensate the output voltage imbalane, and an offset voltage to extend the linear modulation range are easily obtained through simple arithmeti alulations. In the proposed method, too large of a d-link imbalane preludes the output voltages from being balaned. This limitation is also disussed. In addition, a faulttolerant operation is naturally overed, beause the MLCI undergoing an unbalaned d-link ondition an be onsidered as an MLCI operating under a faulty ondition on swith modules. Compared to the existing methods, the proposed strategy is very simple to implement, ompensates the output voltage imbalane in real time, and maximizes the voltage utilization of the Available online: P a g e 629

3 International Journal of Researh (IJR) e-issn: , p- ISSN: X Volume 2, Issue 12, Deember 2015 Available at d links. Therefore, if this sheme is applied to appliations suh as EV tration drive systems, the dynami harateristis an be greatly improved. This paper is organized as follows. In Setion II, the voltage vetor spae for the oneby-three onfiguration MLCI is analyzed for a oneptual study. The proposed modulation strategy is addressed in Setion III. In Setions IV and V, the simulations and the experimental results on the two-by-three MLCI are presented. Setion VI onludes this paper. B. Voltage Vetor Spae Analysis When the d-link voltage of a single H- bridge module is Vd, the output voltage vpn has three states, i.e., Vd, 0, and Vd, MODELLING OF CASE STUDY II. SYSTEM CONFIGURATION AND VOLTAGE VECTORSPACE ANALYSIS A. Configuration of MLCI for EV Tration Motor Drive Fig. 1 shows the EV tration motor drive system that is dealt with in this paper. In this onfiguration, various power ratings an be easily implemented by onfiguring the number of the single H-bridge modules aording to a required speifiation suh as a neighborhood EV, full-size sedan, and so on. Here, eah H- bridge module inorporates voltage and urrent sensing iruitries, gate drivers, and ommuniation interfaes between the module itself and the main ontroller. In addition, battery ells an be also inluded in the H-bridge module. The unipolar modulation tehnique is applied between two swithing legs in the H- bridge module. Consequently, the effetive swithing frequeny in eah H-bridge module is twie the arrier frequeny. In addition to this, the well-known PS modulation tehnique is used to implement interleaving and multilevel operation. Therefore, the effetive swithing frequeny fsw in a phase is fsw = 2N f (1) Where N and f represent the number of the H-bridge modules in eah phase and the arrier frequeny of PWM, respetively. As an example, Fig. 2 shows the arriers for eah module, the duty yles in unipolar modulation, and the output voltage when N = 2. Fig. 2. Unipolar and phase shift modulation for single H-bridge module. Fig. 3. Output voltage of a single H-bridge module. Fig. 4. One-by-three onfiguration MLCI. As shown in Fig. 3. By adopting the onept of a swithing funtion, it an be represented as (2) Where Sp is a swithing funtion and p an be replaed with a, b, or, whih represent the phases. Fig. 4 shows a simple one-by-three onfiguration MLCI. For voltage vetor spae analysis, the main onept is derived from this simple topology, and then, it is expanded to more Available online: P a g e 630

4 International Journal of Researh (IJR) e-issn: , p- ISSN: X Volume 2, Issue 12, Deember 2015 Available at levels. In Fig. 4, there are two neutral points s and n in the MLCI. Here, the voltage between the output point of eah phase and the neutral point n is defined as the pole voltage. The pole voltages are represented as van, vbn, and vn. The voltage between the output point of eah phase and the load side neutral point s is speified as the phase voltage. The phase voltages inlude vas, vbs, and vs. By using this onept, the voltage between the two neutral points is defined as vsn and an be written as (b) Fig. 5. Voltage vetor spae of one-by-three onfiguration MLCI. By substituting (4) into (3), the phase voltage of eah phase is represented as follows by using the relationship defined in (2): (3) By using the ondition that the sum of all phase voltages is zero beause the load does not have a neutral line, vsn is rewritten as (5) (a) (4) If the magnitudes of three d links are balaned so that Vd_a, Vd_b, and Vd_ have the same value Vd, the voltage vetor spae in α β oordinates is defined in Fig. 5(a) by using (5). In the figure, underbars indiate that the swithing funtion has the value of 1. A part of the hexagon in Fig. 5(a) is shown in Fig. 5(b). In this figure, the vetors v010 and v111 are plaed at the same referene axis, phase b. However, the onstituents of those vetors are different. For v010, this vetor an be synthesized without the other two phases assistane. However, v111 annot be produed without other vetors aording to (5). From this, let the vetors whih do not require other two phases assistane to be defined as the independent vetors. Similarly, the vetors whih require other phases support are defined as the dependent vetors. Aording to these definitions, v100, v001, and v010 are the independent vetors, while v111, v111, and v111 are the dependent vetors in Fig. 5(b). Fig. 5(a) also ompares the regions that an be omposed by the independent Available online: P a g e 631

5 International Journal of Researh (IJR) e-issn: , p- ISSN: X Volume 2, Issue 12, Deember 2015 Available at Fig. 6. Voltage vetor spae in an unbalaned dlink ondition. vetors are no longer multiples of 60. Using these properties, the voltage vetor spaes in two different ases are ompared in Fig. 7. In Fig. 7(a), Vd_a has a lower value than the others. In Fig. 7(b), all three d links have different voltages. As it an be seen in Fig. 7, the original shape of the hexagon is distorted in both ases. This means that the trajetory of the maximum output voltage vetor in the α β oordinates is also distorted aording to the shape of the hexagon in eah. On the other hand, the magnitude of the maximum modulation index in the linear modulation range in a given hexagon orresponds to the radius of the inner irle whih is insribed in the hexagon. As shown in Fig. 7, the radius is hanged as the hexagon distorts, and the ahievable linear modulation range is also altered. Here, the maximum amplitude of the phase voltage Vph_max in the linear modulation range is defined as Fig. 7. Comparison of the voltage vetor spae under different d-link ratios. (a) Vd_a < Vd_b = Vd_. (b) Vd_b < Vd_a < Vd_. and the dependent vetors. Unlike traditional three-phase half bridge inverters, the independent vetors an be fully applied in a swithing period beause the d links in eah of the three phases are separated in the given system. It should be noted that the maximum voltage is deided by the dependent vetors in the entire voltage vetor spae. Now, let us onsider the ase when a three-phase load is supplied by unequal d links. Fig. 6 shows an extremely unbalaned ase where Vd_a is half of the others. If Vd_a dereases, the magnitudes of the independent vetors in phase a are also redued. As a result, the magnitude of v100 is dereased. Here, the phase angle of v111, whih is the sum of v010, v100, and v001, is no longer mathed with the angle of the independent vetors in phase b from the figure. As shown in the figure, if the magnitudes of the independent vetors are redued, the available voltage vetor spae is also redued, and the angles of the dependent (6) Where Vd_max, Vd_mid, and Vd_min represent the maximum, medium, and minimum voltages among the d links. In fat, (6) an be simplified as (7) It should be noted that Vph_max is the maximum synthesizable voltage in the linear modulation range in the MLCI undergoing unbalaned d-link onditions. From (7), it an be reognized that Vph_max is determined by Vd_mid and Vd_min. If all d links are well balaned so that Vd_mid and Vd_min have idential values, (7) is rewritten as Available online: P a g e 632

6 International Journal of Researh (IJR) e-issn: , p- ISSN: X Volume 2, Issue 12, Deember 2015 Available at (8) This is exatly double the maximum synthesizable voltage in the linear modulation range of a traditional three-phase half bridge inverter. In fat, the inverter in Fig. 4 is onsidered as a three-phase full-bridge inverter whih is fed by independent d links. To extend the proposed approah to the multistage MLCI using PS modulation, the total d-link voltage per phase is represented as (9) where p represents a ertain phase among phases a, b, and, N is the number of the power stage modules in eah phase, and j represents the index of a power stage module in eah phase. In the multistage MLCI, (9) is utilized to obtain Vd_max, Vd_mid, and Vd_min. After that, (7) is still applied. III. PROPOSED MODULATION TECHNIQUE In Setion II, the maximum synthesizable voltage in the linear modulation range was evaluated under the unbalaned d links. In this setion, a method is proposed to realize the maximum modulation index in the linear modulation range under these onditions. A. Traditional Offset Voltage Injetion Method: The offset voltage injetion sheme is a popular tehnique in three-phase half-bridge inverter appliations. The theory behind this is that an offset voltage is inorporated with phase voltage Fig. 8. Implementation of the NVM method. referenes to implement various PWM shemes in arrier-based PWM by using the fat that lineto-line voltages are applied to a three-phase load [43], [44]. For example, the offset voltage v* sn is injeted to the phase voltage referenes v*as, v*bs, and v*s to implement arrier-based SVPWM as in (10) Then, the pole voltage referenes v* an, v*bn, and v*n, whih will be onverted to PWM duty referenes, are (11) However, the aforementioned tehnique may not maximize the linear modulation range in MLCI undergoing unbalaned d-link onditions. B. Proposed NVM Method If the d links in an MLCI are unbalaned and the traditional offset voltage injetion methods are utilized, the three-phase output voltages may beome distorted as the phase voltage referene approahes Vph_max. This is beause the traditional methods are not onsidering unbalaned d-link onditions. Therefore, even if a phase an synthesize an Available online: P a g e 633

7 International Journal of Researh (IJR) e-issn: , p- ISSN: X Volume 2, Issue 12, Deember 2015 Available at output voltage referene in the linear modulation range, the other phases an be saturated or go into the ove rmodulation region. In this situation, a neutral voltage an be produed by the saturated or overmodulated phase. In order to resolve this issue and to synthesize the output voltage to Vph_max in the linear modulation range, the NVM tehnique is proposed in this paper. Fig. 8 shows the onept of the proposed NVM tehnique. Here, a neutral voltage between the two neutral points n and s in Fig. 4 is modulated to ompensate the output voltage imbalane aused by unbalaned d-link onditions. To do this, first, the weight onstant Kw is defined as (12) By using (12), the weight fators are alulated as From (15), the line-to-line voltages aross eah phase of the load are represented as (16) As it an be seen in (16), v_ sn does not appear in the line-toline voltages, and it is still onsidered as a hidden freedom of voltage modulation. Now, let us onsider the role of the weight fators Kw_a, Kw_b, and Kw_, whih are inversely proportional to the orresponding d-link voltage. For onveniene, let us assume that the magnitudes of the d-link voltage are under the following relationship: (13) where Kw_a, Kw_b, and Kw_ represent the weight fators for phases a, b, and, respetively. Next, the weight fators are multiplied by the phase voltage referenes, and the new referenes v_ as, v_ bs, and v_ s are obtained as Then, from (13) and (17) Equation (18) gives (18) (17) (14) It should be noted that, depending on dlink onditions, the sum of v_ as, v_ bs, and v_ s may not be zero. By using these omponents, the injeted voltage v_ sn and the pole voltage referenes are given as (15) (19) From (15) and (19), it an be reognized that, if v as, whose d-link voltage is less than the others, is orresponding to v max or v min, the absolute value of v sn is greater than v*sn in (10). On the other hand, the final pole voltage referenes v*an, v*bn, and v*n are alulated by subtrating v sn from the original phase voltage referenes v*as, v*bs, and v*s as in (15). From this reasoning, in this example, it is supposed that, if v as is orresponding to v max, then the final pole voltage referenes v*an, v*bn, and Available online: P a g e 634

8 International Journal of Researh (IJR) e-issn: , p- ISSN: X Volume 2, Issue 12, Deember 2015 Available at v*n are less than the original pole voltage referenes Equation (21) shows that the proposed method gives the same voltage referenes as the traditional method under balaned d-link onditions. C. Constraints of the Proposed Method Fig. 9. Comparison of modulated waveforms. (I) Without v*sn. (II) Traditional arrier-based SVPWM. (III) Proposed NVM with Vd_a = Vd, Vd_b = Vd, and Vd_ = Vd. (IV) Proposed NVM with Vd_a = 0.2 Vd, Vd_b = Vd, and Vd_ = Vd. whih are not onsidering v sn but v*sn. On the ontrary, if v s is v max, then the final pole voltage referenes are greater than the original pole voltage referenes. By using this priniple, the proposed method redues the portion of the phase whose d-link voltage is smaller than the others and inreases the utilization of the phase in whih the d-link voltage is greater than those of the other phases. However, as it an be seen in(16), v sn does not affet the line-to-line voltages. Therefore, the line-to-line voltage is the same as the one derived from the original phase voltage referene. From this analysis, the proposed method enables the maximum synthesizable modulation index in the linear modulation range under the unbalaned d-link onditions to be ahieved. In addition to this, if all of the d-link voltages are well balaned so that Vd_a, Vd_b, and Vd_ are equal to Vd. In this setion, the limitation of how unbalaned d links an be while still being ompensated by the proposed method is evaluated. Fig. 9 shows the modulated voltage waveforms with different modulation methods and d-link onditions. In the figure, ases I and II show the results of traditional sinusoidal PWM (SPWM) and arrier-based SVPWM, while ases III and IV illustrate the waveforms of the proposed method with different ratios of d-link voltages. The fundamental idea to examine the limitation of the proposed method is to evaluate what onditions bring the different polarities between the original voltage referene and the modified voltage referene by using the proposed method. In Fig. 9, the verties at π/2 and 3π/2 rad almost ome in ontat with, but do not ross, the zero point. However, the diretions of the verties are opposite the original phase voltage referene in ase IV. This means that an exessive and unneessary voltage is injeted into the system. As a result, (20) By substituting (20) into (12) (14) Fig. 10. Comparison of the duty referenes and the arriers (21) Available online: P a g e 635

9 International Journal of Researh (IJR) e-issn: , p- ISSN: X Volume 2, Issue 12, Deember 2015 Available at (24) Fig. 11. Comparison of the voltage vetor trajetories. The maximum linear modulation range is redued, and the line to line voltage may be distorted. With this basi onept, it is assumed that a phase whih has the lowest d-link voltage ommands v*max and a phase whih has the highest d-link voltage ommands v*min to examine a worst ase situation. From (14) and (15), the following equations an be established: Fig. 12. Seven Level Outputs,Simulation result of traditional SPWM, traditional SVPWM, and the proposed method. (22) By using (22), the pole voltage referene whih is onsidered as the worst ase is (23) By substituting (22) into (23), we have Fig. 13. Eleven Level Outputs,Simulation result of traditional SPWM, traditional SVPWM, and the proposed method. Unless all three-phase voltage referenes are not zero simultaneously, near a positive peak of the original voltage referene, the suffiient ondition whih guarantees the same polarity between v* max and v*min is established as follows: Available online: P a g e 636

10 International Journal of Researh (IJR) e-issn: , p- ISSN: X Volume 2, Issue 12, Deember 2015 Available at (25) By substituting (24) into the first ondition in (25), the following ondition an be written: (26) Here, it is obvious that k2 is always positive. Therefore, as long as k1 is positive, the ondition (26) is always satisfied, and k1 an be rearranged as follows: (31) If the relationship between k1 and k2 is established as in (31), even if the provision in (28) is broken, the onditions in (25) are satisfied so that the proposed method an be still effetive. Let us reall Fig. 9 again here. In the figure, the values of k1 and k2/2 for ase III are evaluated as and , respetively. Although the differene between the two values is very small, (31) is still true with these values. For ase IV, D. Duty Calulation In Fig. 8, the final voltage referenes are entered to the duty referene alulation blok. In this blok, the duty referenes of eah H- bridge module are alulated as follows: (27) Equation (28) is then diretly obtained from (27) to ensure that k1 will always be positive (28) Note that (28) is a suffiient ondition to meet the onditions in (25) so that the proposed method an be applied. However, even if (28) is not satisfied so that k1 is negative, there still is a hane to apply the proposed method. To deal with this situation, let us onsider the relationship between v*max and v* min as follows at a positive peak point: By substituting (29) into (26), we have (30) (29) Sine k1 is negative in this ase, the following ondition is derived from (30); (32) The alulated duty referenes are ompared to PS arriers to generate gating signals, as shown in Fig. 10. It should be noted that the duty referenes for eah H-bridge in eah phase are shared in the PS modulation. V. CONCLUSION The NVM tehnique for MLCIs under unbalaned d-link onditions has been proposed in this paper. In order to analyze the maximum synthesizable voltage of MLCIs, the voltage vetor spae has been analyzed using the swithing funtion. From the analysis, the maximum linear modulation range was derived. The proposed NVM tehnique is applied to ahieve the maximum modulation index in the linear modulation range under an unbalaned dlink ondition as well as to balane the output phase voltages. Compared to the previous methods, the proposed tehnique is easily Available online: P a g e 637

11 International Journal of Researh (IJR) e-issn: , p- ISSN: X Volume 2, Issue 12, Deember 2015 Available at implemented and improves the output voltage quality under unbalaned d-link onditions. Both simulations and experimental results based on the IPM motor drive appliation verify the effetiveness of the proposed method. VI. REFERENCES [1] J. Rodriguez, J.-S. Lai, and F. Z. Peng, Multilevel inverters: A survey of topologies, ontrols, and appliations, IEEE Trans. Ind. Eletron., vol. 49, no. 4, pp , Aug [2] H. Abu-Rub, J. Holtz, J. Rodriguez, and G. Baoming, Medium-voltage multilevel onverters State of the art, hallenges, and requirements in industrial appliations, IEEE Trans. Ind. Eletron., vol. 57, no. 8, pp , Aug CHO et al.: CARRIER- BASED NVM STRATEGY FOR MLCIs UNDER UNBALANCED DC SOURCES 635 [3] J.-S. Lai and F. Z. Peng, Multilevel onverters A new breed ofpower onverters, IEEE Trans. Ind. Appl., vol. 32, no. 3, pp , May/Jun [4] M. Malinowski, K. Gopakumar, J. Rodriguez, and M. A. Perez, A surveyon asaded multilevel inverters, IEEE Trans. Ind. Eletron., vol. 57, no. 7, pp , Jul [5] J. Rodriguez, L. G. Franquelo, S. Kouro, J. I. León, R. C. Portillo, M. A. M. Prats, and M. A. Perez, Multilevel onverters: An enabling tehnology for high-power appliations, Pro. IEEE, vol. 97, no. 11, pp , Nov [6] G. Bergna, E. Berne, P. Egrot, P. Lefran, A. Arzande, J.-C. Vannier, and M. Molinas, An energy-based ontroller for HVDC modular multilevel onverter in deoupled double synhronous referene frame for voltage osillation redution, IEEE Trans. Ind. Eletron., vol. 60, no. 6,pp , Jun [7] Z. Shu, N. Ding, J. Chen, H. Zhu, and X. He, Multilevel SVPWM with DC-link apaitor voltage balaning ontrol for diode-lamped multilevel onverter based STATCOM, IEEE Trans. Ind. Eletron., vol. 60, no. 5, pp , May [8] J. Chavarria, D. Biel, F. Guinjoan, C. Meza, and J. J. Negroni, Energybalane ontrol of PV asaded multilevel grid-onneted inverters under level-shifted and phase-shifted PWMs, IEEE Trans. Ind. Eletron., vol. 60, no. 1, pp , Jan [9] G. Butihi, E. Lorenzani, and G. Franeshini, A five-level single-phase gridonneted onverter for renewable distributed systems, IEEE Trans. Ind. Eletron., vol. 60, no. 3, pp , Mar [10] J. A. Munoz, J. R R. Espinoza, C. R. Baier, L. L. Morán, E. E. Espinosa, P. E. Melín, and D. G. Sbárbaro, Design of a disrete-time linear ontrol strategy for a multiell UPQC, IEEE Trans. Ind. Eletron., vol. 59,no. 10, pp , Ot [11] J. Napoles, J. I. Leon, R. Portillo, L. G. Franquelo, and M. A. Aguirre, Seletive harmoni mitigation tehnique for high-power onverters, IEEE Trans. Ind. Eletron., vol. 57, no. 7, pp , Jul [12] L. G. Franquelo, J. Napoles, R. C. Portillo Guisado, J. I. Leon, and M. A. Aguirre, A flexible seletive harmoni mitigation tehnique tomeet grid odes in three-level PWM onverters, IEEE Trans. Ind. Eletron., vol. 54, no. 6, pp , De [13] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, and B. Wu, Reent advanes and industrial appliations of multilevel onverters, IEEE Trans. Ind. Eletron., vol. 57, no. 8, pp , Aug [14] A. M. Massoud, S. Ahmed, P. N. Enjeti, and B. W. Williams, Evaluation of a multilevel asaded-type dynami voltage restorer Available online: P a g e 638

12 International Journal of Researh (IJR) e-issn: , p- ISSN: X Volume 2, Issue 12, Deember 2015 Available at employing disontinuous spae vetor modulation, IEEE Trans. Ind. Eletron., vol. 57,no. 7, pp , Jul [15] M. Hagiwara, K. Nishimura, and H. Akagi, A medium-voltage motor drive with a modular multilevel PWM inverter, IEEE Trans. Power Eletron., vol. 25, no. 7, pp , Jul [16] J. Rodriguez, S. Bernet, B. Wu, J. O. Pontt, and S. Kouro, Multilevel voltage-soureonverter topologies for industrial mediumvoltage drives, IEEE Trans. Ind. Eletron., vol. 54, no. 6, pp , De Available online: P a g e 639