LECTURE 6 ASSOCIATED OUTPUT AND INPUT FILTER AC WAVEFORMS CAUSED BY SWITCHING

Transcription

1 1 LETURE 6 ASSOIATED OUTPUT AND INPUT FILTER A WAVEFORMS AUSED BY SWITHING I. SELETING INDUTOR AND APAITOR VALUES TO MEET RIPPLE SPEIFIATIONS FOR A GIVEN DUTY YLE - L(D) & (D) L a. L(D) FOR SPEIFIED i L,GIVEN V L DURING DT S V L(duringDT s) = DTs = L(D) 2 il V out DTs =, V V 2R R b. (D) FOR SPEIFIED V c, GIVEN V out DURING DT S out = Iout during Ts =f(d) II. DOUBLE POLE LOW PASS FILTERS A. OUTPUT L- FILTER f(d), 1/f s B. INPUT EMI FILTER, L f(d), L 1/f s STEADY STATE VOLTAGES 1, 2 - HARGE BALANE GIVES STEADY STATE VOLTAGES D. RIPPLE ON INPUT FILTER a. 1 FOR V 1 SPE b. L 1 FOR I L1 SPE

2 2 OUTPUT AND INPUT A WAVEFORMS AUSED BY SWITHING I. SELETING L(D) AND (D) IN D FILTERS FOR PWM ONVERTERS A.SELETING REQUIRED L(D) IN AN L-R FILTER On output filters for D POWER will outline two separate methods to achieve SPEIFIED i L LIMITS AND REQUIRED L VALUES AS WELL AS SPEIFIED v LIMITS AND REQUIRED VALUES. learly i L in a PWM circuit will ramp up and down around its D level. Lets specify i L limits and find how to select L values to achieve this. DEFINING: The inductor current is I L (D) + i L (RIPPLE) and having ripple about I D (steady-state) s.s D level DT s T s D'T s i L i L We find for both the buck and the boost: i V 2L Given in a practical case i L = 10% of i dc (steady-state) and the v dc - v o difference as known L(FOR DESIRED Di L ) = (V D - V o )DT S /2DI l IS A LINEAR FUNTION OF D. This is a minimum value of L. Note that L will increase when smaller ripple is required. USEFUL RELATION TO SELET L(D) :NOTE THAT L = f(d) L = D V o DT s EXAMPLE: For either a buck or a boost: with: f SW = 100 khz = 10 5, T S =10 µsec

3 3 V D - V o IS THE VALUE AROSS L DURING D the on time of the power switch. Usually D does not exceed 0.9, and its value IF V D - V o = 50V, I L = 10A & i L = 10%I L (D) = 1A L = L(f sw, D, IRUIT) L 50 5 = D10 = 250µ H*D (2)(1) The proper L value to meet the required ripple spec. is set in either the buck or the boost by required duty cycle, d. L(max) = 250µ H for D=1. D WILL BE SET BY: V o / V D = f(d) AND f(d) IS UNIQUE TO EAH ONVERTER TOPOLOGY AS SHOWN BEFORE. In short, the required l will vary with d, and d will vary with converter type for specified v out and v in. OTHER L ISSUES: L f(i L ) only valid when i dc + i ac is limited to below core saturation, i sat. THE I D LEVEL MUST BE FAR BELOW I SAT OR i L SWINGS WILL SATURATE THE ORE. B Icritical I B sat SATURATE ORE NOTE: SATURATION OURS IF i > i(critical) BE AREFUL! i > i(critical) implies H or I > H(critical) or I(critical) and µ r changes to µ o suddenly. ore saturation occurs for big current amplitudes if we are not careful. THIS AUSES L TO DROP IN VALUE BY 100 OR MORE.

4 4 µ o B H µ µ o r B sat N L µ r µ o 2 R FOR LARGE µ r (core) L WILL BE LARGE If b in inductor core exceeds B sat the L value will decrease by at B > B sat. This means L(i) variation occurs in a threshold fashion, not gradually. Finally, for steady-state to occur over the full cycle of the switch waveform t s THE NET Ts vldt 0. THIS MUST OUR, OTHERWISE THE 0 INDUTOR URRENT WILL GROW EAH YLE AND EVENTUALLY REAH SATURATION AND i > i(critical). V L V+ V- D D' For an inductor in steadystate and well below core saturation, the total integral area v L dt over T s is ZERO. GIVEN THAT IN STEADY-STATE THE INDUTOR MUST HAVE VOLT-SE BALANE OVER T s : i L s u s d I D DT s D'T s

5 5 In many cases the di/dt upward slope (s u ) downward slope (s d ) in a/sec units. this means that we must choose d and d so that the integral is indeed zero. That is volt-second balance sets d values to their proper values in steady state. di/dt SLOPE IN THE INDUTOR IS SET BY: upward V L /L during dt s. v L is the voltage across L during internal dt s. Downward V L /L during d t s. V L is the voltage across L during interval d t s which is the switch off time... V L differs during dt s and d t s because the converter circuit topology differs for dt s (switch on) and d t s (switch off) as we will show in more detail below. B. SELETING (D) IN A D FILTER Likewise for capacitors we have capacitor charge balance. in steady state for any capacitor, V c is fixed after the switching period t s and not growing or decreasing in steady state.. V c has a dc baseline and an A ripple. v s u s d 2 v DT s D'T s Downward slope is set by I during DT s when the switch is on and the circuit is the on case topology. Upward slope is set by I during D T s when the switch is off and the circuit is in the off case topology.

6 6 If s u s d then D D for steady-state conditions to occur. EXAMPLE: We did the single pole L-R filter now for a R- filter we assume v o = v dc was set by the converter f(d) and v in v o = f(d)v in so that d is known. ONSIDER FIRST A SINGLE POLE R- LOW PASS FILTER driven by a current source. this could very well be the current from an inductor as we will show later. I sw DT s D'T s I sw Switched current from source R Output filter V dc and in steady-state I o V R FOR A SPEIFIED v RIPPLE GOAL, THE VALUE OF DEPENDS ON f sw, D, V D, R dc First consider an interruption of current with no source current for dt s : i out = v dc / R is drained from initially charged to v o = v dc. s d voltage discharge slope (V dc /R)(1/) in V/sec units With source current switched back on for d t s we recharge the capacitor above:

7 7 Iswitch VD 1 R assume net positive current to recharge BAK TO V o = V D active load still current drains drive current s u slope (I sw -V dc /R)(1/) in units of V/sec then the change in V c is such that: v V dc 2 v v V DT D s R 2 DT s D'T s GIVEN V THIS SETS VALUE IS A LINEAR D V DT FUNTION: D s = (D) v 2R EXAMPLE: V D = 20 V, f s = 100 KHz V OF 10% = 2 V, R = 4 Ω 20 = D10 s µ = 2 (2)(4) 200 µ 16 F *D NOTE IS A LINEAR FUNTION OF ON-TIME DUTY YLE D

8 8 Required value of (D) for specified 10% ripple on v dc depends on D (duty cycle) For a given v dc output and v in as well as converter type, D is set by the f(d) for a given converter type. v dc /v g = f(d) yields D to achieve that specific steady state. each converter topology has a unique f(d). Ts again vldt = 0. if not, v c will increase until the dielectric 0 breakdown of the capacitor is reached.. DOUBLE POLE L- LOW PASS FILTERS Here we are solving the case of a series L in-between input and output and parallel across the load At the output, you can calculate similiar current and voltage ripple waveforms for both a series L and a shunt. Again we assume working converters set d and d values and are only concerned with the output ripple specifications i(ac) and v(ac) and how they effect the choice of L and in output filters. L is in series and is in parallel. THIS IS A UNIQUE SITUATION WHERE SMALL RIPPLE APPROXIMATION MUST BE USED TO GET ORRET V vs. t. WE ARE ABLE TO USE THIS SIMPLE APPROXIMATION IF WE DO IT AREFULLY. 1. First recognize that capacitor voltage ripple is affected by the i L ripple in the series charging inductor: I L = I L (dc) + i L Di L was usually considered zero before for single pole filters. Now however, i L is not considered zero. WE SHOW FOR THE ASE BELOW i L EFFETS v AND ANNOT BE NEGLETED.

9 9 V sw = V g R In fact in steady state at the output we can say to a good approximation: I L (D) FLOWS ONLY INTO R AS DOESN T ALLOW I D Di L (ac) AT f sw FLOWS MOSTLY INTO AND NOT R IF Z (f sw ) << R. THEN WE AN SIMPLIFY FILTER ANALYSIS SO THAT i L FLOWS ONLY INTO. This is often the case in practice. Di L Di ALL L RIPPLE Di FLOWS INTO So the time analysis sequence of voltage across the series inductor is: 1. v sw = v g comes on as a step: constant voltage is applied during dt s to the left side of L. The right side of L is considered fixed at v out. V L = v out (sw)-v out (dc) or v L = v g -v o 2. i L appears as a linear ramp during dt s v il = L dt or i ~ at L 3. This current flows mostly into causing v c to change given i c = at is a linear function of time (ramp) then v c ~ at 2 during dt s i v = dt WE WILL AVOID THIS OMPLEX ANALYSIS AS FOLLOWS. onsider the v L waveform as a unisymmetric square wave. then from v L being a square wave i L will be a ramp - i L is a linear function of time( at). The area under the i-t ramp is the charge to be dumped on the capacitor.

10 10 i L = i i = i L We will find that the VALUE TO MEET REQUIRED RIPPLE DEPENDS ONLY ON f sw AND NOT ON D. V Assuming v o varies little, this g D is the voltage waveform t across the inductor v L for: D' v sw (on) (DT s circuit): V L =V g -V o V sw (off) v unspecified sw (off) (D T s circuit): V L unspecified This voltage variation across V L causes a i L flowing i through L about I D L Shaded area under the i L i L vs t curve shown is positive Q during T s /2. This will cause a v. interval T s /2 by symmetry THE NET HARGE Q(DURING T s /2) = ½*BASE(T s /2)*HEIGHT( i L ). This charge change causes 2 v c to vary across the capacitor in the double pole L- filter. 2 V Q = = 1 2 Ts 2 i L V (Ripple on double pole series L / parallel output filter) = GIVEN i L AND v AS SPEIFIED BY THE DESIGN OF THE OUTPUT SPE S WE AN WRITE A SIMPLE EXPRESSION FOR, i T L s = f (f s) is the relation to determine v 8 GIVEN THE REQUIRED i L AND v c RIPPLE VALUES. i T 8 L s

11 11 NOTE THAT UNLIKE THE PRIOR SIMPLE L-R AN R- FILTERS IN L- DOUBLE POLE FILTERS f(d), ONLY f s, i L AND v 2. INDUTOR AFFETED BY DV c Previously we had a series L and parallel between the switched converter pulsed output and the load. A filter could also be placed between the input to the converter and the mains to reduce emi from entering the ac mains from the switching waveforms at the inverter input. There are now laws concerning emi allowed on mains. a. EMI and EM ISSUES In Europe the EU regulation of allowable harmonic pollution of the ac mains is strictly enforced for all switch

12 12 mode power supplies. See later lectures for more details. Never the less, a simple parallel - series L input filter can do wonders for reducing signals at f(switch) from entering the mains. On the next page we will illustrate both conducted and radiated emissions. Both arise from the switches operating at high frequency and carrying large switch powers. THIS IS THE DIRTY SERET DISADVANTAGE of the PWM APPROAH

13 To bring this all to a head we place on the next page some data from the noise generated by a PWM Flyback converter. The noise spectrum is shown as a FFT. Finally, the total EMI signal is compared to that allowed by the law. We repeat that electrical engineers that do not design to regulatory specs are IN VIOLATIOL OF THE LAW. 13

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15 15 i T V g (in) Switch Mode Network V out Input filter to keep switching harmonics from entering the mains: EMI noise issue is now a legal one. Incidentally, some switching signals have very sharp transients that can be better reduced by an R snubber circuit in addition to the EMI filter as shown: Vin Switch Mode Network V out A simplified equivalent circuit model is given below: A Mains L Rout Switch onverter Previously, we saw that for an equal duration square wave (d = d ) the fundamental ac component of the signal has an amplitude 2v dc /π. We will consider the attenuation of the filter in two ways on the next page: A rough transfer function approach An intuitive ripple estimate approach

16 16 1 jw R Where V in = 2 π V Dsinwt 1 + jw R (for D = 0.5) Vout = Vin 1 jwl + jw R 1 + jw R Assume a 40db per decade rolloff due to the L-. If we specify the need for 24db of attenuation at the switch frequency, then the corner frequency of the filter will be at: F =f sw x 10 (24/40) =25KHz For a 50 Ohm input line impedance and a filter damping factor of.707 the required Land are given by: L= 50x0.707/πx25KHz =450 µh = 1/ (2πf ) 2 L =0.9 µf Real commercially available capacitors do not exceed.o5m so, we need to reduce by 2 and increase L by 2. THIS IS ONE WAY. WE ALSO GET A ROUGH IDEA AS FOLLOWS: Raw D onsider V g (fixed) L 1 1 v 1 variation occurs here due to switch network EMI generation f s v c1 variation at the inverter input causes i L1 to flow back to the mains. We have a spec. on the maximum i L1 from the government. onsider v g for now as fixed instead of a rectified sinusoid. V L = v g (fixed) - v c1 = v c. Now any change in v c will cause a change in i L. vcdt 2 il1= L 1

17 17 THE TIME PERIOD dt IS T s /2 AGAIN BY SYMMETRY, AND 1 VOLT-sec AREA UNDER vdt 2 v T s c 2 v T i L1(Ripple current due to v) = s. IF WE 8L1 SPEIFY BOTH v c (known or measured) AND i L, WE AN WRITE THE L VALUE EQUATIONS AS: value to reduce il1 L ( to gov. specification ) v Ts 1 il1 8 given v c FOR THE DOUBLE POLE FILTER INLUDING RIPPLE: L 1 f(d), L 1 1/f s Finally, For HW#1: 1. Answer Questions asked throughout lectures hapter 2 of ERIKSON Problems 2, 3, 4 and 6.