I. Erickson Problem 6.4 A DCM Two Transistor Flyback Converter

Transcription

1 Lecture 15 The Forward PWM Converter Circuit Topology and Illustrative Examples 1 I Erickson Problem 64 A DCM Two Transistor Flyback Converter II Forward Converter A Overview B Forward Converter with a Three Winding Transformer Drive: Two Case Studies 1 One Transistor Implementation 2 Two Transistor Implementation C Forward Converter Transformer D External Reset of a Transformer: Erickson Problem 69

2 Forward PWM Converter Circuit Topologies 2 I Erickson Problem 64 A DCM Two Transistor Flyback Converter b) Erickson Problem 610: One transistor Flyback implementation in the DCM mode of operation We will consider only DCM operation below: 165 Vdc n p :n1 i p i 1 :n 2 15V 1A Q 1 i 2 15V 05A :n 3 i 3 5V 4A Note the ability to provide ±15 V as well as 5 easily If we employed feedback for V o stabilization we could use just one of the three V o to monitor and slave the other two WHAT OTHER WAY IS POSSIBLE?? Neglect: 1 All losses in the electronic circuits 2 No magnetic core losses Also for this problem we arbitrarily set the specification is fixed

3 and i load is fixed for the DCM operation 3 We expect given 3 DCM time intervals: D 1, D 2, D 3 but we arbitrarily fix D 3 = 01 D 2 = 09 D 1 Goal: Find steady state design, where the V(off) blocking voltages are minimum for both the transistors (< 300 V) and diode (< 30 V) solid state switches Below we give circuit conditions for each time interval Interval D 1 T s : Control signal puts Q 1 on and using current flow dot s on the transformer we see that all three diodes in the secondary are off i g n :n p s i L m v p C R V o V Lm = i c i R = 0 i = i o g i c = V R Interval D 2 T s : Control signal puts Q 1 off, all secondary diodes conduct using current flow dots on the transformer i g v Lm i L m v p V(off Tr) 1:n i/n C R V o ns/np

4 i g = 0 o i c = i n V R 4 o V L = V n = V(primary) Period D 3 T s : Q 1 off, all secondary diodes off V(off diode) 1:n v(off diode) v Lm L m v p V(off Tr) C R V Lm = 0 i r i c = 0 i g = 0 o i c = V R V o Draw i c waveform versus time using the above circuits to determine values of i c for each interval ic Vg D1 D2 01 t Vo/n=V(primary) Remember V o n = V(primary) for all ac conditions encountered Applying voltsec balance to the L m inductor: < V > = 0 D V D ( ) 0 = 0 Lm Ts 1 g 2 V p

5 D1 = (09 D 1) Vp D 1( V p) = 9 Vp 9 Vp D 1, setting an upper bound on D 1 V V g p 5 For cost considerations we limit maximum voltages to the switches as follows: Choose: Transistor: V off < 300 V Diode: V off < 30 V 300 V p from primary circuit and transistor maximum standoff voltage spec V p = 300 (165) = (135) D 1 < = Pick D 1 = 04 D 2 = 05 Try this 1st choice and see the effect Diode currents for all three secondaries which are similar in time Three diode currents each have a unique charge passed through them during D 2 T s id charge 1/2 ipeakd2ts D1 D2 01 Current flow in L M is on for 09 T s, given D 3 fixed at 01

6 6 ilm 09 diodes on 01 t Notice the fact that for the buckboost and flyback: i Lm = i(diode) i(transistor) The corresponding current in the transistor and the primary winding is: i p =i TR transistor on for D 1 T s Remember i D is secondary current, whereas i Lm is the primary current Values of Diode Peak Currents: (Given chosen maximum off voltages) D1 i D1(peak) = 2 i (DC) = (2)(1) = 4 A D2 05 D2 i D2 (peak) = 2 i (DC) (2)( 1 = 2 ) = 2 A D2 05 D3 i D3 (peak) = 2 i (peak) = (2)(4) = 16 A D2 05 We must check that each diode can carry these current levels from the diode manufacturer spec sheets Peak I Lm is worth calculating because hysteresis core loss varies t

7 with peak current, not rms current 7 i Lm (peak) = Σ i Dx *1/n x primary secondary current diode currents n = = V V, n = 15 p 135 = V V, n = p i Lm(peak) = = 126 A We must check that this peak current does not saturate the magnetic core Transistor peak current i TR (peak) = i Lm (peak) = 126A V Lm = L d i m Lm dt i Lm (peak) = V L Lm m g D1T s = V Lm D T 1 s i Lm depends on L m values The L m value of the chosen transformer is set by the peak transistor current Vg L m = D T = (165)(4) 2 s ipeak 126 = 052 mh 5 10 Calculate I RMS using the above current waveforms and Appendix 1 on pg 705 of Erickson s text

8 [I (output)] = (peak) * D2 x RMS i Dx 3 x x = 13 for the three secondary windings I 1 (rms) = 4 * 41 = 163 I 2 (rms) = 2 * 41 = 081 I 3 (rms) = 16 * 41 = 653 I Lm(rms) = i Lm(peak) D 1D2 3 = 069 A 8 II Forward Converters A Overview Here we choose in the circuit topology the dots on the transformer coils and the primary / secondary diode placement so that when primary current flows so will secondary current unlike the flyback converter Hence, the name forward converter Three secondary arrangements for the forward converter are given below: Simple center tapped transformers are the key elements to one approach Full wave rectification without isolation of the secondary voltages and without center taps is a second approach to the forward converter topology Fully isolated secondaries without center taps with full wave rectification is the third topology approach Note that in all cases the transformer has the role of dielectric isolation, which is accomplished by the choice of isolation material between wire windings on the transformer The winding turns ratio provides the step up or step down ratio desired There is no air gap in the core so the forward transformer stores no energy, it merely transfers energy form the primary coil to the secondary coil Of, course we must never allow the peak flux in the transformer core to EXCEED THE SATURATION VALUE of the chosen core Forward converters posses both a transformer and an output choke and this distinguishes them from flybacks of lecture 14

9 On the next page we will outline the voltage and current waveforms in a simple halfwave forward converter to give a clear picture of the unipolar drive that occurs in each portion of the transformer secondary that is synchronous with the primary drive sequence In full wave center tapped operation each half of the transformer sees similar waveforms The full wave rectification in the secondary insures that the current waveforms are unipolar as does halfwave rectification 9

10 10 Notice that the output circuit of an LC filter directly after the power switch or output rectifier is the CALLING CARD of the forward converter This is clearly a BUCKLIKE TOPOLOGY with V out being proportional to D x V in B DCM Forward Converter Operation: Two Case Studies On the following pages we will outline the operation of froward converters operating in the DCM of operation via two illustrative examples One will employ a single transistor switch while the second will employ two temporally synchronized switches DCM operation is more complex than CCM operation due to the third time interval that is introduced into the switching period, T sw

11 1 DCM operation using only one transistor I out is nonpulsating for a fixed load and the LRC filtering 11 For the Forward Converter notice that: buck like operation occurs in the secondary circuit to the right of diodes D 2 and D 3 To start with, for the dotted transformer windings always assume all currents flow into the dots and n 1 i 1 n 2 i 2 n 3 i 3 = 0 n 1 : n 2 : n 3 D 2 D 3 L C R V Q 1 D 1 If the input, or primary, current flow direction is known by circuit means to flow the opposite to that initially assumed then this reverse flow occurs also at other coils The dotted side specifies which way current flows DCM operation has three intervals in T s of duration D 1, D 2 & D 3 i Lm is reset to zero so that saturation of the magnetic core does not occur as follows, in DCM operation Interval D 1 T s : Q 1 and diode D 2 conduct creating simultaneous primary and secondary transformer currents while diodes D 1 and D 3 are off again by current flows All currents are assumed into the dots of all windings a) When Q 1 is on appears across n 1 b) A voltage of polarity n 2 /n 1 appears across turn n 2 D 1 is off This is also seen by current flow i 1 flows into dot of

12 coil #1 i 3 flows out of the dot of coil #3 and D 2 is on c) n 3 /n 1 appears across turn n 3 diode D 2 is on drawing a secondary current which appears in the primary as i 1 Then the current drawn from is i 1 = i m i 1 ' Note that the primary is composed of the magnetizing inductance in parallel with the n 1 winding as per the standard transformer model Coil #2 is open because of diode D 1 being off i m L m n 1 : n 2 : n 3 i1' v 1 i1 v 2 i2 i3 D 2 on v 3 v D3 L C R V 12 Q 1 on D 1 off Interval D 2 T s : Q 1 is put off actively by the control signal forcing a current loop in L m and the n 1 coil This causes current to flow out of the n 1 coil at the dotted end, and current flows into the dotted end of the n 2 coil i m L m n : n : n i 1 ' v 1 i 1 v 2 i 2 i 3 v 3 D 3 on L v D3 C R V Q 1 off D 1 on i m now flows in the n 1 winding as shown exiting the dot of the n 1 coil The n3 coil has current flow into the dotted end

13 n 1 13 L m i m i m In total then the conservation of mmf gives: n 1 i 1 n 2 i 2 n 3 i 3 = 0 sign is into dot sign is out of dot i 2 and i 3 coil current directions are as assumed but i 1 is known to flow out of the dot of the n 1 coil due to Q 1 being off during the i 1 time interval D 2 T s Due to the current flow direction we can say that during D 2 T s : Q 1 is off and diodes D 1 and D 3 are on whereas diode D 2 is off as shown above Diode D 1 is on because of current flow into the dot of winding n 2 which turns D 1 on Diode D 2 is off because of current flow into the dot of winding n 3 which turns diode D 2 off Diode D 3 is on because of current flow into the dot of winding n 3 equals i 3 out of undotted n 3 turning D 3 on With diode D 1 on we have: INPUT OUTPUT across n 2 coil so Current i 3 as shown flows by the dot convention from the n 3 coil to the output 1 V Lm = V n g n 2 and this negative voltage across L m causes the magnetizing n1 Vg current to decrease with a slope di/dt: n2 Lm

14 Note also that in the primary we have the sum of two voltages across the transistor [V (off)] = V [1 n 1 Tr max g n ] 2 14 Interval D 3 T s : i Lm will try to reverse sign after the time period D 1 T s going up and the time period D 2 T s going down as shown below in the i Lm plot versus time Vg 1 2 (upslope) V n / n g (downslope) Lm Lm Vg/Lm Vg(n1/n2)/Lm First i Lm hits zero then i Lm tries to go negative At this point a new circuit topology arises as diode D 1 goes off and diode D 3 goes on i m =0 L m n : n : n i1' v 1 i 1 v 2 i 2 i 3 v 3 D 3 on ilm v D3 L C R V Q 1 off D 1 off If i Lm now goes negative with Q 1 off then the dot convention tells that the i Lm current loop now enters the n 1 winding from the dotted side in the current loop seen below n 1 Q 1 off This current flow direction for i 1 causes i 2 to also try to flow into the dotted side of coil #2 as shown below:

15 n 2 But i 2 tries to flow out but diode D 1 does not allow this direction of current flow So diode D 1 goes off 15 D 1 Likewise i Lm flow into n 1 dot current flow into the n 3 dot and D 3 is turned on when i Lm hits zero Since both transistor Q 1 and diode D 1 are off i Lm remains zero for the whole period D 3 T s A tradeoff must be made in the forward converter since: 2 D 2 = n 1 n D n moving the turns ratio 2 1 n allows the interval D 1 1 for fixed interval D 2 BUT n1 n implies that the standoff voltage across the transistor 2 increases since: 1 V Tr (off) = [1 n ] So we trade off decreased Tr on time n 2 D 1 for increased voltage stress This transistor switch voltage stress may be too much for one transistor to work in its safe operating area (SOA) Below we show a way to solve this by utilizing two rather than one switch and dividing the switch stress between them

16 2 Two transistor implementation of the Forward Converter operating in DCM operation What do you guess the phasing of Q 1 and Q 2 gate control is? 16 D 1 Q 1 1:n D 3 D 4 L C R V D 2 Q 2 The tandem transistors Q 1 and Q 2 have the same phase gate control So they are both in the same state Here our L m is considered large as the core has no slotted opening and the core magnetic reluctance is low Although i Lm is small we still we need to consider L m effects Now the primary voltage when Q 1 and Q 2 are both off can be dropped across the two transistors as both are in series, reducing switch stress to more allowable levels Interval D 1 T s : Control signal forces both Q 1 and Q 2 on, primary diodes D 1 and D 2 are both off Current flow is such that i 1 (primary) flows into the dot end of the one turn coil so i 2 flow is out of the secondary winding of n turns The secondary current is 1/n of the primary current

17 17 1:n i n i 1 when i 1 flows into the dot on winding 1 a current i 1 /n flows out of the dot on the n turn winding as shown above This insures that diode D 4 is off and diode D 3 is on i g 1:n n L C R i m /L m The current in L m increases linearly during switch interval D 1 with a slope /L m Interval D 2 T s : The external control signal forces both Q 1 and Q 2 off Both primary diodes D 1 and D 2 are on as shown below during the interval D 2 T s driving the magnetizing current down during time D 2 T s gnd D 1 i Lm Lm 1:n D 3 off n L D 4 on C R V o D 2

18 18 Note that i Lm flow is always positive with respect to zero during intervals D 1 and D 2 It first rises during D 1 T s and then falls during D 2 T s as shown below What occurs if i Lm does not reach zero? i Lm for core reset D 1 <1/2 /L m D 1 D 2 /L m T s t i m /L m The i Lm current period as shown in DCM of operation could lead over a few switch cycles to core saturation if i Lm did not return to zero DCM operation, however, guarantees that this occurs If i Lm tries to go negative, then diodes D 1 and D 2 go off and prevent it from doing so Setting/Fixing i Lm = 0 so the core doesn t saturate We will find below in part 3 for i Lm to reset the transistor on time D 1 < ½ is required Is this clearly why? Period D 3 T s : Q 1, Q 2, as well as diodes D 1 and D 2 are all off in the primary circuit i Lm = 0, V primary = 0 C Forward Transformer Overview As stated earlier we must never allow the flux density, B, in the forward converter core to exceed the saturation flux for that core If we do, the transformer will look like a short circuit and no doubt fry the power switches We will employ Faraday s law to see the trends between transformer core size and the choice for the

19 number of turns in the windings V(out) = N(# turns of wire) x ω(radian frequency)x φ(flux) 19 Where φ(flux) given by is given by B(flux density)x A core (core area) Now each core material has a maximum allowable flux density that it can handle before the onset of core saturation Hence, we can say that there is a required number of turns on the transformer windings Consider first the primary windings We will find below the result that N varies inversely with B max (saturation value) N primary = V primary /(ω x B max x A core ) That is the MINIMUM number of primary winding turns varies as: the input voltage level V primary Inversely with operating frequency Inversely with the saturation flux of the core Inversely with the core size Clearly, there is lots of design tradeoffs to be considered Regardless, once the number of primary winding turns is set this acts as the reference for all other secondary winding turn choices as described below The secondary turns are unique for each secondary voltage desired We start with the secondary that requires the most output power The voltage across the output rectifers should also be accounted for The starting point for all such calculations is the fact that the voltage in a specific winding divided by the number of turns in that winding must be equal to the output voltage of another winding divided by its number of turns Finally, we have to consider worst case when the input voltage is minimum, V in (min), and the duty cycle is maximum, D max That is we find the relationship: N secondary = N primary x( V out V diode ) V in (max) x D max We solve for N sec at lowest V in and highest D we expect to occur

20 20 The result is always a noninteger number and one must round off to the nearest number of turns This could result in the output voltage being not what we desire Again an iterative process is required to meet all desires Note that adding secondary turns on the primary winding will always move you in the safe direction of a lower flux density, below the dangerous B(saturation) D DCM Forward Converter with External Reset to actively avoid core saturation Next we explain how to actively achieve L m core reset by use of an external voltage source, with the secondary goal of causing less standoff voltage stress for both Q 1 and diode D 2 Also the duration D 1 T s can be increased so for a fixed D 2 T s : 3 3 D 2 = n 1 n D n can be reduced if D 1 T s increases Why is this good? 1 n1 fixed If n3 Lower peak transistor current occurs n1 Erickson Problem 69: External V r resets the core with less stress than reset with as shown below: Note that the auxiliary secondary winding n 2 is not an output circuit, rather it is a reset voltage entry point The full schematic is shown on the following page

21 21 n :n 1 3 D 3 D 2 R v Q 1 reset winding D 1 V r :n 2 In DCM operation there will be 3 periods as shown below: D 1 T s Q 1 on Diode D 2 on Diode D 3 off Diode D 1 off D 2 T s Q 1 off Diode D 2 off Diode D 3 off Diode D 1 on D 3 T s Q 1 off Diode D 2 off Diode D 3 off Diode D 1 off Interval D 1 T s : Diode D 2 on and diode D 3 off in the winding n 3 n :n L 1 3 i v L n 3 /n 1 i c v/r C R V :n 2 During interval D 1 T s an effective DC voltage of magnitude D(n 3 /n 1 ) appears across winding n 3 As diode D 1 is off, V R does not affect the core flux levels V R

22 Interval D 2 T s : Diode D 1 in winding #3 is on activating the reset current on the magnetic core The current i Lm flows out of the n 1 winding dot implying current flows into both n 2 and n 3 windings Hence, diode D 2 is off and diode D 1 is on 22 i Lm n 1 n 3 L C i C v/r R V n 2 i R V R Reset of core via integrating V R for the interval D 2 T s Interval D 3 T s : All circuits are open and no voltsec drive to the magnetic core flux occurs L C i C v/r R V V R Below we calculate the applied V R to the windings required for duration D 2 T s to cancel applied for duration D 1 T s to winding #1 Magnetizing Inductor: L M Voltsec balance to L M has only two components

23 < V > = 0 V D T D [ N1 Lm Ts g 1 s 2 V r ] T s = 0 N2 < V > = 0 D = V Lm Ts sets the relation 2 V D 1 n r n1 Setting D 1 and D 2 still must leave a nonzero interval D 3 T s D 3 = (1D 1 D 2 ) > 0 1 D1 n1 1 > V D n V g 1 2 R g 1 or 2 V R > V D n Sets minimum value of V R to be applied (1 D 1) n1 during interval D 2 T s for L m core reset g 2 23 Consider Switch Stress for Interval D 2 T s 1 V Tr (off) = n VR substitute for via n2 from appears on n 1 coil due source to V R on n 2 coil 1 V Tr (off) = [1 D 1 D ] 1 V Tr (off) = / (1 D 1) Output Inductor of Buck : L <D3> = V o <V L > Ts = 0 voltage equal either side 1 V = V D = n n * V 0 sets D 1 T s time so L has V 3 D n 1 g o 1 n1 <V L > Ts =0 in steady state 3 g

24 24 The above summarizes a comparison between flyback and forward converter topologies as regards the switch stress and a crude estimate of the required SOA for the switches Finally, For HW#3 Due in 1 week: 1 Answer any Questions asked throughout lectures Chapter 6 Problems 7, 8, and 11(the forward converter)