Under the Hood of Flyback SMPS Designs

Transcription

1 Topic 1 Under the Hood of Flyback SMPS Designs Bing Lu

2 Agenda 1. Basics of Flyback Topology 2. Impact of Transformer Design on Power Supply Performance 3. Power Supply Current Limiting 4. Summary Texas Instruments 2010 Power Supply Design Seminar 1-2

3 Transfer of Energy FET turns ON Voltage across primary magnetizing inductance V i Energy is stored in flyback transformer: Function of L, D and T s Secondary diode in blocking state FET turns OFF During commutation: Leakage energy absorbed by clamp circuit Stored energy transferred to output through diode If DCM operation, all the stored energy is transferred I P I o V i 1:n 2 V o Clamp I P V drain - - I out Pulsating input and output current Texas Instruments 2010 Power Supply Design Seminar 1-3

4 Transfer of Energy FET turns ON Voltage across primary magnetizing inductance V i Energy is stored in flyback transformer: Function of L, D and T s Secondary diode in blocking state I P I o FET turns OFF During commutation: Leakage energy absorbed by clamp circuit Stored energy transferred to output through diode If DCM operation, all the stored energy is transferred V i I o 1:n 2 V o Clamp I P V drain - I out Pulsating input and output current Texas Instruments 2010 Power Supply Design Seminar 1-4

5 Transfer of Energy FET turns ON Voltage across primary magnetizing inductance V i Energy is stored in flyback transformer: Function of L, D and T s Secondary diode in blocking state I P I o FET turns OFF During commutation: Leakage energy absorbed by clamp circuit Stored energy transferred to output through diode If DCM operation, all the stored energy is transferred V i I o 1:n 2 V o Clamp V drain - I out Pulsating input and output current Texas Instruments 2010 Power Supply Design Seminar 1-5

6 Transfer of Energy FET turns ON Voltage across primary magnetizing inductance V i Energy is stored in flyback transformer: Function of L, D and T s Secondary diode in blocking state FET turns OFF During commutation: Leakage energy absorbed by clamp circuit Stored energy transferred to output through diode If DCM operation, all the stored energy is transferred Pulsating input and output current V i 1:n 2 V o Clamp V drain I out Texas Instruments 2010 Power Supply Design Seminar 1-6

7 CCM versus DCM Continuous conduction mode (CCM) Small ripple and rms current Lower MOSFET conduction and turn-off loss Lower core loss Lower capacitors loss Can have better full load efficiency Smaller EMI and output filters Discontinuous conduction mode (DCM) No diode reverse recovery loss Lower inductance value May result in a smaller transformer Better no load efficiency First-order system Inherently stable No RHPZ problem Slope compensation not needed in CMC Primary MOSFET Primary Current Time (t) Texas Instruments 2010 Power Supply Design Seminar 1-7 V drain I P Secondary Current I o V drain Primary MOSFET Primary Current I P Secondary Current I o DxT s ΔI LS D T s ΔI L V o Vi n2 m 2S V o V i n2 T I pkmin T s Time (t) V i I o_avg I pk Idle Period (1D)xT s I pk (1 D) T s I o_avg

8 Right-Half-Plane Zero, CCM Operation Energy is delivered during 1 D Effect of control action during ON time is delayed until next switch turn OFF Initial reaction is in opposite direction of desired correction RHP Zero Phase decreases with increasing gain f ( 1 D) 2 Vo = π RPHZ 2 2 L D Iout n2 D Main switch duty-cycle V i 1:n 2 V o Clamp I P V drain - - V i I o 1:n 2 V o Clamp V drain FET ON - FET OFF I out I out Texas Instruments 2010 Power Supply Design Seminar 1-8

9 RCD Clamp Circuit During commutation primary-tosecondary, the leakage energy is absorbed by the clamp circuit R clamp dissipates the leakage energy and some magnetizing energy The clamp capacitor ensures a low voltage ripple Use short connection with minimum loop area V clamp is maximum at full load and minimum input voltage R clamp selected for a maximum drain voltage in worst case Tradeoff between efficiency, peak drain voltage, output current limit and cross regulation (see ringing effect) R clamp V clamp Clamp-Diode Forward Recovery V drain Primary MOSFET V i Vclamp V i Diode or Synchronous N1:N2 Rectifier I P V drain R S Leakage-Inductance Demagnetization V i V n o V o Texas Instruments 2010 Power Supply Design Seminar 1-9

10 Agenda 1. Basics of Flyback Topology 2. Impact of Transformer Design on Power Supply Performance 3. Power Supply Current Limiting 4. Summary Texas Instruments 2010 Power Supply Design Seminar 1-10

11 Transformer s Leakage Inductance Transformer s leakage inductance represented by L leak2 Primary winding is the closest to center gap When FET turns OFF L leak2 opposes to I P decrease and I S increase Magnetizing inductance works to maintain magnetizing current V i I P V Clamp mag1 FET Clamp Diode Forward Recovery V i V clamp L m N1:N2 Vmag2 Leakage Inductance Demagnetization L leak2 V leak2 I S V D Current Circulates in Secondary Winding(s) V out V i V clamp During Primary-to- Secondary Commutation W2 W1 ø Leakage Inductance Resonates with Drain Capacitance Voltage spike on FET during commutation Rate of rise of current is influenced by leakage inductance V FET V mag2 V leak2 0V V clamp Clamp Capacitor Voltage V mag2 V D V out V FET Clamp Capacitor Voltage Reduction in Magnetizing Current Due to Faster Commutation Commutation primary-tosecondary is not instantaneous and depends on V clamp Loss of volt-seconds I P I S D tr Low Clamp Voltage Lost Volt-Seconds I P I S D tr High Clamp Voltage Texas Instruments 2010 Power Supply Design Seminar 1-11

12 Effects of Leakage Inductance Clamp circuits and snubbers needed for primary FET and secondary rectifier(s) Lower power-supply efficiency Impact on gate-drive strategy if synchronous rectifier is used Higher duty cycle and magnetizing current than expected Higher H-field radiated emission High impact on cross-regulation Texas Instruments 2010 Power Supply Design Seminar 1-12

13 How Leakage Can Be Minimized Leakage inductance is a function of winding geometry, number of turns and separation between primary and secondary Minimize the separation between the primary and main secondary winding(s) Interleave the primary and main secondary Select a core with a long and narrow window L L W2 W1 W1 W2 W2 W2 W1 W1 W1 W2 W1 W2 W1 W2 W2 W1 Option 1 Option 2 Leakage inductance is not lowered with a high permeability core Having the winding tightly coupled to the core will not reduce it Texas Instruments 2010 Power Supply Design Seminar 1-13

14 Cross-Regulation Overview Multiple-output flyback topology is popular because of its simplicity and low cost If the coupling is perfect, the turns ratio directly defines output voltages In the real world, perfect coupling is not possible This often results in poor cross-regulation Texas Instruments 2010 Power Supply Design Seminar 1-14

15 Cross-Regulation Physical Model Transformer windings cannot all be equally well coupled to the gap because of physical separation between them Magnetic energy stored between the windings represented as leakage inductances Model not applicable to any transformer geometry Can become complex if interleaving is used, or if multiple secondary windings are wound simultaneously (multifilar) Not accurate in situation of lightly loaded secondary outputs Good tool to understand how the common flyback transformer geometries work Texas Instruments 2010 Power Supply Design Seminar 1-15

16 Cross-Regulation Physical Model V i l p Clamp FET l W4 N4 l W3 N3 l W2 N1:N2 V4 V3 V2 W1 Primary W2 W3 W4 Basic Flyback Circuit Transformer Construction l p L leak12 L leak23 L leak34 V i Clamp V mag1 L m N2:N3 N2:N4 I 2 I 3 I W3 I W4 I 4 N1:N2 FET V2 V3 V4 Transformer Physical Model This circuit is only applicable to the transformer windings stackup shown Each leakage inductance considered is between two consecutive secondaries Also called Ladder model Texas Instruments 2010 Power Supply Design Seminar 1-16

17 Flux Lines during Commutation Each Secondary Winding with Nominal Load φ m decreases during commutation dφ/dt (decreasing) in each secondary winding is limited by its output voltage Increasing current induced in W2 to dφm e= N W4 to maintain dt φ m in the gap φ m W2 W1 W3 W4 L Leakage between W2 and W1 W1 s voltage limited by clamp W1 closest to gap V clamp limits dφ m /dt in the gap during commutation W2 is next to W1 W2 limits the dφ/dt seen by W3 and W4 W3 and W4 output voltage lower than without leakage Current commutates progressively from near to remote secondary windings During Primary-to-Secondary Commutation Current in All Windings l p Secondary Currents During Commutation Based on Physical Model I 2 I 3 I 4 Texas Instruments 2010 Power Supply Design Seminar 1-17

18 Ringing Effect High dv/dt when main switch turns off if main output is heavily loaded Transformer leakage inductance and parasitic capacity auxiliary secondary voltage tends to ring If auxiliary output fully loaded this ringing is clamped If lightly loaded voltage overshoot with peak detector effect Much higher (sometimes > 2 x nominal value!) auxiliary output voltage at light load Primary clamp voltage has high impact on result Most existing transformer models fail to predict this This effect can be mitigated (but not eliminated) Minimize leakage inductance between secondary windings Locate the highest power secondary(ies) closest to the primary Other solutions include a post-regulator, series resistor or minimum load Texas Instruments 2010 Power Supply Design Seminar 1-18

19 Cross-Regulation Example Auxiliary Output Lightly Loaded W2 (high current output) heavily loaded, W4 lightly loaded W4 s output received too much energy during Phase 1 due to ringing W2 s output did not receive enough energy I W4 I W3 V3 I 4_pk I 3_pk Effect of V3 Capacitors ESR At end of commutation (Phase 1): I W2 I 2_pk Σ{reflected secondary currents} magnetizing current V mag1 V4 went too high Phase 2: high dφ/dt (decreasing) in W4 I W4 0 A rapidly I W2 increases to maintain φ m in the gap I P Phase 1 φ m I P_pk Phase 2 Phase 3 Time (t) After I W4 crosses 0 A, W2 s and W3 s di/dt change to maintain the downslope of the magnetizing current and flux φ H δ= m δ= N I A μ W1 W3 W4 Texas Instruments 2010 Power Supply Design Seminar 1-19 W2 Phase 2: No Primary Current

20 Test Results V DD 10 Ω R W3 Current Probe I W6 V6 V AW3 W3 (9T) W6 (9T) 6.8 µf R6 Current Transformer V_I prim 100:1 Current Probe I W4 V4 W1A W1B W2 W4 W3 W6 36 Ω 300 Ω W4 (14T) 6.8 µf R4 V i 5 V R clamp 15 kω 0.1 µf V clamp MURS120 W1 (21T) I P W2 (4T) I W2 Current Transformer 1: Ω 249 Ω V_I sec Input voltage: 48 V 5-V output load: 0 A to 5 A Auxiliary outputs: V6 (10 V at 0 to 140 ma) and V4 (18 V at 0 to 200 ma) To CS Input Primary MOSFET Sync Rectifier Switching frequency: 250 khz Primary magnetizing inductance: 70 µh I 5 V To 5-V Filter and Load Texas Instruments 2010 Power Supply Design Seminar 1-20

21 Cross-Regulation Test Results with Main Output Fully Loaded I W6 (0.5 A/div) I W6 (0.5 A/div) I W4 (1 A/div) I W4 (1 A/div) 4 I W2 (2.94 A/div) I W2 (2.94 A/div) 1 1 Time (0.5 µs/div) V6 at 1.6 W, V4 at 2.5 W, I 5 V = 5 A Time (0.5 µs/div) V6 at 0.5 W, V4 at 3.6 W, I 5 V = 5 A The two auxiliary outputs operate in DCM Notice the change of slope of I W2 when I W4 or I W6 crosses 0 A Texas Instruments 2010 Power Supply Design Seminar 1-21

22 Cross-Regulation Test Results: Lightly Loaded Auxiliary with Main Output Fully Loaded I 5V =5A, V4 at 0.3 W, V clamp =70V V6 (10 V/div) 12.4 V I 5V =5A, V4 at 0.3 W, V clamp =70V V6 (10 V/div) 20.6 V V W6 (10 V/div) V W6 (10 V/div) I W6 (200 ma/div) Time (1 µs/div) V6 at 0.5 W Time (1 µs/div) V6 at < 5 mw At minimum load, V6 (10 V nominal) goes up to 20.6 V Texas Instruments 2010 Power Supply Design Seminar 1-22

23 Cross-Regulation Test Results with Main Output Fully Loaded : Impact of Clamp Voltage I 5V =5A, V4 at 0.3 W, V clamp =83V V6 (10 V/div) 14.4 V I 5V =5A, V4 at 0.3 W, V clamp =83V V6 (10 V/div) 26 V V W6 (10 V/div) V W6 (10 V/div) I W6 (200 ma/div) Time (1 µs/div) V6 at 0.5 W Time (1 µs/div) V6 at < 5 mw RCD resistor has been increased for higher V clamp : 70 V 83 V V6 increased significantly in both cases Texas Instruments 2010 Power Supply Design Seminar 1-23

24 Overload Test at Auxiliary Output: Impact of Leakage There was no hiccup mode even at more than 3 A! 4 I W4 (1 A/div) I 5V =0A, V4 at 2.5 W, R6 = 1 Ω The overloaded winding is unable to take all the energy because of leakage, W3 having in fact a better coupling to primary than W6 Enough energy delivered by W3 to V DD to maintain switching 3 2 V AW3 (20 V/div) I W6 (2 A/div) Time (0.5 µs/div) 6.2-A Peak Texas Instruments 2010 Power Supply Design Seminar 1-24

25 Benefits of Good Cross-Regulation Good control of auxiliary outputs in spite of load variations Better control of gate drive voltage amplitude, less gate drive losses Lower rms current in output capacitors, lower dissipation May allow the controller to reach hiccup mode more easily when the main output is short-circuited for better protection Not necessarily true if the short-circuit is applied to an auxiliary output! Texas Instruments 2010 Power Supply Design Seminar 1-25

26 How Cross-Regulation can be Improved The high current winding must have the best coupling to primary Minimize leakage between all secondary windings Optimize, not minimize, the leakage inductance of auxiliary windings to primary Use winding placement to control leakage inductance Winding stackup Spread each winding over the full width of the bobbin for better coupling Primary A W2A Primary B W2B W3 or Primary A W2A Operate main output in CCM W3 W2B Primary B Better than Try to avoid operating the auxiliary outputs in DCM. In some cases, consider using resistance in series with the diode Consider winding more than one auxiliary secondary simultaneously (multifilar) Lower clamp voltage may help Trade-off between cross regulation, efficiency, peak drain voltage and current limit Some other types of clamp circuits may provide better results than the RCD clamp Texas Instruments 2010 Power Supply Design Seminar 1-26 Primary A W2A W2B Primary B W3 If W3 is lightly loaded and W2 is the highcurrent main output.

27 Impact of Transformer Design on Flyback Efficiency The following guidelines can be used during transformer design to optimize the converter efficiency Minimize leakage inductance from primary to main (high-current) secondary Minimize transformer high frequency conduction loss Multifilar or Litz wires when necessary Interleaving Select core shape for minimum number of layers Optimize the transformer turns ratio for best efficiency Select CCM operation Other factors also have an indirect impact on efficiency Cross-regulation V DD rail used for gate drive Output capacitors rms current Impact of fringing flux from gap Worse with planar transformers Secondary RMS Current Squared at 48 V Good Duty-Cycle Trade-Off with 48-V Input x Primary RMS Current Squared at 48 V Duty Cycle (%) Texas Instruments 2010 Power Supply Design Seminar x Primary RMS Current Squared (A ) 2 Secondary RMS Current Squa red (A ) 2

28 Flyback and EMI Flyback I P and I S pulsate Use low Z caps, minimize loop areas Output filter often required Interwinding capacitance CM CE Transformer and diode configuration impact effective capacitance Less if facing windings at same AC potential Diode versus synchronous rectifier Flyback Forward I CM 2 V i I CM 2 I DM V i I P Clamp FET P N1:N2 S I S V D V out Output to Chassis CM Better to start with end connected to primary MOSFET Shields V drain E-field Reduces interwinding capacity effect on CE Minimize leakage for low H-field RE Interleaving reduces H-field RE but may increase effective P-S interwinding capacitance Center-gap transformer Texas Instruments 2010 Power Supply Design Seminar 1-28 FET Primary A Primary B Primary C Secondary A Secondary B Other Secondary V out V D

29 Agenda 1. Basics of Flyback Topology 2. Impact of Transformer Design on Power Supply Performance 3. Power Supply Current Limiting 4. Summary Texas Instruments 2010 Power Supply Design Seminar 1-29

30 Power Supply Current Limiting Overview Current-limiting characteristic of power supply defines: Output power beyond which output voltage falls out of regulation. Corresponds to the output load-current limit (I out_lim ) Output current in overload situations including short-circuits Current-limiting characteristic is influenced by parasitics Turn-off delays, leakage inductance, Texas Instruments 2010 Power Supply Design Seminar 1-30

31 Understanding Current Limit Flyback Power Supply with Peak CMC in CCM Clock Ramp Slope Comp Clamp V i I o 1:n2 V o I out Primary Current D x T s ΔI L I A_LIM I pk_lim Power Supply Controller PWM COMP (From Error Amp) I_SENSE V C V C_LIM R SC C R Current- Sense Filter R s Secondary Current m 2S (1 D) x T s Time (t) Just at Current Limit, Output Begins to Fall Out of Regulation I o_avg I pk_lim is the primary peak current limit I o_avg is the output current If short-circuit, I o_avg can be much higher than when current limit has just been reached Primary Current Secondary Current (1 D) x T s I pk_lim D x T s Time (t) Output Short Circuit IA Iout = Io_avg = 1 D n 2 ( ) I o_avg Texas Instruments 2010 Power Supply Design Seminar 1-31

32 Current-Limit Model Basic Representation Peak CMC in CCM, fixed switching frequency ΔI L m 2 m 1 I pk = V C R S I A (Average Magnetizing Current) Gate Control D T s Neglecting DC voltage drops: m 2 ΔIL Vo = 1 D T n L ( ) S 2 D Vo = n V V 2 i o Texas Instruments 2010 Power Supply Design Seminar 1-32

33 Influence of Input DC Voltage on Output Load Current Limit Impact of Feedforward Power Supply Controller PWM COMP (From Error Amp) Clock Ramp R ff Feedforward I_SENSE V C V C_LIM Slope Comp R SC C R Clamp V i I o 1:n2 R s V o I out Output Load Current Limit (A) Without Feedforward With Feedforward If V i (1 D) I out_lim Input Voltage (V) increases With feedforward, output load current limit becomes almost independent of input voltage Better control during overload, less stress on power circuitry Power limit Cost and/or size reduction Feedforward also improves line noise rejection Texas Instruments 2010 Power Supply Design Seminar

34 Current Limit Model With Feedforward K ff Vi R m S 2 V C R S I pk R S Magnetizing Current) R m S 1 R S I A D T s Gate Control K ff x V i is the feedforward contribution Subtracting it from V c is identical to adding it to current feedback Texas Instruments 2010 Power Supply Design Seminar 1-34

35 Current Limit Model Adding Slope Compensation Slope Compensation (Clock Ramp) (T m0 x s T dis) 2 m 0 K V ff i V C R S I A R S I L_pkmin Gate Control D T 2 D T s s R m S 2 R m S 1 T dis Slope compensation to avoid subharmonic oscillation at duty-cycle close to or higher than 50% For easier understanding, slope compensation contribution subtracted from V c. Equivalent to slope compensation added to current feedback In that circuit representation, the slope compensation is capacitively-coupled Texas Instruments 2010 Power Supply Design Seminar 1-35

36 Current Limit Model With all Delays, Slope Compensation and Feedforward For a more accurate, parasitics must be included in the analysis Parasitic delays RC filter time delay Turn off delay, including current comparator and gate drive FET turn-on delay from onset of slope compensation ramp See Topic 1, Appendix A, in the Seminar Manual for detailed equations Texas Instruments 2010 Power Supply Design Seminar 1-36

37 Influence of Transformer Leakage on Output Load Current Limit Rate of rise of current is influenced by leakage, commutation primary-tosecondary is not instantaneous Loss of volt-seconds (also influenced by the clamp voltage) Duty-cycle and average magnetizing current have to increase to maintain the output voltage Higher conduction loss Higher transformer peak current than expected -> I out_lim lower than expected V i I P Clamp I P I S V mag1 FET Ideal Xfmr N1:N2 L m Vmag2 L leak2 V leak2 I S V D V out Leakage inductance helps however to keep control of the output current in output short-circuit situation Lost Volt-Seconds V V D V D 1 D D ( ) o i new clamp tr new tr n2 Texas Instruments 2010 Power Supply Design Seminar 1-37 D tr

38 Current Limit During Overload Example with Combined Effects In overload: Output current increases output voltage decreases Short-circuit: output current much higher than at onset of current limit Parasitic turn off delays may result in an out of control current if volt-seconds balance is not possible at the transformer Transformer s leakage inductance helps to maintain that balance If no leakage, the imbalance occurs starting at V o1 With leakage, the imbalance occurs only from V o2 Output Current (A) V o_short n 2 Assuming no hiccup mode Output Voltage (V) ( TS tdel_off Dtr TS) = V t V D T i del _ OFF clamp tr S Texas Instruments 2010 Power Supply Design Seminar Without Leakage With Leakage V o1 0 V o2 Short Circuit

39 Summary The flyback power transformer is the key element of the converter, for optimum efficiency and cross-regulation Parasitics have a strong influence on flyback converter s behavior, particularly under overload or short-circuit conditions The primary clamp circuit design is a trade-off between: Efficiency Peak drain voltage Output current limit Cross-regulation Simple feedforward technique can be used to optimize the converter and the system, lowering worst-case components stress and reducing the overall cost and size Texas Instruments 2010 Power Supply Design Seminar 1-39