CONTINUOUS-TIME DELTA-SIGMA MODULATORS WITH ENHANCED NOISE-SHAPED QUANTIZER

Transcription

1 CONTINUOUS-TIME DELTA-SIGMA MODULATORS WITH ENHANCED NOISE-SHAPED QUANTIZER By TAEWOOK KIM A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY UNIVERSITY OF FLORIDA 2017

2 2017 Taewook Kim

3 To my wife, Hyejin Oh

4 ACKNOWLEDGMENTS I would like to thank my advisor, Dr. Nima Maghari for his guidance and support throughout the pursuit of my Ph.D. It is my great honor and pleasure to work with him. I respect his enthusiasm for research and teaching. Dr. Maghari provided many informational and insightful suggestions to my research from the beginning. I would also like to thank my committee members: Dr. William R. Eisenstadt, Dr. Rizwan Bashirullah, and Dr. John Conklin who provided excellent service with useful guidelines on my Ph.D program. I am also indebted to my colleagues, Changsok Han, Ahmed Fahmy, Jun Liu, Arun Javvasi, Troy Bryant, and Beomsoo Park for their useful and helpful discussions on the research. Further, I would like to thank my family in Korea for their continued support and positive perspective with unconditional love. Specially, I thank my wife Hyejin Oh for her endless love and support. 4

5 TABLE OF CONTENTS page ACKNOWLEDGMENTS... 4 LIST OF TABLES... 7 LIST OF FIGURES... 8 LIST OF ABBREVIATIONS ABSTRACT CHAPTER 1 INTRODUCTION Motivation Research Contribution Dissertation Outline FUNDAMENTALS OF DELTA-SIGMA MODULATOR Oversampling ADC Quantization Oversampling Delta-Sigma Modulator Basics Noise-Shaping Multi-bit Quantizer Discrete-Time Vs. Continuous-Time DSMs Opamp Power Consumption In DSMs OVERVIEW OF NOISE-SHAPING QUANTIZERS Noise-Shaped Integrating Quantizer VCO-Based Quantizer GRO-Based Quantizer PROPOSED DOUBLE NOISE-SHAPED QUANTIZER Operational Principle NSIQ and GRO-Based Quantizer Bi-Directional Scheme in the Double Noise-Shaped Quantizer Minimization Of Gain Mismatch Between NSIQ and GRO-Based Quantizer Minimum Pulse Injection In The GRO-Based quantizer

6 5 CONTINUOUS-TIME DELTA-SIGMA MODULATOR WITH NOISE-SHAPED INTEGRATING QUANTIZER AND DIGITAL INTEGRATOR Architecture Characteristic And Stability Excess Loop Delay and Pole Compensation Implementation of Main Building Blocks Gm-C Based NSIQ Quantization Prediction and Timing Loop Filter Digital Integrator and Feedback Path Measurement Results CONTINUOUS-TIME DELTA-SIGMA MODULATOR WITH DOUBLE NOISE- SHAPED QUANTIZER Architecture Modulator Implementation Effect of Leakage From NSIQ Effect of Leakage From GRO-Based Quantizer Effect of Gain Mismatch Between NSIQ and GRO-Based Quantizer Measurement Results CONCLUSION LIST OF REFERENCES BIOGRAPHICAL SKETCH

7 LIST OF TABLES Table page 2-1 SQNR (db) with 1-bit quanitzation vs. OSR with different order of NTF (L) Performance summary of the proposed CT DSM and comparison Performance summary of the CT DSM using the DNSQ and comparison

8 LIST OF FIGURES Figure page 1-1 Generations of wireless communications Types of analog-to-digital converters Characteristics of an analog-to-digital converter Quantization error of ADC PSD of the quantization noise for oversampling technique First-order DSM Magnitude of noise transfer function of a first-order DSM An example of a second-order DSM SQNR (db) with 2-bit quanitzation vs. OSR with different order of NTF (L) SQNR (db) with 4-bit quanitzation vs. OSR with different order of NTF (L) Examples of CT DSM implementations An example of a two-stage opamp with miller compensation The simplified noise-shaped integrating quantizer Conceptual modeling of the NSIQ Simplified bi-direction scheme of the noise-shaped integrating quantizer Conceptual block diagram of a VCO based quantizer and timing diagram for 1 st order noise-shaping Conceptual block diagram of a GRO-based quantizer and timing diagram for 1 st order of noise-shaping Conceptual block diagram of the double noise-shaped quantizer Architecture of the double-noise shaped quantizer Simplified schematic of the bi-directional DNSQ including the Gm-C based NSIQ and GRO-based quantize

9 4-4 The concept of bi-directional scheme for the double noise-shaped quantizer with the polarity of the quantization error A timing diagram including phases of the DLL and GRO Simplified bi-directional GRO-based quantizer Minimum pulse injection methodology Block diagrams of continuous-time delta-sigma modulators Illustrations of the quantizer input signal amplitudes The amplitude comparison at the input of the quantizer as a function of the modulator input amplitude System-level simulation of the proposed CT DSM indicating STF and the input of the quantizer for two different cases: using the NSIQ and a conventional (flash type) quantizer The ELD compensation topologies Impulse invariance transformation of the DAC2, DAC3 and the input of the quantizer The simplified schematic of the proposed 3 rd order of CT DSM The simplified architecture of the proposed noise-shaped integrating quantizer Prediction of the quantizer digital output The timing of the global DAC (DAC1). The global DAC has more time (half clock cycle) to operate than internal DACs (DAC2 and DAC3) The simplified 3-stage operational amplifier with feedforward The simplified schematic of the digital integrator The simplified scheme of the global DAC (DAC1) unit cell implementation, calibration, and SNDR effect Die microphotograph of the fabricated DSM Measured 65k-samples FFT output spectrum

10 5-16 Measured SNDR and SNR versus varying input signal amplitudes Measured STF and NTF Simplified block diagrams of the proposed CT DSM architecture using the DNSQ Simplified schematic of the implemented CT DSM using the DNSQ Behavior diagram of leakages of the NSIQ Behavioral diagram of GRO leakage SNDR performance vs. the gain mismatch between the NSIQ and the GRObased quantizer Die microphotograph of the fabricated DSM Measured 32k-samples FFT output spectrum Measured output spectrum with two input tones at 12 MHz and 12.5 MHz with -9 dbfs Measured SNDR and SNR versus varying input signal amplitudes Measured STF

11 LIST OF ABBREVIATIONS ADC BW CMFB CT DAC DEM DLL DNSQ DSM DT DWA ENOB FFT FOM GRO ISI IMD MASH MDAC NRZ NSIQ NTF OSR Analog-to-Digital Converter Band-Width Common-Mode Feed-Back Continuous-Time Digital-to-Analog Converter Dynamic Element Matching Delay-Locked Loop Double Noise-Shaped Quantizer Delta-Sigma Modulator Discrete-Time Dynamic Weighted Averaging Effective Number of Bits Fast Fourier Transform Figure of Merit Gated Ring Oscillator Inter-Symbol Interference Inter-Modulation Distortion Multi-Stage Noise-Shaping Multiplying Digital-to-Analog Converter Non-Return to Zero Noise-Shaped Integrating Quantizer Noise Transfer Function Oversampling Ratio 11

12 OTA PDF PSD PVT RZ SC SFDR SNDR SNR SQNR STF UGBW VCO VCDL Operational Transconductance Amplifier Power Density Function Power Spectral Density Process-Voltage-Temperature Return to Zero Switched Capacitor Spurious Free Dynamic Range Signal-to-Noise-and-Distortion Ratio Signal-to-Noise Ratio Signal-to-Quantization-Noise Ratio Signal Transfer Function Unit-Gain Band-Width Voltage-Controlled Oscillator Voltage-Controlled Delay Line 12

13 Abstract of Dissertation Presented to the Graduate School of the University of Florida in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy CONTINUOUS-TIME DELTA-SIGMA MODULATORS WITH ENHANCED NOISE-SHAPED QUANTIZER By Taewook Kim August 2017 Chair: Nima Maghari Major: Electrical and Computer Engineering This dissertation presents continuous-time (CT) delta-sigma modulators (DSMs) using noise-shaped quantizers. The research has explored two routes for improving the overall performance of CT DSM. The first DSM in this dissertation employs a Gm-C based noise-shaped integrating quantizer (NSIQ) with a digital back-end integrator. By incorporating the digital back-end integrator, the tradeoff between resolution and speed for a conventional time-based NSIQ is alleviated. Using only three clock edges and a low-power Gm-C, effective 4-bit quantization with an additional first order noise-shaping is achieved. Also, the linearity requirement of the quantizer is relaxed by employing the digital back-end integrator. The proposed modulator using the Gm-C based NSIQ followed by the digital integrator was fabricated in a 0.13µm CMOS process with an active area of 0.08mm 2. It operates at 640 MHz and achieves a peak SNDR of 75.3 db and a peak SFDR of 94.1 db in a 10 MHz bandwidth while consuming 7.2 mw from a 1.2V power supply. In order to improve the overall performance and efficiency of the DSM, the second DSM utilizes a double noise-shaped quantizer (DNSQ), which not only provides 13

14 2nd order noise-shaping but also generates a 6-bit digital output in the modulator. The proposed DNSQ efficiently extracts the quantization error in the time-domain from the NSIQ, and directly applies it to a gated ring oscillator (GRO) based quantizer, hence achieving a 2nd order of noise-shaping. By incorporating the DNSQ, the modulator can achieve 4th order noise-shaping only with a 2nd order loop filter. The proposed modulator was fabricated in a 0.13 µm CMOS process with an active area of 0.17 mm 2. It operates at 640 MHz and achieves a peak SNDR of 80.4 db in a 15 MHz bandwidth while consuming 11.4 mw from a 1.2 V power supply. 14

15 CHAPTER 1 INTRODUCTION 1.1 Motivation As wireless data usage has increased exponentially due to the dramatic growth of mobile Internet, Internet of things (IoT), and smart devices, 5G wireless network system has been triggered to investigate for technologies with higher data rates and lower latency with energy efficiency. As illustrated in Figure 1-1, 5G technology is expected to have a data rate of 10Gb/s by 2020 [1] while the bandwidth needs to be increased to more than 400 MHz [2]. Thus, the hardware in 5G is required to deal the higher bandwidth with a data rate of 10 Gb/s or more and increased spectral efficiency with lower power consumption and cost. Therefore, the design of analog to digital converters (ADCs), which is one of the critical building blocks in wireless system, needs to be extended to achieve both high resolution and wide bandwidth with minimal power consumption. Generation 5G Analog 1G voice Digital 2G (GSM) 1990 Mobility 9.6kb/s X 1 2.5G (GPRS) 100kb/s X 10 3G (UMTS) 3.5G (HSPA) Mb/s Multi-media 2Mb/s X 200 X 4k 4G (LTE) LTE-A Gb/s Voice and Data over IP 300Mb/s Gb/s X 30k X 100k Data Rate Increase Figure 1-1. Generations of wireless communications. 15

16 A suitable ADC architecture that satisfies these demands is the continuous-time (CT) delta-sigma modulator (DSM) with a multi-bit quantizer as DSMs benefit from oversampling and noise-shaping to enhance the signal-to-quantization noise ratio (SQNR). CT DSMs have become more favorable compared to discrete-time (DT) DSMs as they are more beneficial in terms of power efficiency and anti-alias filtering. Thus, recent researches have been focused on developing high-speed and high resolution CT DSMs as it involves reduction of power consumption and design complexity. Although CT DSMs are beneficial in terms of both power efficiency and anti-alias filtering, realizing a CT DSM introduces the challenge of pushing higher resolutions towards higher frequencies with low power consumption. In order to improve the signal-to-noiseand-distortion ratio (SNDR) performance of conventional CT DSMs with a given sampling frequency and bandwidth, the order of the DSM loop or the number of quantization levels should be increased. However, increasing either the order of the loop or the number of quantization levels comes with a steep price of increased power consumption and circuit complexity. Conventionally, flash-type quantizers have been used to generate multi-bit outputs, but due to the considerable power consumption, alternative ways have been proposed. Out of many different structures, noise-shaping quantizers have been actively proposed as an attractive method to improve the efficiency of the modulator. Compared to conventional flash-type quantizers, an extra order of noise-shaping can be obtained with the noise-shaping quantizer instead of adding an integrator with an opamp in the loop filter, which increases circuit complexity and power consumption. Recently, the voltage controlled oscillator (VCO) based quantizer [3]-[5] and the noise-shaped 16

17 integrating quantizer (NSIQ) [6]-[8] as noise-shaping quantizers in DSMs have been proposed as an attractive solution to reduce the power consumption and increase the performance compared to traditional quantizers (such as a flash ADC). These noiseshaping quantizers provide an extra order of noise-shaping and will relax the loading effect of the loop filter (due to reduced input capacitance). However, the non-linearity of the VCO-based quantizer limits the performance of the DSMs such as the SNDR and the spurious-free dynamic range (SFDR). Thus, the DSMs employing the VCO-based quantizer require either linearization techniques or calibrations [9]-[12], which will increase power consumption and complexity. In contrast, the NSIQ-based quantizer is inherently linear by its nature, but suffers from a speed/resolution tradeoff. For instance, in a conventional NSIQ, a counting clock frequency of 2 N times the sampling frequency, fs, is needed to achieve N-bit quantization. Therefore, the maximum operating speed will be limited by the NSIQ s counting clock which is limited by technology, imposing a direct speed/resolution tradeoff. Another noise-shaping quantizer is a gated ring oscillator (GRO) based quantizer [13]-[18]. By operating as on and off states, the GRO-based quantizer is also inherently linear, but it requires a voltage-to-time conversion circuit in ADCs. However, all of these quantizers provide only a 1 st order of noise-shaping in the modulator. This dissertation addresses the above mentioned challenges to implement high performance CT DSM using a Gm-C based NSIQ followed by a digital back-end integrator. The dual-slope nature of the proposed Gm-C based NSIQ drastically reduces the linearity requirements of the Gm-C circuitry, which also serves as an active-adder summing the signals of the loop filter. In addition, the digital integrator at the back-end 17

18 of the loop [19] relieves the requirements of the speed and the number of quantization levels for the quantizer. With the aid of the bi-directional discharging scheme [6] (where the discharging direction is set by the signal s polarity) and digital integration in the loop, the Gm-C based NSIQ provides effective 4-bit quantization levels and an extra order of noise-shaping using only three counting clock edges and three corresponding latches. In addition, in order to further improve the performance of the modulator, a double noise-shaped quantizer (DNSQ) is proposed in this dissertation, which takes advantage of both the NSIQ and GRO-based quantizer. In the DNSQ, the quantization error, which is effectively extracted in the time domain from the NSIQ, is directly applied as an input to a GRO-based quantizer so that the DNSQ not only provides 2 nd order noise-shaping, but also generates a 6-bit digital output in the modulator. In the proposed CT DSM, the 1.5-bit quantization levels of the NSIQ are increased to 3-bit with the help of a digital integrator at the back-end of the modulator. The increased resolution of the NSIQ combined with an additional 3-bit from the GRO-based quantizer results in a 6-bit final output. Additionally, the impact of various non-idealities of the DNSQ in the modulator is analyzed and discussed in this dissertation. 1.2 Research Contribution Several contributions made in this dissertation to the study and implementation of CT DSMs are as follows: Development of a combination of a noise-shaped integrating quantizer (NSIQ) and digital integrator at back-end with analysis of the loop characteristics of the CT DSM to show significant advantages compared to conventional DSM using a flash quantizer. 18

19 Implementation of a Gm-C based NSIQ, which operates at higher frequency with lower power dissipation compared to active RC based NSIQ. Excess loop delay (ELD) compensation scheme that drives internal DACs from the NSIQ instead of DSM output. Implementation and measurement of the CT DSM employing the NSIQ and digital integrator to verify the concept and prove the efficiency of the CT DSM. Invention of a double noise-shaped quantizer (DNSQ) to improve further the efficiency of the CT DSM by generating 2 nd order noise-shaping with more number of quantization bits from the quantizer. Analysis of performance degradation due to non-idealities of the DNSQ, which are shaped by the loop filter in DSM. Implementation and measurement of the CT DSM employing the DNSQ to verify the concept and prove the efficiency of the CT DSM. 1.3 Dissertation Outline This dissertation is organized as follows. Chapter 2 introduces the concepts of a DSM. Chapter 3 overviews briefly about noise-shaping quantizers and a double noiseshaped quantizer is proposed in Chapter 4. Chapter 5 presents the proposed CT DSM architecture using a Gm-C based NSIQ and a digital back-end integrator. In Chapter 6, the proposed double noise-shaped quantizer is implemented in a continuous-time deltasigma modulator. Finally, Chapter 7 concludes the dissertation. 19

20 CHAPTER 2 FUNDAMENTALS OF DELTA-SIGMA MODULATOR Analog-to-digital converters (ADCs) are essential building blocks in most electronic systems and applications that processes the encoding of a continuous analog signal into a discrete and quantized signal. As illustrated in Figure 2-1, different ADC architectures are available depending on bandwidth and resolution requirements. Thus, each application needs a specific ADC architecture to achieve the best trade-off between the speed, resolution, and power consumption. DSMs belong to the family of oversampling converters and are suitable for high-resolution applications. Moreover, DSMs are closed feedback loop systems which tolerate analog non-idealities such as offset and mismatch to provide high-resolution with low cost analog building blocks. This chapter describes the fundamentals of ADCs and DSMs to help the understanding of the rest of the dissertation. The concepts of quantization, oversampling, and noiseshaping are introduced in Chapter 2. Speed Low-to-Medium Speed High Accuracy Resolution Oversampling Integrating (Dual-slope) Medium Speed Medium Accuracy Successive Approx. Algorithmic High Speed Low-to-Medium Accuracy Flash Pipelined Folding Time-interlevead Nyquist-rate Converter Figure 2-1. Types of analog-to-digital converters. 20

21 2.1 Oversampling ADC This section provides the necessary background of quantization and the concept of oversampling mechanism to understand the principle of DSM. V in ADC D out D out V in -V ref A q e V LSB /2 V ref V in -V LSB /2 B Figure 2-2. Characteristics of an analog-to-digital converter. A) ADC transfer curve, and B) quantization error Quantization Quantization is the process of converting an analog signal into a finite range of digital numbers. As an example, quantization of analog signals to a resolution of 3-bit is illustrated in Figure 2-2A. The ADC maps an analog input signal into the digital domain by rounding-up or down to the nearest step. Thus, quantization is a non-linear operation that introduces an error depending on how well the signal is approximated. The analog 21

22 input signal, Vin ranges from -Vref to +Vref, which provides a full-scale (FS) of 2Vref. The quantization step can thus e expressed as V LSB = FS = V ref 2 N 2 N 1, (2-1) where N denotes the number of quantization bit. Figure 2-2B depicts a model for an approximation of quantization error (qe) which is the difference between the input signal and digital output. The illustration shows that the behavior of the quantization error is somewhat dependent on the input signal. Nonetheless, the quantization error can be assumed to be uncorrelated with the input signal and approximated as an additive white-noise approximation if the input signal to the ADC behaves randomly and the quantization step is sufficiently small. With this assumption, the probability density function (PDF) of the quantization error is uniformly distributed between -VLSB/2 and VLSB/2 as shown in Figure 2-3A, and the power spectral density (PSD) of the quantization error is white as illustrated in Figure 2-3B. PDF 1/V LSB PSD V LSB 1 12 F S -V LSB /2 V LSB /2 A q e -F S /2 F S /2 F B Figure 2-3. Quantization error of ADC. A) Probability density function, and B) power spectral density of the quantization error. The performance of an ADC can be calculated by the maximum signal-toquantization-noise ratio (SQNR). This SQNR is obtained by dividing the power of a 22

23 sinusoidal input signal by the power of the quantization noise. The power of the quantization noise can be calculated from the uniform PDF shown in Figure 2-3B as P qe = +V LSB /2 q 2 e dq 1 V LSB V LSB /2 = V LSB 2 12, (2-2) Whereas the signal power is given by P sig = 1 T A T sig 2 sin (wt) 2 dt 0 = A sig 2 2, (2-3) where Asig denotes the amplitude of the input signal. Thus, with a full-scale sine wave input signal (Asig = FS/2 = Vref), the maximum SQNR can be SQNR = (FS/2) 2 2 ( FS 2 N)2 12 = N A sig 2 2, (2-4) Representing equation (2-4) in db, SQRN db = 10log(SQNR) = 6.02N , (2-5) Thus, each doubling of the number of bit gives 6 db improvement Oversampling As seen in equation (2-5), the SQNR performance is limited by the number of bit, N. One way to improve the performance more is to operate the ADC with a higher sampling frequency than the Nyquist rate, F S > 2 F B, (2-6) where FS and FB denotes the sampling frequency and the desired bandwidth, respectively. This technique, which is called oversampling spreads out the total power of quantization noise hence reducing the power of quantization noise within the desired bandwidth as illustrated in Figure

24 PSD Nyquist-rate Oversampling F B F S /2 F Figure 2-4. PSD of the quantization noise for oversampling technique. In order to calculate the SQNR improvement by the oversampling technique, a parameter of frequency ratio, called over-sampling ratio, OSR, is defined as OSR = F S 2 F B. (2-7) Thus, with the use of oversampling, the power of the quantization noise within the interested bandwidth becomes only a fraction of the total noise, F B P osr = 1 P F qe df = 1 S F B OSR V LSB (2-8) Using equation (2-8) and the full-scale of input signal, the SQNR of an N-bit oversampling ADC with an OSR is calculated in db as SQNR OSR_dB = 6.02N log(OSR). (2-9) This equation (2-9) shows the advantage of using oversampling where SQNR is improved by 3 db for every doubling of the OSR. 2.2 Delta-Sigma Modulator Basics This section provides the concept and operation of quantization noise-shaping and the differences between discrete-time and continuous-time DSMs. 24

25 2.2.1 Noise-shaping In Chapter 2.1, oversampling technique is used to improve the SQNR performance. However, a limit exists in increasing the speed or sampling frequency. Moreover, the improvement of SQNR is only at a rate of 3 db by doubling the OSR. In this section, to further improve the SQNR performance, a noise-shaping technique is explained. Noise-shaping enables to shape the spectral density such that most of the quantization noise power is outside of the desired signal bandwidth. A DSM is the system which performs noise-shaping without affecting the signal bandwidth. q e X z -1 1-z -1 Integrator Q ADC Y Figure 2-5. First-order DSM. Figure 2-5 shows a DSM that shapes the quantization noise with a first-order high-pass transfer function. It consists of an integrator, an ADC as a quantizer, and digital-to-analog converter (DAC) in a negative feedback loop system. The operation of the DSM can be understood in terms of its frequency domain representation. It is worth noting that the quantization error is assumed to be uniformly distributed, and independent on the input signal (X) so that the modeling of the modulator is linear and easy to analyze. 25

26 With the transfer function of the integrator in the loop, H(z) = z 1 1 z 1. (2-10) the signal transfer function, STF(z), becomes STF(z) = Y(z) X(z) = H(z) 1+H(z) = z 1, (2-11) which corresponds to a single clock delay. Thus, the output (Y) of the DSM is same as the input (x) with a delay. Whereas the noise transfer function, NTF(z) is given by NTF(z) = Y(z) q e (z) = 1 1+H(z) = 1 z 1. (2-12) The equation (2-12) clearly shows the quantization error is shaped a first-order highpass shaped. This first-order noise-shaping is associated with the order of the loop filter. To calculate the SQNR performance, the squared magnitudes of these transfer functions are necessary. The squared magnitude of STF is STF 2 = z 1 2 = 1, (2-13) and the squared magnitude of NTF is given by NTF 2 = 1 z 1 2 = 1 e jw 2 = (2sin ( w 2 ))2, (2-14) where w = 2πF/FS (normalized frequency) with z = e -jw. The magnitude of the noise transfer function is illustrated in Figure 2-6 and in-band quantization noise power is shaped as seen in Figure

27 2 NTF π ω Figure 2-6. Magnitude of noise transfer function of a first-order DSM. Now, the power of in-band quantization noise including the NTF is given by P qe_1st = 1 π w B 0 P qe NTF 2 dω = V LSB π/osr 12π 0 (2sin (w 2 ))2 dω. (2-15) Assuming large OSR (OSR >>1), 2sin(w/2) ~ w in equation (2-15) can be approximated in the interested signal band. Thus, the power of the in-band quantization noise can be represented as P qe_1st P qe 2 π 2 3OSR 3 = V 2 LSB 36 π 2 OSR 3. (2-16) This equation (2-16) results in the calculation of SQNR as SQNR 1st_dB = 6.02N log(osr) 10 log( π2 3 ). (2-17) This equation (2-17) clearly shows the improvement of SQNR with OSR at a rate 9 db by doubling the OSR so that a higher effective number of bits (ENOB) can be achieved. To improve the SQNR performance more, a 2 nd order noise-shaping can be obtained with a 2 nd order of loop filter. Figure 2-7 illustrates an example of a second- 27

28 order DSM that shapes the in-band quantization noise by 2 nd order. Straightforward analysis of Figure 2-7 shows that STF(z) = z 1, NTF(z) = (1 z 1 ) 2. (2-18) With a similar analysis as the first-order modulator, the in-band quantization noise power can be represented by P qe_2nd P qe 2 π 4 = V 2 LSB π 4 5OSR 5 60 OSR 5. (2-19) This quantization noise results in the SQNR of the 2 nd order modulator given by SQNR 2nd_dB = 6.02N log(osr) 10 log( π4 5 ). (2-20) Therefore, doubling the OSR increases the SQNR by 15 db compared to 9 db in the first-order modulator. q e X 1 1-z -1 Integrator1 z -1 1-z -1 Integrator2 Q ADC Y Figure 2-7. An example of a second-order DSM. expressed as As a results, the SQNR performance can be improved by a higher-order NTF NTF(z) = (1 z 1 ) L, (2-21) 28

29 where L denotes the order of the NTF. This higher-order NTF can be obtained by increasing the number of loop filter order. The in-band quantization noise power with the order of L can be represented as P qe_l V LSB 2 12 π 2L (2L+1) OSR(2L+1). (2-22) Using this equation (2-22), a general SQNR with the NTF order of L can be expressed by SQNR L_dB = 6.02N (20L + 10) log(osr) 10 log( π2l (2L+1) ). (2-23) Thus, doubling the OSR increases the SQNR by 6L+3 db. This theoretical SQNR of a DSM versus OSR with different order of NTF (L) is tableted in Table 2-1 with an 1-bit quantization level. Table 2-1. SQNR (db) with 1-bit quantization vs. OSR with different order of NTF (L). Order OSR = 2 OSR = 4 OSR = 8 OSR = 16 OSR = 32 OSR = 64 L = L = L = L = L = L =

30 2.2.2 Multi-bit Quantizer In Chapter 2.2.1, only single-bit quantization is discussed. The single-bit quantizer is widely used due to its inherent linear characteristic with simple design methodology. However, in high-resolution applications, a multi-bit quantizer may be often used to lower the total quantization noise power. Thus, increasing the number of quantization levels directly improves the SQNR performance of the modulator as seen in equation (2-23). The calculated SQNR with 2-bit and 4-bit quantization levels versus the OSR with different order of NTF are shown in Figure 2-8 and 2-9, respectively. Also, the multi-bit quantizer alleviates the stability issue in higher (more than 3 rd order) order modulator by lowering the quantization steps, hence achieving aggressive noiseshaping. 160 L=6 L=5 L=4 140 L=3 SQNR (db) L=2 L= OSR Figure 2-8. SQNR (db) with 2-bit quantization vs. OSR with different order of NTF (L). 30

31 L=6 L=5 L=4 L=3 120 L=2 SQNR (db) L= OSR Figure 2-9. SQNR (db) with 4-bit quantization vs. OSR with different order of NTF (L). However, the DSM utilizing the multi-bit quantizer suffers from a non-linearity of the feedback DAC due to mismatch among its unit element. The non-linearity of the DAC is directly added to the input of the modulator and the output reflects the nonlinearity. Thus, it requires calibration scheme [20]-[26] or dynamic element matching (DEM) [27]- [33] to compensate the non-linearity and improve SFDR performance Discrete-Time Vs. Continuous-Time DSMs The above discussion in Chapter 2 is based on discrete-time (DT) DSM architectures, which are implemented with switched-capacitor schemes. Figure 2-10 illustrates the examples of continuous-time (CT) DSMs implementations. It utilizes the RC active integrators with opamps in the loop. Compared to DT DSMs which requires 31

32 the unit-gain bandwidth (UGBW) of the opamps to be 3~4 times higher than the sampling clock frequency, the requirement for the UGBW of the opamps in CT DSMs is often relaxed since the opamps in CT DSMs process the continuously changing signals. Thus, the power consumption of the opamp in CT DSMs can be significantly reduced compared to the DT DSMs. C 1 X R 1 - Y Q + DAC1 A C 1 C 2 X R 1 R Y + Q + DAC2 DAC1 B C 1 C 2 C L X R 1 R 2 R L Y + Q + + DACL DAC2 DAC1 C Figure Examples of CT DSM architecture implementations. A) the first-order DSM, B) the second-order DSM, and C) a higher order of DSM. 32

33 In addition, the anti-aliasing filter, which consumes a considerable amount of power is often required before the DT DSM to suppress signals around multiples of the sampling clock frequency. Whereas for the CT DSM, the requirement for the antialiasing filter can be relaxed or even eliminated since CT DSM provides inherent antialiasing characteristic. However, CT DSMs are more sensitive to the sampling clock jitter due to the relatively large charge error caused by the clock jitter compared to DT counterpart. This clock jitter effect can be alleviated by using a multi-bit quantizer with multi-bit DACs. Also, CT DSMs require RC time-constant tuning schemes to have the modulator stable without SQNR degradation due to PVT variations effecting the values of resistors and capacitors in the integrators. V DD M5 M3 Vbp M4 M6 C m C m Vo+ Vi+ M1 M2 Vi- Vo- C L C L I2 I1 I2 Figure An example of a two-stage Opamp with miller compensation. 33

34 2.2.4 Opamp Power Consumption In DSMs The opamp is an essential building block for loop filters in both CT and DT DSMs, and the power consumption of the opamp can be a critical factor to degrade the efficiency of the DSM. Thus, the analysis of the opamp is investigated in this subsection. Figure 2-11 illustrates the typical two-stage opamp with a miller compensation, which is widely used in DSMs and many systems. The power dissipation of the opamp is determined by current consumptions of I1 and I2 with a given power supply voltage (VDD). To estimate the currents I1 and I2 with proper DC biases and stability, we can use an equation for a given UGBW for the first-stage of the opamp of UGBW = g m1 2πC m, (2-24) where gm1 is the transconductance of the input transistor, M1, and Cm denotes the capacitor for miller compensation. With the transconductance, g m1 = 2I D1 (V gs1 V th1 ) = I1 (V gs1 V th1 ), (2-25) where Vgs1 and Vth1 are the gate-source voltage and threshold voltage of M1, respectively, the current I1 can be represented by I1 = UGBW 2π C m (V gs1 V th1 ). (2-26) To avoid the dominant pole by the load capacitor (CL), the output-stage requires at least three times higher UGBW [34] as 3 UGBW = g m5 2π(C m +C L ). (2-27) Then, the current of the output stage, I2, can be represented by I2 = 3 UGBW π (C m + C L ) (V gs5 V th5 ). (2-28) 34

35 Assuming the same overdrive voltages, (Vgs - Vth), for all transistors, the total current of the opamp can be expressed as I total = I1 + 2 I2 = UGBW π (8C m + 6C L ) (V gs V th ). (2-29) This equation (2-29) clearly shows that the power dissipation is directly proportional to UGBW, and CL. CL can be determined by the coefficients of the integrators in the DSM loop, but it has to be large enough to avoid the dominant noise by the capacitor, (kt/c). This indicates that we cannot reduce the power dissipation using low load capacitance. To make it worse, the UGBW in DT DSMs need to be 3~4 times higher than the sampling clock frequency as mentioned in Chapter Thus, the power consumption of the opamp will increase significantly depending on the sampling clock frequency. As a result, the efficiency of DSMs is limited by the tradeoff between the power consumption and the overall performance: increasing the order of loop filter will increase the required number of opamps and the overall power consumption. An alternative approach is to employ a noise-shaping quantizer instead of a flash ADC quantizer in a DSM. The noise-shaping quantizer will provide an extra order of noise-shaping which results in removing an opamp for a given number of order in DSMs. Therefore, the efficiency of the DSMs can be significantly improved with a noise-shaping quantizer, which is explained in detail in Chapter 3. 35

36 CHAPTER 3 OVERVIEW OF NOISE-SHAPING QUANTIZERS Noise-shaping quantizers such as NSIQs and VCO-based quantizers have become a topic of great interest due to the extra order of noise-shaping in DSMs. This chapter describes the basic operations of noise-shaping quantizers, and reviews their advantages and disadvantages. X ɸ S R C V DS ɸ D V REF D out ɸ discha. Modified Timing control logic & Counter ɸ count A -V DS ɸ S ɸ D ɸ S X(n) - q e (n-1) -q e (n-1) Sampling/ Windowing D out ɸ discha. Discharging /Counting B D out t -q e (n) t t available Figure 3-1. The simplified noise-shaped integrating quantizer. A) The simplified block diagram of the NSIQ using an active RC integrator, and B) The timing diagram of the NSIQ assuming counting occurs at both rising and falling edges of the counting clock. 36

37 3.1 Noise-Shaped Integrating Quantizer The traditional dual-slope ADC can be modified to provide first order quantization noise shaping as illustrated in Figure 3-1A. In the traditional dual-slope ADC, the input signal is sampled on the integrating capacitor during a sampling phase (ɸS), and the integrated signal is discharged during a discharging phase (ɸD). Meanwhile, the digital counter is incremented by a fast counting clock until the comparator detects the zerocrossing of the discharged voltage (VDS). The difference between the traditional dualslope ADC and the noise-shaped integrating quantizer is in the discharging phase. In the NSIQ, the discharging is terminated at the next edge of the counting clock after the zero-crossing as shown Figure 3-1B, and the reset phase of the traditional dual-slope ADC is eliminated. The value stored on the capacitor at the end of the discharging phase will be the quantization error of the current sample. During the discharging phase, the digital counter increments with a fast counting clock. The value stored in the digital counter at the end of the discharging phase is available at the beginning of the next sampling phase and has a delay of 0.5TS assuming that the discharging period is half of the sampling clock period. This digital output presents the quantized input with the differentiated quantization error, (1-z -1 ) qe(z), where qe(z) is the quantization error. In effect, this quantizer provides a first order of quantization noise shaping. Window Integ. q e X K I Dout s discharging feedback RZ z -1/2 ɸ D Figure 3-2. Conceptual modeling of the NSIQ. 37

38 The conceptual block diagram of the NSIQ is shown in Figure 3-2. The integrating (or time integral) characteristic using the switch at the front of the integrator (in Figure 3-1A) during the sampling phase can be modeled as a window block, whose transfer function can be expressed as H win (s) = e st s/2 sin (πft s/2) πft s /2 (3-1) where TS denotes the period of the sampling clock. Because of the feedback path and the RC time constant for the discharging characteristic (corresponding to a return-tozero in Figure 3-1A) in the NSIQ, its model looks similar to a first order CT DSM having a 1-bit output except for the windowing function. As a result, the signal transfer function (STF) of the NSIQ can be represented as H NSIQ (s) = e sts/2 sin (πft s/2) K I (3-2) πft s /2 s+ K I where KI represents the normalized gain (1/RC) of the integrator in Figure 3-1A. The low-pass response of Sinc function on the STF will add an anti-alias filtering effect in a DSM with the NSIQ compared to one with a conventional (flash type) quantizer. In this case of the NSIQ, the zeros of the STF occur at even multiples of the sampling frequency, FS (1/TS), as noted by equation (3-2). However, the undesired effects from the window such as the pole and the delay (e -sts/2 ) should be compensated for in the DSM loop in order to avoid any stability issues and performance degradation. In this dissertation, two separate DACs taken directly from the output of the quantizer (rather than the digital integrator) in the loop are implemented for the compensation of the window effect and the delay, and are discussed in more detail in Chapter 5. The bi-directional scheme enables the discharging in NSIQ to occur in both the positive and negative directions using different polarities of the reference voltage as 38

39 illustrated in Figure 3-3A. As shown in Figure 3-3B, the discharging is determined to be in either the positive or negative direction depending on the polarity of the input signal, which is detected at the beginning of the discharging phase. The polarity detection simply captures the MSB and reduces the speed of the counting clock by half. Also, this polarity detection plays an important role in the proposed quantizer with a bi-directional scheme, which is elaborated in Chapter 6. In addition to the extra order of noise-shaping, the NSIQ comes with several advantages over the flash type quantizers. The power consumption will be reduced significantly since a single comparator with only few logic gates will take the role of a multi-bit quantizer. Also, the quantization error can be extracted in both analog and time domains so that it can be extended to a cascade type modulator. In addition, the NSIQ can be improved further in advanced nodes (processes) in terms of its speed and power consumption since it is essentially operating in time domain. Despite many significant advantages, the speed of the counting clock is still a limiting factor for high-speed applications since the number of quantization levels is determined by the counting clock. For N-bit quantization, the frequency of the counting clock should be f c = 2 N f s (3-3) where fc, N, and fs are the frequency of the counting clock, the number of quantization levels, and the frequency of the sampling clock, respectively. Equation (3-3) shows the tradeoff between the speed of the counting clock and the resolution of the quantizer, which limits the overall performance of the DSM. In view of this drawback, we propose a 39

40 new DSM architecture that not only resolves this limitation, but also simplifies the internal DACs of the modulator. X ϕ S R C V DS +V REF -V REF Dir Dir Dout Timing & Polarity (Dir) Detection & Counter A ϕ count -V DS ϕ S ϕ D Sample Discharge ϕ S Sample ϕ D Discharge -q e (n-1) Detect Polarity -q e (n) -q e (n+1) Detect + Direction Polarity - Direction Counting clock B t Figure 3-3. Simplified bi-direction scheme of the noise-shaped integrating quantizer. A) simplified NSIQ block diagram with bi-directional scheme, and B) timing diagram of the NSIQ with discharging direction. 3.2 VCO-Based Quantizer The conceptual block diagram of a VCO-based quantizer is illustrated in Figure 3-4. The key idea is to count the number of oscillations within each period of a clock signal using a counter and a differentiator. If the VCO output edges and the clock edges are synchronized, the digital output can be represented as 40

41 D out (t) = F OSC(V in (t)) F CLK (3-4) where FOSC denotes the oscillation frequency as a function of input Vin(t) and FCLK represents the clock frequency. Thus, the VCO-based quantizer converts the analog input signal from voltage to frequency domain and generates a digital output which is proportional to the input signal. One interesting aspect of the VCO-based quantizer is its inherent ability to achieve 1 st order noise-shaping. In (3-4), the VCO output is assumed to be synchronized to the clock edges, resulting in no noise-shaping effect. However, in reality, the VCO is a free-running oscillator and will not align with the clock edges. So, the quantization error between the VCO output and the clock edges occurs every clock cycle as shown in Figure 3-4. Without resetting the VCO and the counter, the final output contains the difference between the previous and current quantization error, (1-z - 1 ) qe(z), hence exhibiting an inherent 1 st order noise-shaping property. V in Counter osc Diff. 1-z -1 D out CLK CLK V in osc CNT q e [n-1] -q e [n-1] q e [n] -q e [n] q e [n+1] D out Figure 3-4. Conceptual block diagram of a VCO based quantizer and timing diagram for 1 st order noise-shaping. 41

42 With a multi-phase ring oscillator, the counter can be eliminated and the differentiator can be replaced with XOR gates by taking each phase of the delay cell in the VCO [4][5]. The digital output of the VCO-based quantizer is a function of time difference between each delay cell instead of the oscillation frequency. Moreover, the digital output acts as a barrel-shifting algorithm and has an inherent dynamic element matching (DEM) effect so that the mismatch of the delay cells in the VCO will be 1 st order shaped. Also, the design of the VCO-based quantizer includes a highly digital implementation which can be further improved with technology scaling by reducing gate delays and power consumption. However, due to the non-linear voltage-to-frequency transfer characteristic, the VCO-based quantizer performance suffers from distortions that limit the performance of a DSM. Although this nonlinearity of the VCO-based quantizer can be suppressed by embedding it in a DSM loop, the realization of large loop gain at high frequencies makes it difficult for a DSM to achieve high linearity. Thus, the VCO-based quantizer requires calibration [9]-[12] or linearization [35]-[38] techniques to combat the nonlinearity in an open-loop, but this increases power dissipation and complexity in the digital circuit. Also, the oscillation frequency is not guaranteed over the PVT variations, thereby affecting the delays. 3.3 GRO-Based Quantizer The GRO-based quantizer is similar to a VCO-based quantizer. It counts the oscillator output and generates a digital output with a differentiator as illustrated in Figure 3-5. The main deviation from the VCO-based quantizer is that the GRO takes a time domain input instead of a voltage input. Conceptually, the GRO can be realized by 42

43 adding switches in series with a conventional ring oscillator to the power rails. Thus, it oscillates only when the switches are closed, and the oscillation phase is suspended in the off-state when the switches are open. In detail, the charge stored on the parasitic capacitors inside of the oscillator preserves the oscillation phase during the off-state. As a result, the GRO starts with the previous quantization error at the beginning of every clock cycle, and the quantization error occurred in the current cycle is transferred to the next clock cycle. This way, the GRO-based quantizer provides 1 st order noise-shaping. en GRO Counter Diff. T in osc 1-z -1 D out en CLK CLK V in osc CNT q e [n-1] -q e [n-1] q e [n] -q e[n] q e [n+1] D out Figure 3-5. Conceptual block diagram of a GRO-based quantizer and timing diagram for 1 st order of noise-shaping. In addition to the advantages of a VCO-based quantizer, the GRO-based quantizer has an inherently linear behavior by operating as on and off states. Once the 43

44 GRO is on, it oscillates at a certain frequency independent from the input amplitude, whereas the oscillation frequency of the VCO is dependent on the input amplitude. Such advantage allows the GRO-based quantizer to be linear without any calibration technique. However, a voltage to time conversion circuit is required to employ it in ADCs. In this dissertation, the voltage-to-time conversion is easily performed in the NSIQ which is explained in detail in Chapter 4. Other design considerations of the GRObased quantizer in practice include the dead-zone behavior [14] and leakage [39] during the off-state caused by circuit non-idealities. The dead-zone behavior is resolved in the proposed design by injecting a minimum pulse width into the input of the GRO while the effect of leakage is made negligible by the loop gain of the modulator due to its nature of shaping a quantizer s non-idealities in a DSM. 44

45 CHAPTER 4 PROPOSED DOUBLE NOISE-SHAPED QUANTIZER Quantizers are key building blocks in both continuous-time (CT) and discretetime (DT) delta-sigma modulators (DSMs). Among various types of quantizers, noiseshaping quantizers such as voltage-controlled oscillator (VCO) based quantizers and noise-shaped integrating quantizers (NSIQ) are attractive solutions by providing an additional order of quantization noise-shaping. On one hand, VCO based quantizers are relatively fast, but are often non-linear. On the other hand, the NSIQ suffers from a tradeoff between the counting clock speed and resolution, but can be very linear. Nevertheless, the NSIQ offers an interesting benefit that the quantization error is inherently available in both time and voltage domains. Thus, the NSIQ can be easily extended to provide an additional order of noise-shaping. In this dissertation, we propose a double noise-shaping quantizer (DNSQ) incorporating an NSIQ and a gated ring oscillator (GRO) based quantizer that not only provides 6-bit quantization levels effectively with a back-end digital integrator, but also offers two extra orders of noiseshaping. 4.1 Operational Principle Figure 4-1 illustrates the conceptual block diagram of the proposed DNSQ. The DNSQ consists of two noise-shaping quantizers, NSQ1 and NSQ2 shown in Figure 4-1. The first noise-shaping quantizer, NSQ1 converts the analog input signal (X) into the digital MSB output with first order noise-shaping, D1 = X + (1-z -1 ) qe1. (4-1) 45

46 Meanwhile the quantization error, qe1 of NSQ1 is extracted and fed to the second noiseshaping quantizer, NSQ2 so that the digital LSB output from NSQ2 becomes D2 = qe1 + (1-z -1 ) qe2. (4-2) The differentiation (1-z -1 ) of (4-2), is followed by a subtraction of (4-2) from (4-1) in digital domain so that qe1 is ideally canceled out and the final output contains only a 2 nd order shaped quantization error, qe2 from NSQ2, Dout = X (1-z -1 ) 2 qe2. (4-3) The main benefit of this architecture is to simultaneously provide both quantization and noise-shaping from both NSQ1 and NSQ2. (1-z -1 ) q e1 X NSQ1 D1 Dout q e1 NSQ2 D2 1-z -1 (1-z -1 ) q e2 Figure 4-1. Conceptual block diagram of the double noise-shaped quantizer. Generally, in multi-step quantizer such as this one, the main design challenge is how to extract the quantization error, qe1 from NSQ1 effectively. The conventional way 46

47 of extracting the quantization error is performed in the analog domain by subtracting the input signal X of the first quantizer from its output, which requires a DAC and a residue (or sample-and-hold) amplifier for the subtraction, or a multiplying-dac (MDAC) [40]- [42], which adds circuit complexity and requires additional power consumption. Moreover, the interstage gain mismatch and linearity of the DAC are critical limitations in achieving the desired performance. In the proposed quantizer, the quantization error is inherently extracted in the time domain without the necessity of using any DAC or amplifier as explained in the following Chapter NSIQ and GRO-Based Quantizer In the proposed DNSQ, the NSIQ operates as the first noise-shaping quantizer as shown in Figure 4-2A. As mentioned, the NSIQ provides quantization error in both the analog and time domains, and it can be easily extracted in the time domain. Utilizing this advantage, the quantization error in the time domain, qe_time is directly fed to a GRO-based quantizer, which functions as the second noise-shaping quantizer. As was described conceptually in Chapter 4.1, the quantization error from the NSIQ is canceled out in the digital domain, and the final output will have only the second order noiseshaped quantization error from the GRO based quantizer. This enables the proposed quantizer to act as a 2 nd order noise-shaping quantizer. The quantization error from the NSIQ is the time duration from the zero-crossing point to the next counting clock edge after the zero-crossing point as illustrated in Figure 4-2B. The zero-crossing point can be easily detected with a comparator. Hence, no additional DAC or amplifier is required in the proposed quantizer to extract the quantization error. Moreover, the GRO-based quantizer operates in a delay-free fashion 47

48 as the extraction of the quantization error starts immediately after the zero-crossing point, and at the same time the GRO starts shifting its phases. In other words, as soon as the NSIQ begins generating quantization error, the GRO-based quantizer processes the quantization error in a delay-free fashion. Thus, it eliminates the requirement of any sample-and-hold circuitry to create an additional delay in the modulator. X NSQ1 ɸ S R C V DS NSIQ -V DS ϕ S Charging ϕ D Discharging +V R -V R Dir Dir ɸ count en ɸ discha. q e_time Timing control & q e gen. GRO D1 Dout -q e1 (n-1) NSIQ Phases q e in time ϕ d1 ϕ d2 ɸ discha. q e_time -q e1 (n) NSQ2 XORs (1-z -1 ) GRO based Quantizer (1-z -1 ) D2 GRO Phases GRO enable t A B Figure 4-2. Architecture of the double-noise shaped quantizer. A) the proposed DNSQ, and B) timing diagram of the DNSQ. The proposed DNSQ may be considered as a counterpart of multi-stage noiseshaping (MASH) DSMs [43] due to the multi-step quantization and only the last stage quantization error appearing at the output with multi-order quantization noise-shaping. However, the DNSQ has several advantages over the MASH DSMs. In conventional MASH DSMs, each stage requires a loop filter and a quantizer with feedback DACs. Extra hardware for extraction of the quantization error such as a DAC and amplifier is 48

49 required as mentioned previously. On the other hand, each stage in the proposed DNSQ is a quantizer itself, providing noise-shaping without a loop filter. In addition, only a single comparator is required to extract the quantization error. These features allow for an easy integration of the DNSQ in DSM architectures in order to achieve high order of noise-shaping and aggressive quantization with minimal design complexity. Although the DNSQ is an attractive topology for a standalone oversampling ADC due to the SQNR provided by the 2 nd order noise-shaping, the standalone DNSQ is prone to leakage of the quantization error of NSQ1, similar to MASH modulators. This leakage can degrade the cancellation of qe1 at the final digital output and cause distortions. In this dissertation, the DNSQ is employed in a modulator with a 2 nd order loop filter so that the leakage of NSQ1 and any other non-idealities from the DNSQ are processed and shaped by the loop filter as discussed in more detail in Chapter Bi-Directional Scheme in the Double Noise-Shaped Quantizer A Gm-C based NSIQ with a bi-directional scheme is utilized for the proposed DNSQ as shown in Figure 4-3 (single-ended shown for simplicity). During the sampling phase (ɸS), the input signal is integrated on the integrating capacitor (Cgm) through the gm. At the beginning of the discharging phase (ɸD), the polarity of the voltage on Cgm is detected first, and a discharging voltage from a combination of a current source and a resistor is applied to the gm to discharge the capacitor in the desired direction while the control logic generates the discharging enable signal (ɸdis). At the first clock edge after the zero-crossing, the control logic terminates ɸdis to stop discharging by disconnecting the discharging voltage from the gm. Therefore, the quantization error is stored on Cgm. To preserve this quantization error, the input of the gm is shorted to common-mode 49

50 voltage (Vcm in Figure 4-3) after discharging until the next sampling phase. Together with the bi-directional discharging scheme, the Gm-C integrator, and the pre-amplifier with only 2 dynamic latches, 3 quantization levels (1.5-bit) are obtained with a 1 st order of noise-shaping. Vin ϕ S ϕ D ϕ dis Vcm ϕ D Rdis Bi-directional Gm-C based NSIQ gm C gm Vq Pre- amp ϕ dis Dir q e_time dir ϕ d1 ϕ d2 qe ϕ S ϕ D FFs & Control Logic D1 1.5-bit en GRO 1 en GRO 8 D Q clk gro[8] D Q gro[1] Polarity Polarity clk Bi-directional GRO-based Quantizer D2 3-bit Figure 4-3. Simplified schematic of the bi-directional DNSQ including the Gm-C based NSIQ and GRO-based quantizer. With the bi-directional scheme described in [6][44], the number of counting clock phases and related hardware of the NSIQ can be reduced by half hence minimizing control logic and power consumption in the proposed DNSQ. In contrast to a conventional NSIQ, the half LSB adjustment [6] is not utilized in the DNSQ since the quantization error from NSIQ is ideally canceled out at the output of the DNSQ and only 50

51 relatively small 2 nd order shaped quantization error from the GRO-based quantizer remains. NSIQ D NSIQ V in q e from NSIQ LSB (bi-directional) (mid-tread) V in -LSB q e_time in time LSB GRO Output Swapping output A V in V in en 8 GRO 2 1 clk clk gro[8] D Q gro[2] D Q gro[1] D Q Polarity (Dir) clk Pseudo- diff. out Bi-directional GRObased Quantizer B Control Logic Figure 4-4. The concept of bi-directional scheme for the double noise-shaped quantizer with the polarity of the quantization error. A) quantization error of bi-directional NSIQ in voltage and time domains, and output of GRO-based quantizer. B) Simplified schematic of the bi-directional GRO-based quantizer. As a result of removing half-lsb compensation, the quantization error of the NSIQ ranges either from 0 to LSB or from 0 to -LSB, depending on the detected polarity of the input signal as shown in Figure 4-4A. However, the quantization error in the time domain always takes a positive form. This means the quantization error fed from the NSIQ to GRO can only take a positive form, regardless of the polarity of the quantization error stored on the NSIQ, and hence creates a severe signal/polarity dependent error. To address this issue, the output of the pseudo-differential GRObased quantizer is swapped based on the NSIQ discharging polarity to effectively 51

52 present a negative quantization error as illustrated in Figure 4-4B. In this fashion, the negative quantization error from the NSIQ can be represented with the polarity detection at the output of the GRO-based quantizer. Therefore, the bi-directional scheme with the polarity detection in the proposed DNSQ not only enables the reduction of the number of counting clock phases, hardware, and power consumption, but also properly represents the negative quantization errors in the time domain. Since the discharging polarity is available at the beginning of the discharging phase, this action does not impose any critical timing path. 4.4 Minimization Of Gain Mismatch Between NSIQ and GRO-Based Quantizer Although the quantization error can be easily extracted in the time domain with only a comparator, the gain mismatch between the NSIQ and the GRO-based quantizer needs to be considered just like any other two-step quantizers [45]-[53]. To mitigate the gain mismatch effectively, a delay locked loop (DLL) is employed in the proposed DNSQ. All phases of the GRO should be equally spaced in the time duration corresponding to 1 LSB of the NSIQ, which is the time difference between the counting clock edges as illustrated in Figure 4-5. In this dissertation, in order to equally space the 8 phases of the 3-bit GRO-based quantizer between the counting clock edges, ɸd1 and ɸd2 are generated from the DLL with 12 delay cells, noting that the first quantization step in the bi-directional and mid-tread scheme should be equal to a half LSB. If delay cells of both the DLL and the GRO have the same propagation delay, the gain mismatch between the NSIQ and the GRO can be minimized. Thus, the identical delay cell shown in Figure 4-6A is utilized to match the propagation delays of both the DLL and the GRO 52

53 closely. Also, the GRO delay cells are biased by the same control voltage (Vctr) from the DLL as shown in Figure 4-6B. Such approach alleviates the gain mismatch between the NSIQ and GRO-based quantizer over all PVT variations. This gain mismatch effect in the modulator is analyzed further in Chapter 6. -V DS ϕ S Charging ϕ D Discharging NSIQ Phases ϕ d1 ϕ d2 12 Phases from VCDL in DLL d1 d4 d8 d12 q e = 1 NSIQ LSB GRO enable 8 Phases from GRO for NSIQ LSB t Figure 4-5. A timing diagram including phases of the DLL and GRO. It is worth noting that the NSIQ is intentionally designed to have only 1.5-bit quantization levels, although 12 phases of the DLL are available for the counting clock edges. Resolving only 1.5 bits in the NSIQ reduces the design burden of the NSIQ while more quantization levels are effectively obtained from the second quantizer with an additional order of noise-shaping. In other words, instead of adding 12 dynamic latches and complex digital logic with additional power consumption into the NSIQ, obtaining 3 53

54 bits from the GRO-based quantizer results in a more efficient quantizer with 2 nd order noise-shaping. Vin V ctr_p enb Vop Von Vip q e_time en GRO GRO-based Quantizer clk clk clk gro[8] D Q gro[2] D Q gro[1] D Q Dir Polarity Control Logic D2 3b en v ctr ϕ S ϕ D ϕ d1 ϕ d2 V ctr_n A F ref PFD CP DLL LF v ctr d1 d4 d12 12 Delay Cells B Figure 4-6. Simplified bi-directional GRO-based quantizer. A) delay cell for both DLL and GRO, and B) simplified block diagram for minimization of gain mismatch between GRO and NSIQ using a DLL. 4.5 Minimum Pulse Injection In the GRO-Based Quantizer Another design consideration is the case when the pulse width of the GRO input is too short. In the NSIQ, the quantization error in the time domain is generated from the zero-crossing point, detected by the comparator (comp. in Figure 4-7A) to the end of discharging period (ɸdis). It is critical that the generated pulse width provides enough time for the GRO to operate properly. However, if the zero-crossing occurs near to the clock edges or the zero-crossing and the clock edges are aligned together, the GRO input will be too short for proper operation. In the worst case, the pulse will look like a 54

55 glitch as shown in Figure 4-7B. Such condition can create a dead-zone or meta-stable behavior in the GRO. The corrupted GRO output due to the dead-zone or meta-stability will not only degrade the performance of the modulator, but can possibly cause instability in the modulator. -V DS ϕ S Charging ϕ D Discharging -V DS ϕ S Charging ϕ D Discharging -V DS ϕ S Charging ϕ D Discharging ϕ d1 ϕ dis ϕ d2 ϕ d1 ϕ d2 ϕ dis ϕ d1 ϕ d2 ϕ dis comp. gro_en Typical case A t comp. gro_en Glitch B t ϕ dis_dly comp. gro_en C Min. pulse t Figure 4-7. Minimum pulse injection methodology. A) typical case of the GRO input having enough time to operate properly, B) case of too short pulse width or glitch occurred for the GRO input, and C) case of minimum pulse width generated for the GRO input. In order to avoid any dead-zone or meta-stable behavior in the GRO, a minimum pulse injection for the input of the GRO is proposed. The key idea is to generate the input of the GRO from the zero-crossing to a delayed version of the discharging period (ɸdis_dly) as illustrated in Figure 4-7C. With the minimum pulse injection, the dead-zone or meta-stable behavior will be avoided. This effectively acts as an added offset to the qe1 pulse, and while the added offset does not directly degrade SNDR, it will eat up the dynamic range of the GRO quantizer, if the offset is large. More importantly, since the qe1 pulse ideally varies from 0 to a full LSB, adding an offset might push this pulse to go 55

56 over full LSB in time domain, therefore shifting all the phases by 2π resulting in a complete cycle of the GRO. To eliminate this issue, it is crucial to make sure the added pulse is long enough to eliminate the glitch like behavior and short enough not to push the maximum quantization error larger than LSBNSIQ+LSBGRO (in time domain). In this design, the added pulse was less than LSBGRO/2 to ensure the above criteria are satisfied (two inverter delays). 56

57 CHAPTER 5 CONTINUOUS-TIME DELTA-SIGMA MODULATOR WITH NOISE-SHAPED INTEGRATING QUANTIZER AND DIGITAL INTEGRATOR In this dissertation, a Gm-C based NSIQ combined with a digital back-end integrator in the CT DSM loop is proposed to resolve the speed/resolution tradeoff of the conventional NSIQ. This chapter first explains the operation principle of the NSIQ with the digital back-end integrator and then analyzes the characteristics of the proposed CT DSM and the compensation of the window effects. X DAC1 4-bit a 1 s DAC2 4-bit a 2 s DAC3 4-bit a 3 s DAC4 4-bit Q 4-bit Quant. Y A z -1 X DAC1 4-bit a 1 s Q1 6-bit or higher Quant. Digital Filter ELD Q2 4-bit Truc. Y B z -1 X DAC1 4-bit NRZ a 1 s a 3 DAC2 2.5 bit RZ a 2 s DAC3 2.5 bit RZ 2.5 bit Noise- Shaped Quant. z -1/2 k q k q s 4-bit z -1 1-z -1 Digital Integ. Y C Figure 5-1. Block diagrams of continuous-time delta-sigma modulators. A) a conventional DSM, B) the hybrid DSM, and C) the proposed DSM. 57

58 5.1 Architecture Figure 5-1 illustrates three DSM architectures with 4-bit output. Compared to the conventional DSM shown in Figure 5-1A, a digital filter in the hybrid DSM [54][55] shown in Figure 5-1B increases the order of loop filter and replaces some portion of the analog circuitry (or analog filter). This hybrid DSM requires two quantizers: the first one for analog quantization (Q1) with high resolution and the other one for digital truncation (Q2) with low resolution. However, the performance of the hybrid DSM is mainly limited by low resolution of the digital truncation (Q2) although it utilizes a high resolution quantizer (Q1). The proposed DSM architecture shown in Figure 5-1C employs the noise-shaped quantizer in combination with a digital back-end integrator. In contrast to the hybrid DSM, the digital integrator in the proposed DSM does not increase the order of noiseshaping, but it relaxes the burden of the quantizer (NSIQ) by accumulating the quantizer output code without any truncation. Several aspects of the proposed architecture merit consideration. First, the DSM loop is capable of achieving 3 rd order noise-shaping with a 2 nd order analog loop filter compared to the conventional DSM because the noiseshaped quantizer provides an additional order of noise shaping. Second, the digital integrator at the back-end of the loop increases the number of quantization levels at the final output. In the proposed architecture, the digital integrator increases the 2.5-bit quantization to the 4-bit final output of the DSM. Thus, the increased number of output bits enhances the signal-to-noise ratio with improved stability. Third, the power consumption can be reduced significantly since the proposed architecture uses only two op-amps and the digital integrator relaxes the number of quantization levels of the quantizer, which is one of the most power hungry blocks [56][57]. 58

59 In addition, the linearity requirement of the quantizer is alleviated. In the traditional DSM architecture shown in Figure 5-2A, the quantizer has to process (or digitize) both the signal and the filtered quantization noise whereas the quantizer followed by the digital integrator in the proposed architecture only deals with differentiated signals (essentially high-pass filtered with respect to the sampling frequency) from the full-scale output as shown in Figure 5-2B. In other words, the digital integrator plays the role of accumulating the differentiated and quantized signals at the DSM s final output. The input to the quantizer is effectively the differentiated version of that of the traditional DSM. Therefore, the signal amplitude is suppressed, allowing for relaxed linearity requirement. V in LF1 Quantization Levels V Q 4b Q Dout A V in LF2 Quantization Levels V Q 2.5b Q 4b z -1 1-z -1 Dout Dig. Int. B Figure 5-2. Illustrations of the quantizer input signal amplitudes. A) the conventional DSM loop, and B) the proposed DSM loop. Another benefit of the proposed architecture is the reduced amount of hardware and number of levels for the internal DACs of the modulator. In the proposed structure, the internal DACs are operated by the output of the quantizer (before the digital 59

60 integrator) instead of the integrated output. Therefore, internal DACs (DAC2 and DAC3 in Figure 5-1C) use only 6 unit elements (2.5-bit). To sum up, the proposed architecture using the NSIQ in combination with the digital integrator yields the benefits of reduced power consumption, relaxed requirements of the linearity of the quantizer and number of quantization levels. 5.2 Characteristic and Stability Unlike the traditional DSM architecture shown in Figure 5-2A, where the quantizer has to process both the signal and the filtered quantization noise, the NSIQ in the proposed architecture processes mainly the filtered quantization noise with a significantly attenuated (or suppressed) input signal component as shown in Figure 5-2B. The input to the quantizer in a conventional DSM, shown in Figure 5-2A, is given by V Q_coventional = STF X + (NTF 1) q e (5-1) where STF and NTF represent the signal transfer function and the noise transfer function of the modulator, respectively. It can be noted that, if a large input signal (X) is applied to the DSM, the quantizer directly sees the large input since the STF is normally 1 in the signal bandwidth. Thus, the quantizer should cover the large input signal range with a large number of levels. Alternatively, in the proposed architecture with the NSIQ and digital backend integrator, the quantizer input is given by, V Q_proposed = STF (1 z 1 ) X + (NTF (1 z 1 ) 1) q e. (5-2) It is clear that the input signal is first order high-pass filtered. With the oversampling nature of DSMs, where the input signal bandwidth is much smaller than the sampling frequency, the high-pass filter attenuates the input signal at the input of the quantizer. 60

61 We can estimate the maximum amplitude of the input signal transition between two clock cycles (TS=1/fs) as follows X(t) X(t + T S ) t=0 = Asin(ω in t) Asin(ω in (t + T S )) t=0 = Asin ( 2πf in ) πa, (5-3) f s OSR if the over sampling ratio (OSR) is large. Equation (5-3) is approximation based on Taylor expansion of a Sine function for small fin/fs. Based on (5-2) and (5-3), the maximum amplitude of the filtered quantization error and differentiated input signal at the input of the quantizer will be Max (V Q_proposed ) (2 NTF max 1) LSB 2 + πa 2 OSR (5-4) where NTFmax is the maximum magnitude of the NTF (which for maximally flat NTFs occurs at fs/2). Note that the NTFmax represents the overall NTF which is the product of the NTF provided from the loop filter and the quantizer (NSIQ). This maximum amplitude at the input of the quantizer should be within the linear range of the quantizer to guarantee the stability of the modulator (sufficient but not a necessary condition) [58], (2 NTF Max 1) LSB 2 + πa 2 OSR < V linear (5-5) where Vlinear is the linear range of the quantizer. For the conventional DSM structure (with the STF of unity), in order for VQ to be within the linear range, the NTFmax should follow (NTF max 1) LSB 2 + A < V linear. (5-6) Comparing (5-5) and (5-6) provides interesting insight. While the VQ of the traditional and the proposed structures contains both the input signal and the filtered quantization error, in the traditional modulator, the input signal may dominate whereas in the proposed structure, the filtered quantization noise is the dominating factor. In other 61

62 words, if the input signal is zero, then the VQ of the proposed structure will be larger than the traditional modulators (noting the coefficient of NTFmax). However, as we increase the input signal amplitude, the VQ of the traditional modulators starts to increase at a much faster rate compared to the proposed structure. Therefore, the traditional modulator will saturate much faster than the proposed structure. The simulated maximum VQ versus input signal amplitude (with different frequencies) is shown in Figure 5-3A. For this simulation, OSR = 32, NTFmax = 2, and a 7-level quantizer (and 4-bit digital integrator) are used (these parameters are the same as the fabricated modulator). To show the worst case scenario, the frequency of the applied input signal is fs/2osr, which places the input signal at the edge of the signal band. Figure 5-3A validates the previous observation: the VQ of the proposed structure is drastically less dependent on the input signal compared to that of the traditional DSM. The histogram of the VQ for two different input signal amplitudes are provided in Figure 5-3B. It is evident that when the input signal is small (0.1Vref), the VQ of both structures are well within the reference range where VQ of the proposed modulator is comparable to that of the traditional DSM. However, if we apply a larger input signal (0.8Vref), the VQ of the conventional modulator increases while in the proposed structure it remains mostly unchanged. As such, in the proposed structure, since the VQ is always small, the extra levels of the quantizer can be removed. 62

63 1 V Q Amplitude F in = 10 Fs/(2 OSR) F in = 5 Fs/(2 OSR) F in = 2 Fs/(2 OSR) F in = 10 Fs/(2 OSR) F in = 1 Fs/(2 OSR) F in = 5 Fs/(2 OSR) F in = 0.2 Fs/(2 OSR) F in = 2 Fs/(2 OSR) F in = 1 Fs/(2 OSR) F in = 0.2 Fs/(2 OSR) V Q in the Conventional DSM V Q in the Proposed DSM Imput Amplitude A # of occurance Vin = 0.1 Vref Vin = 0.8 Vref Conventional Proposed V V Q Amplitude B V V Q Amplitude Figure 5-3. The amplitude comparison at the input of the quantizer as a function of the modulator input amplitude. A) comparison of the input amplitudes of quantizers (VQ), and B) histograms of the VQ for small input (left) and large input (right). 63

64 PSD (db) STF w. NSIQ V Q w. NSIQ STF w. Conv. V Q w. Conv Frequency (Hz) Figure 5-4. System-level simulation of the proposed CT DSM indicating STF and the input of the quantizer for two different cases: using the NSIQ and a conventional (flash type) quantizer. The STF of the modulator is designed carefully to avoid the high-pass filtering characteristic at the input of the quantizer, which otherwise causes the modulator to saturate at high frequencies. Extensive system-level simulations were performed to check the characteristics of the proposed CT DSM with the NSIQ and the digital integrator at back-end shown in Figure 5-1C. Figure 5-4 illustrates the simulation results of the STF and the transfer function of the input to the quantizer (VQ) for two different cases: using the NSIQ with the digital integrator and using a conventional (flash type) quantizer with the digital integrator in the loop [19]. Both STFs show the characteristic of a cascade of integrators in feedforward and feedback (CIFF-FB) which has roll-off at high frequencies with peaking at the out-of-band frequency [59]. The simulation result (with the coefficients of the realized loop filter) using the NSIQ with the digital integrator 64

65 indicates a peaking of about 4 db at 55 MHz with second-order roll-off while the STF of the modulator using the conventional quantizer with the digital integrator has a peaking of 4 db and first-order roll-off. This implies that the window sampling effect of the NSIQ increases the order of roll-off in the STF at high-frequencies. As expected, both the transfer functions of the input to the quantizer have a high-pass filtered characteristic up to 55 MHz. However, beyond 55 MHz, the input of quantizer using the NSIQ shows a first-order roll-off while the input of the quantizer using the conventional quantizer is flat. This is because the second-order low-pass response of the STF using the NSIQ cancels out the first-order high-pass filtering effect of (1-z -1 ) as per equation (5-2). This roll-off response of the input of the NSIQ at high-frequencies will prevent the quantizer from saturation due to unwanted interferers. 5.3 Excess Loop Delay and Pole Compensation While the proposed architecture using a digital integrator at the back-end of the loop bears resemblance to the conventional architectures, which employ digital processing at the back-end presented in [19][60]61], its topology is actually quite different with respect to the way it compensates the excess loop delay (ELD) and the window effects of the NSIQ. A conventional method of the ELD compensation is often implemented by taking the output of the modulator and feeding it back to the input of the quantizer with a DAC as illustrated in Figure 5-5A. Another approach is to take the output of the modulator and feed it back to the last integrator with a differentiation as shown in Figure 5-5B. The internal feedback DACs for the ELD compensation in both structures (Figs. 5-5A and B) require the same number of unit elements as that of the digital outputs. 65

66 X a 1 s a 3 a 2 s Q z -1 1-z -1 Y X a 1 s a 3 a 2 s Q z -1 Y 1-z -1 DAC2 DAC1 DAC2 DAC1 A 1-z -1 B X a 1 s a 3 a 2 s Q z -1 Y 1-z -1 X a 1 s a 3 a 2 s Q z -1 Y 1-z -1 DAC1 DAC2 RZ Y(1-z -1 ) z -1/2 DAC1 DAC2 RZ DAC3 RZ z -1/2 C D Figure 5-5. The ELD compensation topologies. A) the output of the digital integrator feed into the input of quantizer, B) the output of the digital integrator feeds into the input of the 2 nd integrator with a differentiation (1-z -1 ), which is equivalent to A, C) the output of the quantizer feeds into the 2 nd integrator, which is equivalent to B, and D) the proposed topology to compensate the ELD and the window effect of NSIQ. Unlike conventional DSMs with a regular quantizer where only one ELD compensation is required, there is an additional pole on top of the ELD in the proposed DSM that needs to be compensated for. As discussed in Chapter 3, the integrating characteristic of the NSIQ results in window sampling. This window effect will create an unexpected pole in the loop and may force the loop to be unstable. Therefore, the ELD and the pole of the NSIQ should be compensated properly for the modulator to be stable. It is worth noting that the ELD will affect the first sample of the impulse response [62], whereas the NSIQ pole will affect the second one. This is because the global DAC is updated one-delay after the quantizer sampling instance, making the global feedback 66

67 path skip the first sample and produce an impulse response starting from the second sample. Although the first sample of the impulse response corresponding to the ELD can be compensated, the second sample corresponding to the pole of the NSIQ will degrade the stability and performance of the modulator. Thus, two DACs are required to compensate both the ELD and NSIQ pole because the first and second samples of the impulse response are to be compensated. In the proposed architecture, DAC2 and DAC3 are used to compensate the ELD and NSIQ pole as shown in Figure 5-5D, and only the coefficients of these DACs are modified, therefore, no additional hardware is required. The operation of the two internal DACs is different compared to the one used for the global DAC1. DAC2 and DAC3 are driven directly by the quantizer, which carries the differentiated (1-z -1 ) version of the modulator output as shown in Figure 5-5C. In other word, applying an impulse (δ[n]) from the output of the modulator to DAC1 implies that a differentiated impulse (δ [n]= δ[n]- δ[n-1]) will be applied to DAC2 and DAC3 as shown in Figure 5-6. The path from DAC2 to the quantizer (DAC2-Q) contains one integrator, accumulating the impulse during the sampling period (ɸS). The response from DAC3 to the quantizer (DAC3-Q) has a positive value at the first sample and a negative value at the second one. Knowing that there is an integration (windowing effect) inside of the NSIQ, the final impulse response through DAC2 and DAC3 will be the integration of the responses from the two DAC paths (DAC2-Q and DAC3-Q). Thus, the first sample, associated with the ELD, can be compensated by a linear summation of the two paths, and the second sample, corresponding to the pole of the NSIQ, can be compensated by a subtraction of the two paths, which can be done using minimal hardware. 67

68 a 2 s DAC2-Q DAC3-Q δ' Q 1 1-z -1 δ DAC3 DAC2 z -1/2 ϕ D ϕ S ϕ D ϕ S ϕ D ϕ S δ[n] δ'[n] DAC2-Q DAC3-Q Figure 5-6. Impulse invariance transformation of the DAC2, DAC3 and the input of the quantizer. 5.4 Implementation of Main Building Blocks The schematic of the proposed 3 rd order CT DSM is shown in Figure 5-7. It incorporates a second-order active loop filter implemented using an opamp-rc integrator, a 2.5-bit Gm-C-based NSIQ, and a digital integrator. The circuit design details of the main building blocks in the modulator are described next. 68

69 C 1 R Z -1 R 3 Clock Gen. ϕ 1 X R 1 C 2 DAC1 - + NRZ 4bit R 2 DAC2 - + RZ 2.5bit R 4 DAC3 RZ 1 2 Q Noise- Shaped Quant bit UP/DN Accum. Digital Integrator Y 4 Figure 5-7. The simplified schematic of the proposed 3 rd order of CT DSM Gm-C Based NSIQ With the relaxed linearity requirement and reduced number of quantization levels offered by the digital integrator, a Gm-C integrator can operate at a higher speed with lower power consumption compared to a conventional active RC integrator. The NSIQ consists of a Gm-C integrator merged with a pre-amplifier followed by only 3 dynamic latches with control logic for 7 quantization levels via the bidirectional discharging scheme as shown in Figure 5-8A. In the sampling phase, the input signals from the loop filter and the DAC3 are summed through Gm1 and Gm2 onto Cgm. In the discharging phase, both Gm1 and Gm2 will be combined to create one equivalent Gm. The combination of a current source and a resistor (Rdis) effectively creates a reference voltage which sets the discharging slope. Intentionally, a classic/simple differential pair with resistive degeneration is used for the Gm cells (with the resistive common-mode feedback, Rg= 50 KΩ, and the capacitive load, Cgm = 200 ff) as shown in Figure 5-8B to 69

70 prove the efficiency and relaxed linearity requirements of the Gm-C based NSIQ in the loop. Vi1 D Qout DAC 3 Vi2 Discharging path R 3 R 4 R R ϕ S ϕ S ϕ D Vig1 Vig2 gm1 gm2 C gm Vq Pre- amp dir ϕ d1 ϕ d2 ϕ S ϕ D FFs & Control Logic D Qout R dis A ϕ dis Dir ϕ d3 C gm Vq- Vig1+ gm1 Rg Vig2+ Vig1- Rg gm2 C gm Vq+ Vq Vig2- ϕ S Charging Phases ϕ D Discharging 0.15ns 0.3ns 0.3ns ϕ d1 ϕ d2 ϕ d3 ϕ S q e (n) t t B ϕ dis C t Figure 5-8. The simplified architecture of the proposed noise-shaped integrating quantizer. A) the proposed Gm-C-based NSIQ structure, B) the schematic of the Gm-C, and C) a timing example of the quantizer. The timing of the quantizer is shown in Figure 5-8C. With the bi-directional and mid-tread quantization scheme, the time periods from the start of the discharging to ɸd1, ɸd2, and ɸd3, are 150ps, 450ps and 750ps, respectively. In this quantizer, the continuoustime comparator (for zero-crossing detection) is replaced by a low-power preamplifier and three dynamic latches. The discharging direction (polarity) is read at the beginning of the discharging phase. Three delayed versions of clock edges will trigger each dynamic latch 70

71 consecutively. If the zero crossing has occurred, the discharging will be terminated and the residue voltage will be stored in the output capacitor of the Gm-C (Cgm). The discharging stops as soon as one of the latches triggers. In contrast to the conventional active RC integrator based NSIQ, the charging and discharging on the node Vq on Cgm in Figure 5-8A is performed using the same slope. This results in a true dual-slope behavior. In addition, this quantizer not only provides a first order quantization noise shaping, but also serves as an active adder of the loop. Vq ϕ S ϕ D Charging Discharging ϕ S Charging Vq ϕ S ϕ D ϕ S ϕ d1 ϕ d2 ϕ d3 D Qout MSB Timing DAC2,3 (Polarity) Margin Active MSB = 1 à D Qout = or 0 à D Qout = A t ϕ d1 ϕ d2 ϕ d3 D Qout MSB Timing DAC2,3 (Polarity) Margin Active MSB = 1 à D Qout = or 0 à D Qout = B t Figure 5-9. Prediction of the quantizer digital output. A) the case of the zero-crossing occurring before the ɸd2, and B) the case of the zero-crossing occurring after the ɸd Quantization Prediction and Timing Another interesting property of the proposed system is that we can predict the quantizer output before the end of the discharging phase to allocate more time for the digital integrator. At the beginning of the discharging phase, the MSB (or direction) is read and then the discharging starts. If the second latch corresponding to the ɸd2 phase provides a 1 as shown in Figure 5-9A, it means that the zero-crossing has occurred 71

72 and the quantizer output is available. On the other hand, if the output of the latch corresponding to ɸd2 phase provides 0 as shown in Figure 5-9B, it implies that the discharging will continue and will result in the digital code of either full-scale or zero depending on the MSB (or direction). Either way, as soon as the latch corresponding to the phase ɸd2 triggers, we can predict the quantizer output code, and set the proper values for the internal DACs. It is worth noting that the comparator corresponding to the phase ɸd3 is still necessary to extract the quantization error of the last code (by terminating the discharging pulse), although the last code is predictable right after the ɸd2 phase. The timing is even more relaxed for the global DAC since the available time for the digital integration is from the ɸd2 to the end of the next sampling as shown in Figure Vq ϕ S ϕ D ϕ S ϕ D ϕ S t MSB (Polarity) ϕ d1 ϕ d2 ϕ d3 Timing Margin D Qout DAC2,3 Active D out t t Available Time for DAC1 and integrator DAC1 Active Figure The timing of the global DAC (DAC1). The global DAC has more time (half clock cycle) to operate than internal DACs (DAC2 and DAC3). 72

73 5.4.3 Loop Filter The first and second loop filters are realized using an active-rc integrator that eases the design of the feedback DAC with superior linearity and low noise. The opamp in the integrator is implemented using a three-stage fully differential amplifier shown in Figure 5-11 similar to the one presented in [63]. Two feed-forward compensation paths conserve the high gain bandwidth product of the opamp with minimized power consumption. In this opamp, the first and second stages have a self-biased commonmode feedback and the last stage uses an explicit common-mode amplifier. This kind of multi-stage opamp with feedforward compensation technique provides a high unity-gain bandwidth with low power consumption [64]. The simulations of the opamp using a 0.13 µm process have shown that it consumes 1.2 ma of current from a 1.2 V supply voltage and achieves a DC gain and a unity-gain bandwidth of 58 db and 2.4 GHz, respectively. Capacitor banks [65] with 30% tuning range were employed to compensate the RC process variation in the integrator. Vo+ Vovcm CMFB Vi+ A1 A2 A4 A3 Vi+ Vi+ A5 Vi- Vi- Vi- Figure The simplified 3-stage operational amplifier with feedforward. 73

74 5.4.4 Digital Integrator and Feedback Path Figure 5-12 shows a simplified block diagram of the digital integrator. A 16-bit thermometer-coded barrel-shift based up-down accumulator is implemented by control logic and a barrel shifter (using multiplexers, and D-flip-flop registers). Initially, the accumulator starts from the middle code which is represented by half 0s and half 1s. It will shift up or down corresponding to the input from the quantizer output. This scheme ensures that it consumes lower power than a full or half adder based accumulator especially operating at 640 MHz sampling frequency. Also, the adder does not overflow so that it does not require any overflow detection or protection. Din Up-Dn Shifting Control Logics Dctr D15_pre D14_pre D13_pre D12_pre D04_pre D03_pre D02_pre D01_pre D00_pre 1 1 D03_pre D02_pre D01_pre D00_pre Mux Mux Mux CLK FF FF FF Dout D15 D01 D00 Initial State D15= 0 D14= 0 D10= 0 D09= 0 D08= 0 D07= 1 D06= 1 D05= 1 D01= 1 D00= 1 Din = +2 Din = -3 D15= 0 D14= 0 D10= 0 D09= 1 D08= 1 D07= 1 D06= 1 D05= 1 D01= 1 D00= 1 D15= 0 D14= 0 D10= 0 D09= 0 D08= 0 D07= 0 D06= 1 D05= 1 D01= 1 D00= 1 Figure The simplified schematic of the digital integrator. 74

75 4-bit CK Digital Integrator Clock Gen. (VCDL) CK_D D Q Q D Q Q Rising/Falling Controllable Driver DAC unit (X) W 1 L 1 W 2 L 2 W 3 L 3 W 4 L 4 40u 5.8u 24u 2.2u 16u 2.2u 12u 5.8u M 1 M 2 M 3 M 4 DAC Out CK_Q (discharging) A CK_D DAC out B SNDR/SFDR (db) X/4 X/2 X 2X 4X DAC Unit Size C SFDR SNDR Figure The simplified scheme of the global DAC unit cell implementation, calibration, and SNDR effect. A) the simplified timing calibration scheme for DAC1 including the rising/falling controllable driver and DAC unit, B) the timing diagram of the calibration, which generates the clock for DAC (CK_D) considering the propagation delays of the flip-flop, the driver, and the DAC to align the DAC output and the clock of the quantizer (CK_Q), C) SNDR/SFDR vs. DAC unit size based on Monte-Carlo simulation results (σ). All the feedback DACs are cascoded current steering types to increase the output impedance and isolate it from glitches at the virtual node. The global DAC1 is 75

76 implemented using a non-return-to-zero (NRZ) topology to minimize the effect of clock jitter whereas the internal DACs (DAC2 and DAC3) are implemented using a return-tozero (RZ) topology for proper timing in the modulator. To minimize the inter-symbol interference (ISI) induced distortions, the timing calibration [66][67] for the global DAC1, which aligns the DAC1 output and the clock of the quantizer, is employed with a DAC driver controlling the rising and falling times as shown in Figure 5-13A and 5-13B. A Monte-Carlo simulation has been used for the global DAC1 to have more than 14-bit linearity [68] with σ = 0.124% and the DAC1 has been designed using a random walk layout strategy [69] to minimize the unit-element mismatch effect. Also, the SNDR and SFDR versus the DAC1 unit size (X) based on the mismatch variance (σ) have been simulated for the proposed architecture with the different DAC unit sizes as shown in Figure 5-13C. 5.5 Measurement Results The proposed CT DSM was fabricated in a 0.13 µm CMOS process with an active area of 0.08 mm 2. The die photograph is shown in Figure The small active area is a direct result of the reduced sizes of DAC2 and DAC3, and the reduced number of analog integrators (only two analog integrators). The modulator clocked at 640 MHz consumes 7.19 mw from a 1.2 V supply, of which 4.69 mw is drawn by the analog part, 1.01 mw by the digital circuitry, and 1.49 mw by the clock generation circuitry. This low power consumption shows the effectiveness of the proposed architecture with the Gm- C-based NSIQ and the digital integrator. 76

77 Figure Die microphotograph of the fabricated DSM. Figure 5-15 plots the measured 65k windowed FFT spectrum of the modulator output with a dbfs 1.9 MHz input sinewave at a sampling frequency of 640 MHz. It illustrates that the modulator achieves third order noise shaping. In a 10 MHz BW, the proposed DSM achieves a peak SNDR, SNR, and SFDR of 75.3 db, 75.5 db, and 94.1 db, respectively. The excellent SFDR of 94.1 db validates the claim that the linearity requirement of the quantizer is relaxed significantly. The measured SNR and SNDR as a function of the input amplitude are plotted in Figure The measured dynamic range is 78.5 db and the full-scale of the modulator is 1.2 Vp-p. 77

78 PSD (db) SNDR = 75.3 db SNR = 75.5 db SFDR = 94.1dB Frequency (Hz) Figure Measured 65k-samples FFT output spectrum. Figure 5-17 shows the measured STF and NTF of the modulator. An input signal of -6 dbfs was swept from 100KHz to 320 MHz to characterize the STF. Although the peaking in the STF from the system-level simulations discussed in this dissertation is 4 db, the measured STF shows peaking of only 0.8 db. This is because of the nonidealities of the NSIQ and opamp with a parasitic pole formed by the resistive dividers (R3, R4 and R in Figure 5-7 and Figure 5-8A) in front of the NSIQ, which sets the loop gains. Table 5-1 summarizes the measured performance and compares it with the state-of-the-art DSMs with similar BW and resolution. The proposed DSM achieves a Walden FOM (FOMWa = power/2 BW 2 ENOB ) of 75.9 fj/conversion-step and a Schreier FOM (FOMSch = (DR)dB + 10 log(bw/power)) of db. Only DSMs using highly 78

79 Magnitude (db) advanced nodes such as 40 nm and 28 nm processes have shown better FOMs than this work Figure Measured SNDR and SNR versus varying input signal amplitudes STF NTF Frequency (Hz) Figure Measured STF and NTF. 79

80 Table 5-1. Performance summary of the proposed CT DSM and comparison This Work [10] [45] [70] [71] Technology (nm) Supply (V) / / /1.4 fs (MHz) Bandwidth (MHz) DR (db) Peak SNDR (db) Peak SNR (db) Peak SFDR (db) Power (mw) Active Area (mm 2 ) FOMWa (fj/conv) FOMSch (db)

81 CHAPTER 6 CONTINUOUS-TIME DELTA-SIGMA MODULATOR WITH DOUBLE NOISE-SHAPED QUANTIZER In this section, the architecture and implementation of the CT DSM using the proposed DNSQ is described. Also, the design considerations and effects of the quantizer s non-idealities in the modulator are analyzed and discussed in more detail. 6.1 Architecture Generally, the requirement of any quantizer at the backend of the loop filter in DSMs is suppressed by the in-band gain of the loop filter. However, the input voltage to the quantizer, which is the sum of the input signal and the filtered quantization error can be relatively large, and depending on the NTF, can have a large signal component. To alleviate the quantizer from processing large input signals, we propose a DSM loop which employs the DNSQ followed by a digital integrator as illustrated in Figure 6-1A. In addition, as described in [44], a modulator with the combination of an NSIQ and a digital integrator benefits from several advantages, such as the effectively increased number of output bits and relaxed linearity requirement of the quantizer, given that digital integrator reduces the signal amplitude at the input of the quantizer. The loop shown in Figure 6-1A can be further simplified. That is, the noisecanceling filter (1-z -1 ) at the output of the GRO can be canceled out by the digital integrator and simply be replaced with a delay as illustrated in Figure 6-1B. This way, redundant digital blocks can be removed without changing the loop transfer function. In the realized architecture, the digital addition at the output is performed outside of the loop as shown in Figure 6-1C. Thus, the critical timing delay in the feedback path caused by the digital addition can be eliminated and the global DAC (DAC1) can be 81

82 relaxed to two 3-bit DACs [72]. In this design, a 2 nd order CT loop filter is employed and the digital integrator effectively increases the 1.5-bit quantization levels of the NSIQ to 3-bit, resulting in a 6-bit output with 3 bits from the GRO-based quantizer. The internal DACs (DAC2 and DAC3) are driven directly by the 1.5-bit NSIQ and 3-bit GRO-based quantizer instead of the 6-bit final output, reducing the size of the internal DACs. X LF NSIQ DNSQ k q k q s Dig. Integ. z -1 1-z -1 Y X LF DNSQ NSIQ k q k q s Dig. Integ. z -1 Y 1-z -1 GRO 1-z -1 GRO z -1 A B a 3 DNSQ Dig. Integ. X a 1 s a 2 s NSIQ k q k q s 1.5 z z -1 Y DAC1 3 3 NRZ RZ DAC2 RZ DAC3 1-z -1 3 GRO z -1 z -1/ C Figure 6-1. Simplified block diagrams of the proposed CT DSM architecture using the DNSQ. 6.2 Modulator Implementation Figure 6-2 illustrates the simplified schematic of the proposed modulator employing a 2 nd order CT loop filter with the DNSQ and a back-end digital integrator. A 82

83 single-ended implementation is shown for simplicity. The 2 nd order loop filter is realized using active-rc integrators which provide more linearity compared to a Gm-C integrator and a clean virtual ground to ease the feedback DAC design. Three-stage opamps with feedforward compensation are chosen to minimize the loop delay caused by the integrator [73]. An up/down accumulator with a barrel-shift algorithm is employed for the digital integrator. C 1 C 2 R 1 R 2 - X R 3 DLL/Clock Gen. NSIQ kq k q s 1.5 R 4 3 GRO ϕ 1 3-bit UP/DN Accum. z Y 3 DAC1 3+3b NRZ DAC b RZ DAC b RZ DNSQ z -1/2 1-z -1 Figure 6-2. Simplified schematic of the implemented CT DSM using the DNSQ. All the feedback DACs are cascode current steering types. Non-return-to-zero (NRZ) DAC pulse is implemented for the global DAC (DAC1), which consists of two equally sized 3-bit DACs. Although the GRO-based quantizer provides an inherent DEM effect, large-dimensioned transistors in the DAC unit are used for 14-bit matching because the DEM affects only one of the 3-bit (LSBs) DACs. The internal DACs (DAC2 and DAC3) are implemented using a return-to-zero (RZ) scheme, and driven by the 4.5- bit DNSQ output. The differentiation (1-z -1 ) in the internal feedback path of the GRO- 83

84 based quantizer output is performed with two separate DACs [64]. This avoids the need for extra logic in the digital domain which can increase power consumption and alter the loop delay. 6.3 Effect of Leakage from NSIQ In an ideal case, the output of the proposed CT DSM with the DNSQ shown in Figure 6-1 contains the input signal and the noised-shaped quantization error from only the GRO-based quantizer, Y = X STF qe2 NTFLF NTF1 NTF2, (6-1) where STF denotes the signal transfer function, and NTFLF, NTF1, and NTF2 denote the noise transfer functions provided by the loop filter, the NSIQ, and the GRO-based quantizer, respectively. However, in real situations, the quantization errors of both NSIQ and GRO are not completely preserved due to leakage. In this section, the leakage of the NSIQ and GRO and their effect on the overall performance is discussed. We categorize the source of the NSIQ leakage to two components: output swing of the gm and hold time (time duration that holds the quantization error). First, leakage due to the output swing is discussed. The NSIQ should hold the previous quantization error on the integrating capacitor. This is performed by shorting the differential inputs of the gm to the common-mode voltage. Since the differential input voltage is zero the differential output current is zero. However, because of the finite output resistance (Rout) of the gm, the VDS will create additional current, which charge or discharge the integrating capacitor. This is illustrated in more detail in Figure 6-3. The 5-transistor gm is used as an example as shown in Figure 6-3A for simplicity. When the discharging stops (rising edge of ɸd1 in Figure 6-3B), the differential inputs of the gm are connected 84

85 to VCM to generate zero differential current. However, at this moment assuming VO+>VO-, IO+ will discharge Cgm+ because VDS2>VDS4 and IO- will charge Cgm- because VDS3>VDS1. Therefore, the leakage is dependent on the output swing of the gm. Generally, a nonlinear leakage due to the output swing causes harmonic distortion because the swing of the gm in the stand-alone NSIQ is signal dependent. However, the swing of the interest is not the swing of the entire clock phase but only of when the discharging stops, in other words, the quantization error. Thus, the leakage due to the swing will mainly affect the noise floor rather than introducing harmonic distortion. Another source of the leakage is the code dependent hold time (thold) which is defined by the time difference of when the discharging stop time and the rising edge of the next sampling phase. Two situations are illustrated in Figure 6-3C with small and large inputs. The discharging stops at either ɸd1 or ɸd2 depending on the input amplitude. Assuming for simplicity that there is linear leakage current after the discharging stops, the voltage loss (VLEAK) due to the leakage current is directly dependent on the hold time (thold) as seen in Figure 6-3C. From the above discussions, the digital output of the stand-alone NSIQ including the leakage can be represented as D1 = X + (1 z 1 ) q e1 + V LEAK, (6-2) where V LEAK = I LEAK (z 1 q e1 ) t HOLD (z 1 D1) (6-3) which implies that the leakage is a function of the quantization error and the digital output of the NSIQ. Due to the output code dependency on thold, this leakage will mainly introduce harmonics, if the input to the quantizer has a large signal component. 85

86 However, in the proposed structure, the NSIQ mostly processes the filtered quantization error due to the use of the back-end digital integrator. Therefore, the harmonic distortion from the leakage will be mostly randomized and only result in increasing the noise floor. The 2 nd order loop filter further suppresses the leakage error as well. Figure 6-3. Behavioral diagram of leakages of the NSIQ. A) source of leakage, B) swing dependent leakage, C) NSIQ digital output dependent leakage, D) FFT results when Rout=100k and E) SNDR versus output resistance. 86

87 A comparison of the proposed DNSQ modulator with and without the digital backend integrator is simulated in Simulink to compare the effect of the NSIQ leakage. Figure 6-3D shows the FFT results of the two structures with the NSIQ leakage in equation (6-3). It shows that without the digital back-end integrator, the DNSQ modulator has harmonic distortions but is harmonic free with the addition of the digital back-end integrator as discussed above. Figure 6-3E shows the output resistance requirement of the gm. Based on equation (6-3), three cases are simulated: ILEAK dependency (dashed line), thold dependency (dotted line), and with both ILEAK and thold dependency (straight line). As seen in Figure 6-3E, thold dependent leakage causes the most significant performance drop due to added harmonic distortions, while ILEAK dependent leakage itself does not deteriorate the performance to such a degree. When both effects are simulated together, the leakage due to thold is randomized by the ILEAK dependent leakage. It can be seen that the output resistance requirement of the gm with the digital back-end integrator is much less than that without the digital back-end integrator. 6.4 Effect of Leakage from GRO-Based Quantizer In the proposed DNSQ, the GRO is enabled for only a small amount of time (qe1 of the NSIQ) and stays off for the remainder of the clock cycle. Therefore, the nonlinear leakage of the GRO is an important factor to analyze even though the GRO is placed at the back-end of the modulator. A timing diagram is provided in Figure 6-4A to describe this in more detail considering two different cases. In Figure 6-2, ɸd1 is placed at 1/3 of the discharging phase (ɸD) and ɸd2 is at the end of the discharging phase for the sake of simplicity. First, it is assumed that the input of the NSIQ is small (Case 1). The 87

88 discharging of the NSIQ stops at ɸd1, and at the same time the GRO is disabled (toff in Figure 6-4A). The GRO stays off until the zero-crossing of the next discharging phase (ɸD(2) in Figure 6-4A), which can happen at any time during this phase. In the second case, the input of the NSIQ is large which cause the discharging to stop after ɸd1 and the GRO to turn off at ɸd2. Similar to the previous case, the GRO will remain off until the zero-crossing of the next discharging phase. From this, we can divide toff into 3 portions: qe1 dependent time, always-off time (during sampling phase ɸS), and zero-crossing of the next discharging phase. It is important to note that the zero-crossing time is directly related to the input voltage of the NSIQ. Therefore, the zero-crossing can happen anywhere during ɸD(2) since the input of the NSIQ in the proposed loop mostly consists of the filtered quantization error. Assuming that the zero-crossing time has uniform probability density function (PDF) with a mean of Ts/4 (half of the discharging period), the toff in case 1 also has the same PDF with a mean of 13/12 Ts (by adding qe1 dependent time, always-off time, and mean of the PDF) while case 2 has the same PDF with a mean of 3/4 Ts (by adding always-off time and the mean of the PDF). The overall PDF toff can be obtained from the PDFs of case 1 and 2 which is shown in Figure 6-4B. 88

89 Figure 6-4. Behavioral diagram of GRO leakage. A) timing diagram, B) PDF of GROoff time (toff), C) effect of GRO leakage with worst case leakage of 50% LSB, and D) SNDR versus worst case leakage. 6.5 Effect of Gain Mismatch Between NSIQ and GRO-Based Quantizer Although the propagation delays of delay cells for both the GRO and DLL are matched closely as discussed in Chapter 6.4, gain mismatch between the NSIQ and the GRO-based quantizer may still be exhibited. To represent the effect of the gain mismatch, a fitting parameter (1+e gain ) is multiplied by qe1, causing the modulator output to be Y = X STF + NTF LF ( e gain ) (1 z 1 ) q e1 NTF LF (1 z 1 ) 2 q e2, (6-5) 89

90 where egain denotes the gain mismatch parameter. This gain mismatch degrades the performance by imperfect cancelation of the qe1 at the output of the modulator. However, in this case, the gain mismatch term with qe1 is third-order high-pass filtered by NTFLF (1-z -1 ). A behavioral simulation has been performed to check the effect of the gain mismatch. The simulation result in Figure 6-5 shows that the DSM loop minimizes SNDR degradation to less than 5 db due to a gain mismatch of ±10% between the NSIQ and the GRO-based quantizer which allows relatively relaxed matching between the GRO and DLL SNDR (db ) Gain Mismatch (%) Figure 6-5. SNDR performance vs. the gain mismatch between the NSIQ and the GRObased quantizer. 6.6 Measurement Results The CT DSM using the proposed double noise-shaped quantizer was fabricated in a 0.13 µm CMOS process with an active area of 0.17 mm 2. The die photograph is 90

91 shown in Figure 6-6. The modulator clocked at 640 MHz, consumes mw from a 1.2 V supply, of which 4.48 mw is drawn by the analog part, 3.63 mw by the digital circuitry, and 2.25 mw by the clock generation circuitry. This low power consumption shows the effectiveness of the proposed architecture combined with the DNSQ. Figure 6-6. Die microphotograph of the fabricated DSM. Figure 6-7 plots the measured 32k windowed FFT spectrum of the modulator output with a -1 dbfs 3 MHz input sine wave at a sampling frequency of 640 MHz. It illustrates that the modulator achieves 4 th order noise-shaping. In a 15 MHz BW, the proposed DSM achieves a peak SNDR, SNR, and SFDR of 80.4 db, 81.7 db, and 87.8 db, respectively. In Figure 6-8, two in-band sinusoidal input tones with -9 dbfs at 12.0 MHz and 12.5 MHz are applied and it shows the IMD3 and IMD2 of 85.5 db and

92 db, respectively. The measured SNR and SNDR as a function of the input amplitude are plotted in Figure 6-9. The measured dynamic range is 82.9 db and the full-scale of the modulator is 1.2 Vp-p. Figure 6-7. Measured 32k-samples FFT output spectrum. 92

93 Figure 6-8. Measured output spectrum with two input tones at 12 MHz and 12.5 MHz with -9 dbfs. Figure 6-9. Measured SNDR and SNR versus varying input signal amplitudes. 93