InAs Quantum-Well MOSFET for logic and microwave applications

Transcription

1 AWAD June 29 th 2012 Accelerating the next technology revolution InAs Quantum-Well MOSFET for logic and microwave applications T.-W. Kim, R. Hill, C. D. Young, D. Veksler, L. Morassi, S. Oktybrshky 1, J. Oh 2, C. Y. Kang, D.-H. Kim 3, J.A. del Alamo 4, C. Hobbs, P.D. Kirsch, and R. Jammy 1 CNSE, 2 Yonsei, 3 Teledyne, 4 MIT Copyright 2012 SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center and AMRC are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.

2 Outline Introduction Device design and process technology Device results from logic to microwave characteristics Conclusions Slide 2

3 Possible Logic Technology Roadmap Manufacturing Development Pathfinding Ge pmos; III-V nmos 2019 ULP TFET 2021 Ge pmos; Si nmos 2015 Ge CMOS 2017 Si FinFET nd Gen HKMG 2009 Gate stack HKMG 2007 Intel Intel, Intel Channel Material Defect Metrology Junctions Gate Stack Sub 60mV Architecture Junction / Doping Manufacturability 45nm 32nm 22nm 14nm 10nm 7nm 5nm Slide 3

4 Motivation for InAs vs. InGaAs <del Alamo, Nature 2012> <Kim, IEDM 2009> v inj (InAs>In 0.7 Ga 0.3 As/In 0.53 Ga 0.53 As) > 2v inj (Si) at less than half V DD Derived v inj values consistent with quasi ballistic transport (Collision-free) Slide 4

5 Layer structure with inverted Si δ-doping Inverted Si δ-doping Optimize Si δ-doping to better electrostatics Slide 5

6 Validation of epi quality in this work QMSA results from calibration structure K Electrons Mobility cm 2 /Vs µ n,hall = 11,200 cm 2 /V-sec and n s,ch = 1 x /cm 2 at 300K µ n,hall = 20,000 cm 2 /V-sec and n s,ch = 1 x /cm 2 at 77K Slide 6

7 Test Structure Design Unique features of this work: InAs channel for better transport Inverted Si δ-doping for low excess R SD and excellent electrostatic control 3 nm Al 2 O 3 /2 nm InP gate stack to improve D it Slide 7

8 InAs MOSFET Output Characteristics Optimized gate recess with L side < 5 nm Excellent I D saturation and pinch off behavior I D,sat = 0.68 A/mm at V DS = 0.6 V at L g = 100 nm Slide 8

9 R ON Characteristic R ON = Ohm-mm with optimized gate recess process (L side < 5 nm) R ON could be reduced with self-aligned architecture Slide 9

10 InAs MOSFET Subthreshold Characteristics SS = 105 mv/dec. at L g = 100 nm with D it = 4 x /ev.cm 2 Excellent gate leakage A room for EOT scaling below 2 nm Slide 10

11 V T roll-off V T was defined at I D = 1 µa/µm V T = 0.2 V at L g = 100 nm: Enhancement-mode operation Slide 11

12 InAs MOSFET g m Characteristic g m,int = C g x v inj g m = 1.73 ms/µm at V DS = 0.5 V ( A record g m,ext at L g = 100 nm) Slide 12

13 InAs MOSFET Microwave Characteristic Calibration: LRRM, De-embedding: OPEN/SHORT - L g = 100 nm: f T = 245 GHz & f max = 355 GHz at V DS = 0.8 V These f T & f max are record values for any III-V MOSFET Slide 13

14 InAs MOSFET promising for RF Applications - L g = 200 nm: f T > 200 GHz & f max = 300 GHz at V DS = 0.8 V - Excellent performance for millimeter wave applications Slide 14

15 III-V MOSFET Benchmarking [1] Open symbol: Surface channel Solid fill: Buried channel [10] [8] [9] [11] - A record transconductance at L g = 100 nm for III-V MOSFET Slide 15

16 III-V MOSFET Q Benchmarking - FOM Q factor defined as g m /S Q = 16 for L g = 100 nm and V DD =0.5 V. Slide 16

17 Extraction methodology for v inj Slide 17

18 C gi How to extract in small L g device Slide 18

19 Q I_xo How to extract - Extracted intrinsic gate capacitance (C gi ) & charge (Q i_xo ) in channel with S-parameter Slide 19

20 Benchmarking: Injection velocity (v inj ) 4 InAs HEMT n ~ 13,000 cm 2 /V-s 3 n ~ 9,500 cm 2 /V-s In 0.53 GaAs 2 1 *Strain-Si *Si nfets V DS = 0.5 V (V 0 DS = 1.1 ~ 1.3 V) L g [nm] - InAs MOSFET shows 2 X higher v inj than Si, even at V DS = 0.5 V - Consistent V inj depending on channel mobility Slide 20

21 Benchmarking: Injection velocity (v inj ) 4 InAs HEMT n ~ 13,000 cm 2 /V-s 3 n ~ 9,500 cm 2 /V-s In 0.53 GaAs 2 n ~ 11,200 cm 2 /V-s InAs QW MOSFET 1 *Strain-Si *Si nfets V DS = 0.5 V (V 0 DS = 1.1 ~ 1.3 V) L g [nm] - InAs MOSFET shows 2 X higher v inj than Si, even at V DS = 0.5 V - Consistent V inj depending on channel mobility Slide 21

22 Conclusions InAs (rather than In x Ga 1-x As) enables: Record g m =1.73 ms/µm at V DS = 0.5 V No significant I OFF penalty (S = 105 mv/dec) Excellent microwave characteristics f T = 245 GHz and f max = 355 GHz at L g = 100 nm 2 V inj improvement vs. s-si First rigorous v inj benchmarking shows InAs MOSFET competitive with best known HEMT InAs MOSFET (0.5V) InAs HEMT (0.5V) Strained Si MOSFET (1V) 2.3 x 10 7 cm/s 2.8 x 10 7 cm/s 1 x 10 7 cm/s Slide 22