TLE8080EM. 1 Overview. Engine Management IC for Small Engines. Features Supply 5V (+/-2%), 250 ma K-line transceiver (ISO 9141)

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1 1 Overview Feaures Supply 5V (+/-2%), 250 ma K-line ransceiver (ISO 9141) Serial Peripheral Inerface (SPI) 4 low side driver for inducive loads wih overemperaure and overcurren proecion and open load/shor o GND in off diagnosis: 2 low side swiches wih maximum operaion of 2.6A 2 low side swiches wih maximum operaion of 350mA 1 low side driver for resisive loads wih maximum operaion curren of 3A including overemperaure and overcurren proecion Configurable variable relucance sensor inerface Rese oupu and 5V undervolage deecion Wachdog Green Produc (RoHS complian) AEC Qualified Descripion The TLE8080EM is an engine managemen IC based on Infineon Smar Power Technology (SPT). I is proeced by embedded proecion funcions and inegraes a power supply, K-line, SPI, variable relucance sensor inerface and power sages o drive differen loads in an engine managemen sysem. I provides a compac and cos opimized soluion for engine managemen sysems. I is very suiable for one cylinder moorcycle engine managemen sysems. TLE8080-2EM and TLE8080-3EM TLE8080-2EM differs from he main version in parameers V5DD Rese Threshold for TLE8080-2EM and TLE8080-3EM and Power On Rese Delay Time for TLE8080-2EM in Chaper 5.4. TLE8080-3EM differs from he main version in parameer V5DD Rese Threshold for TLE8080-2EM and TLE8080-3EM in Chaper 5.4. Type Package Marking TLE8080EM PG-SSOP24 TLE8080EM TLE8080-2EM PG-SSOP24 TLE8080-2EM TLE8080-3EM PG-SSOP24 TLE8080-3EM Daa Shee 1 Rev

2 Table of Conens 1 Overview Block Diagram Pin Configuraion Pin Assignmen Pin Definiions and Funcions General Produc Characerisics V Supply, Rese and Supervision V Supply Power On Rese and Rese Oupu Wachdog Operaion Elecrical Characerisics 5V Supply, Rese and Supervision Power Sages Low Side Swiches Elecrical Characerisics Low Side Swiches Variable Relucance Sensor ( VRS ) Inerface Elecrical Characerisics VR Sensor Inerface Serial Peripheral Inerface (SPI) SPI Signal Descripion SPI Proocol SPI Regiser Se and Rese of Diagnosis Regiser Bis Elecrical Characerisics SPI K-Line K-Line Elecrical Characerisics K-Line Package Oulines Revision Hisory Daa Shee 2 Rev. 1.2

3 Block Diagram 2 Block Diagram VS 5V Volage Supply V5DD WD_DIS Undervolage Deecion CSN; SI; SO; SCLK 4 SPI Wachdog Rese NRO LS Driver inducive loads 350 ma OUT5 LS Driver inducive loads 350mA OUT4 IN3 LS Driver inducive loads 2.6A OUT3 LS Driver resisive loads 3A OUT2 IN1 LS Driver inducive loads 2.6A OUT1 VR_IN1; VR_IN2 2 VR Sensor VR_OUT RX; TX 2 K-Line KIO AGND PGND Figure 1 Block Diagram Daa Shee 3 Rev. 1.2

4 Pin Configuraion 3 Pin Configuraion 3.1 Pin Assignmen KIO 1 24 TX VS 2 23 RX OUT5 OUT4 OUT3 PGND OUT2 OUT PGND AGND V5DD NRO IN3 IN1 CSN PGND 9 16 SCLK VR_IN1 VR_IN2 WD_DIS SI SO VR_OUT Figure 2 Pin Configuraion Pg-ssop-24.vsd 3.2 Pin Definiions and Funcions Pin Symbol Funcion 1 KIO K-Line Bus Connecion 2 VS Baery Volage: Block o AGND direcly a he IC wih min. 100nF ceramic capacior 3 OUT5 Oupu Channel 5 4 OUT4 Oupu Channel 4 5 OUT3 Oupu Channel 3 6 PGND Power Ground: inernally conneced o pin 9, connec exernally o pin 9 7 OUT2 Oupu Channel 2 8 OUT1 Oupu Channel 1 9 PGND Power Ground: inernally conneced o pin 6, connec exernally o pin 6 10 VR_IN1 VR Sensor Inerface Inpu 1 11 VR_IN2 VR Sensor Inerface Inpu 2 12 WD_DIS Wachdog Disable: high acive; inernal pull down 13 VR_OUT VR Sensor Oupu 14 SO SPI Slave Oupu: high impedance 15 SI SPI Slave Inpu: inernal pull down 16 SCLK SPI Clock Inpu: inernal pull down 17 CSN SPI Chip Selec Inpu: low acive; inernal pull up 18 IN1 Conrol Inpu Channel 1: inernal pull down Daa Shee 4 Rev. 1.2

5 Pin Configuraion Pin Symbol Funcion 19 IN3 Conrol Inpu Channel 3: inernal pull down 20 NRO Rese Oupu: low acive, open drain 21 V5DD 5V Supply Oupu: conneced o exernal blocking capacior 22 AGND Analog Ground: conneced o sysem logic ground 23 RX K-Line Receive Oupu: logic oupu of daa received from he K-Line bus KIO 24 TX K-Line Transmi Inpu: logic level inpu for daa o be ransmied on he K-Line bus KIO; inernal pull up 25 Exposed Pad Subsrae Connecion: mus be conneced o PGND exernally on PCB Daa Shee 5 Rev. 1.2

6 General Produc Characerisics 4 General Produc Characerisics Table 1 Absolue Maximum Raings 1) T j = -40 C o +150 C: All volages wih respec o ground unless oherwise specified. Posiive curren flowing ino pin (unless oherwise specified) Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion Volages Supply Volage VS V VS V P_4.1.1 Supply Volage V5DD V V5DD V P_4.1.2 Inpu Volage on Pins IN1, IN3, V x V P_4.1.3 a SCLK, SI, WD_DIS Inpu Volage on Pins CSN, TX V x -0.3 V5DD V P_4.1.3 b +0.3V Inpu Volage VR_IN1, VR_IN2 V VR_IN1/ V see also and P_ DC Volage on Pins OUT1-5 V x V respec o PGND P_4.1.5 all channels are swiched off DC Volage on Pins VR_OUT, V x V I x < 1mA P_4.1.6 SO, RX, NRO DC Volage AGND o PGND V x V P_4.1.7 DC Volage on Pin KIO V KIO V respec o PGND P_4.1.8 KIO is swiched off Currens Inpu Curren beween VR_IN1 I VR_IN1,VR_IN2-50 ma P_4.2.1 and VR_IN2 Inpu Curren VR_IN1, VR_IN2 I VR_IN1/2,GND - 10 ma P_4.2.2 o GND Temperaures Juncion Temperaure T j o C P_4.3.1 Sorage Temperaure T sg o C P_4.3.2 ESD Suscepibiliy ESD Resisiviy all Pins o GND V ESD -2 2 kv HBM 2) P_4.4.1 ESD Resisiviy all Pins o GND V ESD V CDM 3) P_4.4.2 ESD Resisiviy Pin 1, 12, 13, 24 (corner pins) o GND V ESD1,19,20, V CDM 3) P_ ) No subjec o producion es, specified by design. 2) ESD suscepibiliy, HBM according o EIA/JESD 22-A114B. 3) ESD suscepibiliy, Charged Device Model CDM EIA/JESD22-C101 or ESDA STM Daa Shee 6 Rev. 1.2

7 General Produc Characerisics Noes 1. Sresses above he ones lised here may cause permanen damage o he device. Exposure o absolue maximum raing condiions for exended periods may affec device reliabiliy. 2. Inegraed proecion funcions are designed o preven IC desrucion under faul condiions described in he daa shee. Faul condiions are considered as ouside normal operaing range. Proecion funcions are no designed for coninuous repeiive operaion. Table 2 Funcional Range Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion Supply Volage V S 6 18 V P_4.5.1 Juncion Temperaure T j o C P_4.5.2 Noe: Wihin he funcional range he IC operaes as described in he circui descripion. The elecrical characerisics are specified wihin he condiions given in he relaed elecrical characerisics able. Table 3 Thermal Resisance Parameer Symbol Values Uni Noe or Tes Condiion Number Min. Typ. Max. Juncion o Case RhJC 7 K/W 1) P_4.6.1 Juncion o Ambien RhJA 29 K/W 1) 2) P_ ) No subjec o producion es, specified by design. 2) Specified R hja value is according o Jedec JESD51-2,-5,-7 a naural convecion on FR4 2s2p board; The Produc (Chip+Package) was simulaed on a 76.2 x x 1.5 mm board wih 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu). Where applicable a hermal via array under he exposed pad conaced he firs inner copper layer. Daa Shee 7 Rev. 1.2

8 5V Supply, Rese and Supervision 5 5V Supply, Rese and Supervision 5.1 5V Supply The TLE8080EM inegraes a volage regulaor for load currens up o 250mA. The inpu volage a VS is regulaed o 5V on V5DD wih a precision of ±2%. The design allows o achieve sable operaion even wih ceramic oupu capaciors down o 470nF. I is proeced agains overload, shor circui, and over emperaure condiions. For low drop operaion, a charge pump is implemened. VS Vref + I VS - V5DD I V5DD e.g. µc Figure 3 5V Supply 5.2 Power On Rese and Rese Oupu The rese oupu NRO is an open drain oupu. When he level of V V5DD reaches he rese hreshold (V RT ) (increasing volage V V5DD ) he signal a NRO remains low for he power-up rese delay ime ( RD ). The rese funcion and iming is illusraed in Figure 4. The rese reacion ime ( RR ) avoids wrong riggering caused by shor gliches on he V5DD-line. In case of V5DD power down (decreasing volage; V V5DD < V RT for < RR ) a logic low signal is generaed a he pin NRO o rese an exernal micro conroller. The level of he rese hreshold for increasing V V5DD is for he hyseresis (V RH ) higher han he level for decreasing V V5DD. Wih an acive rese all power sages and he K-Line oupu are disabled and SPI commands are ignored. Daa Shee 8 Rev. 1.2

9 5V Supply, Rese and Supervision Vs V V5DD < RR V RT V NRO RD RR RR RD V NRO_H V NRO_L Figure 4 Rese Timing Diagram 5.3 Wachdog Operaion The TLE8080EM inegraes a wachdog funcion which moniors he correc SPI communicaion wih he micro conroller. A wachdog disable pin ( WD_DIS ) wih an inernal pull down curren source is implemened. Wih a high level he wachdog funcion is disabled. For enabled wachdog funcion afer power-up rese delay ime ( RD ), valid SPI communicaion from he micro conroller mus occur wihin he wachdog period ( WP ) specified in he elecrical characerisics. A resar of he wachdog period is done wih a low o high ransiion of he CSN pin of a valid ransmission of a 16 bi message. A rese is generaed (NRO goes LOW) for he ime ( WR ) if here is no resar during he wachdog period as shown in Figure 5. Saus afer wachdog overflow: all oupus are swiched off SPI regisers are no influenced Wachdog Time Ou bi in SPI saus regiser is se firs answer o SPI communicaion is he conen of he saus regiser Swiching of Oupus and rese of Wachdog Time Ou Bi afer wachdog overflow: Oupus 1 and 3 will be swiched on wih an posiive edge a IN1 respecively IN3 Oupus 2, 4 and 5 will be swiched on wih a wrie command o CMD regiser he wachdog ime ou bi will be rese wih he rising edge of CSN of he firs read command of he saus regiser Daa Shee 9 Rev. 1.2

10 5V Supply, Rese and Supervision Vs V 5DD V RT V NRO Wachdog Period RD Normal operaion rr WR CSN resar WP SI 16 Bis 16 Bis 16 Bis e.g. 4 Bis 1. correc SPI communicaion No correc SPI communicaion wihin he Wachdog Period causing rese Figure 5 Wachdog Timing Diagram Daa Shee 10 Rev. 1.2

11 5V Supply, Rese and Supervision 5.4 Elecrical Characerisics 5V Supply, Rese and Supervision Table 4 Elecrical Characerisics: 5V Supply, Rese and Supervision V S = 13.5 V, T j = -40 C o +150 C, all volages wih respec o ground, posiive curren flowing ino pin (unless oherwise specified) Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion 5V Supply Oupu Volage V V5DD V 0 ma < I V5DD < 250mA, 6V < V S < 18V P_5.1.1 Oupu Curren Limiaion I V5DD ma V V5DD = 0V P_5.1.2 Load Regulaion ΔV V5DD, Lo 50 mv 1 ma < I V5DD < P_ mA Line Regulaion ΔV V5DD, Li 10 mv I V5DD = 1mA, P_ V < V S < 18V Power Supply Rejecion PSRR 60 db f = 100Hz, V S, ripple = 0.5 Vpp 1) P_5.1.5 Oupu Capacior C V5DD 470 nf 1) P_5.1.6 Oupu Capacior ESR ESR(C V5DD ) 10 Ω 1) P_5.1.7 Curren Consumpion I VS ma I V5DD = 0mA, all channels and K- Line off P_5.1.8 Low Drop Volage V V5DD V I V5DD = 1mA V S =5V V I V5DD = 250mA V S = 5V, afer device ramp-up (V S > 9V) V I V5DD 250mA V S = 5.5 V, afer device ramp-up (V S > 9V) 1) P_5.1.9 P_ a P_ b Over Temperaure Proecion Over Temperaure Threshold T OT C 1) P_5.2.1 Over Temperaure Hyseresis T OT,Hys 20 C 1) P_5.2.2 Daa Shee 11 Rev. 1.2

12 5V Supply, Rese and Supervision Table 4 Elecrical Characerisics: 5V Supply, Rese and Supervision (con d) V S = 13.5 V, T j = -40 C o +150 C, all volages wih respec o ground, posiive curren flowing ino pin (unless oherwise specified) Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion Under Volage Deecion V5DD Rese Threshold for TLE8080EM V RT V V V5DD decreasing, only a version TLE8080EM P_5.3.1 Rese Hyseresis V RH mv P_5.3.2 V5DD Rese Threshold for TLE8080-2EM and TLE8080-3EM Power On Rese Power On Rese Delay Time for TLE8080EM and TLE8080-3EM Power On Rese Delay Time for TLE8080-2EM V RT V V V5DD decreasing, only a versions TLE8080-2EM and TLE8080-3EM RD ms only a versions TLE8080EM and TLE8080-3EM RD ms only a version TLE8080-2EM P_5.3.3 P_5.4.1 P_5.4.2 Rese Reacion Time RR µs P_5.4.3 Rese Oupu NRO Low Level Oupu Volage V NRO,L 1.1 V I NRO = 1mA P_5.5.1 Wachdog Wachdog Period WP ms P_5.6.1 Wachdog Rese Time WR µs P_5.6.2 Inpu Characerisics WD_DIS Low Level Inpu Volage V WD_DIS,L 1 V P_5.7.1 High Level Inpu Volage V WD_DIS,H 2 V P_5.7.2 Pull Down Curren I WD_DIS,pd µa a V IN = 5V P_5.7.3 Pull Down Curren I WD_DIS,pd 2.4 µa a V IN = 0.6V P_5.7.4 Hyseresis V WD_DIS,Hys mv P_ ) No subjec o producion es, specified by design. Daa Shee 12 Rev. 1.2

13 Power Sages 6 Power Sages 6.1 Low Side Swiches The power sages are buil by N-channel power MOSFET ransisors. The channels are universal muli channel swiches, bu are mosly suiable o be used in engine managemen sysems. Wihin an engine managemen sysem, he bes fi of he channels o he ypical loads is: Channel 1 and 3 for injecor valves or similar sized solenoids wih a maximum operaion curren requiremen of 2.6A Channel 2 for malfuncion indicaion lamps or oher resisive loads wih a maximum curren requiremen of 3A Channel 4 and 5 for relays or oher inducive loads wih a maximum curren requiremen of 350mA The channels are swiched off while rese is acive (pin NRO is low). Afer an power on rese he channels will be swiched on wih a posiive edge a IN1 respecively IN3 or wih a swich on command over SPI. Vba OUT I D L, R L V ba OUT ID R V DScl V DS VDS GND GND Channel 1, 3, 4, 5 Channel 2 Figure 6 Low Side Swiches In Table 5 he conrol concep, ypical loads, he implemened proecion and monior funcions are illusraed. Table 5 Overview Diagnosis Funcion Channel Conrol Recommended Load Over Temperaure Over Curren Open Load/ Shor o GND 1 Pin IN1 Injecor Valve x Lach 1) x 2 SPI CMD Regiser Bi 0 MIL (max. 3W) x repeiive swiching; off ime 1) oc,off 3 Pin IN3 Valve x Lach 1) x 4 SPI CMD Regiser Bi 1 Relay one emperaure sensor Lach 1) x for channel 4 and channel 5 5 SPI CMD Regiser Bi 2 Relay one emperaure sensor for channel 4 and channel 5 Lach 1) x 1) Rese behavior of he diagnosis bis see Chaper 8.2. Daa Shee 13 Rev. 1.2

14 Power Sages In overcurren condiion he affeced channel will be swiched off. There are wo differen implemenaions for swiching on again afer an over curren even. For channels 1, 3, 4 and 5 he swich off sae is lached. The inpu pins IN1, IN3 mus be se o low o rese he lach before he channel can be swiched on again. For channels 4 and 5 he over curren saus is rese wih a wrie command o he CMD regiser afer a Diagnosis Read Command has been sen. The swiching sae is according o he saus of bi 1 and 2. Channel 2 will be swiched off and afer oc_off = 5ms ypically he channel will be swiched on again auomaically. The resul is repeiive swiching wih a fixed off ime of oc,off. The overcurren saus of channel 2 is inernally lached. For releasing he over curren diagnosis bi afer over curren condiion, channel 2 mus say swiched on for a leas oc,s. The bis 0 o 4 in he Sa regiser reflec he acual swiching saus of he channels. For deailed descripion see Chaper All he channels are proeced from over emperaure. In an overemperaure siuaion he affeced channel will be swiched off. The channel will resar operaion if he juncion emperaure decreases by hermal shudown hyseresis T OT,Hys. Channels 4 and 5 are using a common emperaure sensor. Therefore, he wo channels are swiched ogeher during over emperaure. For channels 1, 3, 4 and 5 an open load/shor o GND in off deecion wih a pull down curren source (acive in off) and a comparaor is implemened. In case of swich off and he oupu volage is below he open load deecion hreshold (V oux < V ol,h ), he open load in off imer is sared. Afer he open load in off delay ime ol,d, he open load is deeced (iming see Figure 9 and Figure 10). The diagnosis saus of he channels is moniored in he SPI Diagnosis Regiser DIAG (see Chaper 8.2). Daa Shee 14 Rev. 1.2

15 Power Sages 6.2 Elecrical Characerisics Low Side Swiches Table 6 Elecrical Characerisics: Power Sage V S = 13.5 V, T j = -40 C o +150 C: All volages wih respec o ground. Posiive curren flowing ino pin (unless oherwise specified). Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion Oupu Channel 1 and 3 On Resisance R OUTx_on Ω I OUTx_nom = 1.3A, P_6.1.1 T j = 150 C Oupu Clamping Volage V OUTx_cl V I OUTx = 0.02A P_6.1.2 Over-curren Swich Off Threshold I OUTx_oc A P_6.1.3 Over-curren Swich Off Filer Time oc,f µs P_6.1.4 Over Temperaure Swich Off T OT C P_6.1.5 Over Temperaure Hyseresis T OT,Hys 20 C P_6.1.6 Open Load in Off Deecion Threshold V ol,h V P_6.1.7 Open Load in Off Pull Down Diagnosis I ol µa V OUTx = 13.5V P_6.1.8 Curren Open Load in Off Diagnosis Delay ol,d µs P_6.1.9 Time Turn On Delay Time d,on µs V OUTx = 13.5V, I OUTx = 1.3A, resisive load 1) P_ Turn Off Delay Time d,off µs V OUTx = 13.5V, I OUTx = 1.3A, resisive load 1) Turn On Time s,on µs V OUTx = 13.5V, I OUTx = 1.3A, resisive load 1) Turn Off Time s,off µs V OUTx = 13.5V, I OUTx = 1.3A, resisive load 1) P_ P_ P_ Oupu Leakage Curren in Off Mode I OUTx_off 3 µa V OUTx = 13.5V, P_ T j = 150 C 2) Oupu Channel 2 On Resisance R OUTx_on Ω I OUTx_nom = 0.3A, P_6.2.1 T j = 150 C Over-curren Swich Off Threshold I OUTx_oc A P_6.2.2 Over-curren Swich Off Filer Time oc,f µs P_6.2.3 Over-curren Swich Off Time oc,off 3 8 ms P_6.2.4 Over-curren Saus Time oc,s 1 12 ms P_6.2.5 Over Temperaure Swich Off T OT C P_6.2.6 Daa Shee 15 Rev. 1.2

16 Power Sages Table 6 Elecrical Characerisics: Power Sage (con d) V S = 13.5 V, T j = -40 C o +150 C: All volages wih respec o ground. Posiive curren flowing ino pin (unless oherwise specified). Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion Over Temperaure Hyseresis T OT,Hys 20 C P_6.2.7 Turn On Delay Time d,on µs V OUTx = 13.5, I OUTx = 1.3A, resisive load 1) P_6.2.8 Turn Off Delay Time d,off µs V OUTx = 13.5V, I OUTx = 1.3A, resisive load 1) Turn On Time s,on µs V OUTx = 13.5V, I OUTx = 1.3A, resisive load 1) Turn Off Time s,off µs V OUTx = 13.5V, I OUTx = 1.3A, resisive load 1) P_6.2.9 P_ P_ Oupu Leakage Curren in Off Mode I OUTx_off 3 µa V OUTx = 13.5V, P_ T j = 150 C Oupu Channel 4 and 5 On Resisance R OUTx_on Ω I OUTx_nom = 0.3A, P_6.3.1 T j = 150 C Oupu Clamping Volage V OUTx_cl V I OUTx = 0.02A P_6.3.2 Over-curren Swich Off Threshold I OUTx_oc ma P_6.3.3 Over-curren Swich Off Filer Time oc,f µs P_6.3.4 Over Temperaure Swich Off T OT C P_6.3.5 Over Temperaure Hyseresis T OT,Hys 20 C P_6.3.6 Open Load in Off Deecion Threshold V ol,h V P_6.3.7 Open Load in Off Pull Down Diagnosis I ol µa V OUTx = 13.5V P_6.3.8 Curren Open Load in Off Diagnosis Delay ol,d µs P_6.3.9 Time Turn On Delay Time d,on µs V OUTx = 13.5V, I OUTx = 0.3A, resisive load 1) P_ Turn Off Delay Time d,off µs V OUTx = 13.5V, I OUTx = 0.3A, resisive load 1) Turn On Time s,on µs V OUTx = 13.5V I OUTx = 0.3A, resisive load 1) P_ P_ Daa Shee 16 Rev. 1.2

17 Power Sages Table 6 Elecrical Characerisics: Power Sage (con d) V S = 13.5 V, T j = -40 C o +150 C: All volages wih respec o ground. Posiive curren flowing ino pin (unless oherwise specified). Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion Turn Off Time s,off µs V OUTx = 13.5V, I OUTx = 0.3A, resisive load 1) P_ Oupu Leakage Curren in Off Mode I OUTx_off 2 µa V OUTx = 13.5V, P_ T j = 150 C 2) Inpu Characerisic IN1 and IN3 Low Level Inpu Volage V IN,L 1 V P_6.4.1 High Level Inpu Volage V IN,H 2 V P_6.4.2 Inpu Volage Hyseresis V IN,Hys mv P_6.4.3 Pull Down Curren I IN,PD µa V IN = 5V P_6.4.4 Pull Down Curren I IN,PD 2.4 µa V IN = 0.6V P_ ) definiion of iming see Figure 7 or Figure 8. 2) in OFF mode open load diagnosis pull down curren acive. V IN x V OUTx V BATT 80% 20% d,on s, ON d,off s, OFF Figure 7 Timing Low Side Swiches Channel 1 and 3 Daa Shee 17 Rev. 1.2

18 Power Sages V CSN V OUTx V BATT 80% 20% d,on s, ON d,off s, OFF Figure 8 Timing Low Side Swiches Channel 2, 4 and 5 V INx V OUTx V BATT open open V ol.h ol.d ol.d CHx_OL Figure 9 Timing Open Load/Shor o GND in Off Deecion Channel 1 and 3 Daa Shee 18 Rev. 1.2

19 Power Sages V CSN V OUTx VBATT open open V ol.h ol.d ol.d CHx_OL Figure 10 Timing Open Load/Shor o GND in Off Deecion Channel 2, 4 and 5 Daa Shee 19 Rev. 1.2

20 Variable Relucance Sensor ( VRS ) Inerface 7 Variable Relucance Sensor ( VRS ) Inerface The variable relucance (VR) sensor inerface convers an oupu signal of a VR sensor ino a logic level signal suied for µc 5V inpu pors. The volage difference beween he wo inpu pins, VR_IN1 and VR_IN2, which are conneced o he wo oupu pins of he VR sensor, is deeced and he oupu pin VR_OUT is swiched depending on he sign of he volage difference (see Figure 12 ). The ampliude of he VR sensor signal is limied by an inernal clamping circui o avoid damage of he device due o over volage caused by he VR sensor signal. VR_IN1 Selec Load Clamp & Load 2,5V Buffer Deecion VR_OUT VR_IN2 Selec Threshold Figure 11 VR Sensor Inerface Block Diagram Daa Shee 20 Rev. 1.2

21 Variable Relucance Sensor ( VRS ) Inerface 7.1 Elecrical Characerisics VR Sensor Inerface Table 7 Elecrical Characerisics: VR Sensor Inerface V S = 13.5 V, T j = -40 C o +150 C: All volages wih respec o ground. Posiive curren flowing ino pin (unless oherwise specified) Parameer Symbol Values Uni Noe or Tes Condiion Number Min. Typ. Max. Inpu Characerisics: Posiive VR Sensor Inerface Deecion Threshold V VR,h_pos mv P_7.1.1 Negaive VR Sensor Inerface Deecion Threshold Negaive VR Sensor Inerface Deecion Threshold Negaive VR Sensor Inerface Deecion Threshold Negaive VR Sensor Inerface Deecion Threshold VR Sensor Inerface Load Selecion VR Sensor Inerface Load Selecion VR Sensor Inerface Load Selecion VR Sensor Inerface Load Selecion VR Sensor Inerface Inpu Clamping Curren VR Sensor Inerface Inpu Clamping Volage V VR,h_neg mv CMD Regiser: VR_T[1:0] = 00 Rese Sae mv CMD Regiser: VR_T[1:0] = mv CMD Regiser: VR_T[1:0] = V CMD Regiser: VR_T[1:0] = 11 R VR,Load kω T j = 25 C, CMD Regiser: VR_L[1:0] = 00 Rese Sae 90 kω T j = -40 C, CMD Regiser: VR_L[1:0] = 00 Rese Sae 60 kω T j = 150 C, CMD Regiser: VR_L[1:0] = 00 Rese Sae kω CMD Regiser: VR_L[1:0] = kω CMD Regiser: VR_L[1:0] = kω CMD Regiser: VR_L[1:0] = 11 P_7.1.2 P_7.1.3 P_7.1.4 P_7.1.5 P_7.1.6 P_7.1.7 P_7.1.8 P_7.1.9 I VR,clamp ±50 ma P_ V VR,clamp ±2.5 ±3 ±3.5 V I VR,clamp = ±50mA P_ Daa Shee 21 Rev. 1.2

22 Variable Relucance Sensor ( VRS ) Inerface Table 7 Elecrical Characerisics: VR Sensor Inerface (con d) V S = 13.5 V, T j = -40 C o +150 C: All volages wih respec o ground. Posiive curren flowing ino pin (unless oherwise specified) Parameer Symbol Values Uni Noe or Tes Condiion Number Min. Typ. Max. Oupu Characerisics: Low Level Oupu Volage V VR_OUT,L 0.3 V I VR_OUT = 100µA P_7.2.1 High Level Oupu Volage V VR_OUT,H V5DD V I VR_OUT = -100µA P_ Transfer Characerisics: Delay Time Inpu o VR_OUT dr µs P_7.3.1 falling edge Delay Time Inpu o VR_OUT rising edge df µs P_7.3.2 V VR_IN1 VR_IN2 V VRT h_pos =0V V VRT h_neg V VR_OUT dr df 50% Figure 12 Timing Characerisics of he VR Sensor Inerface Daa Shee 22 Rev. 1.2

23 Serial Peripheral Inerface (SPI) 8 Serial Peripheral Inerface (SPI) The diagnosis and conrol inerface is based on a serial peripheral inerface (SPI). The SPI is a 16 bi full duplex synchronous serial slave inerface, which uses four lines: SI, SO, SCLK and CSN. 8.1 SPI Signal Descripion CSN - Chip Selec: The sysem micro conroller selecs he IC by means of he CSN pin. Whenever he pin is in low sae, daa ransfer can ake place. As long as CSN is in high sae, all signals a he SCLK and SI pins are ignored and SO is forced o high impedance. CSN - High o Low Transiion: SO changes from high impedance o high or low sae depending on he Saus Flag (see Chaper 8.2). CSN - Low o High Transiion: End of ransmission, he validaion check of he communicaion is done (number of bis and valid command) and valid commands are execued. SCLK - Serial Clock: This inpu pin clocks he inernal shif regiser. The serial inpu (SI) ransfers daa ino he shif regiser on he falling edge of SCLK while he serial oupu (SO) shifs informaion ou on he rising edge of he serial clock. I is essenial ha he SCLK pin is in low sae whenever chip selec CSN makes any ransiion. SI - Serial Inpu: Serial inpu daa bis are shifed in a his pin, he mos significan bi (MSB) firs. SI informaion is read on he falling edge of SCLK. Please refer o Secion 8.2 for furher informaion. SO - Serial Oupu: Daa is shifed ou serially a his pin, he MSB firs. SO is in high impedance unil he CSN pin goes o low. The oupu level before he firs rising edge of SCLK depends on he saus flag. New daa will appear a he SO pin following he rising edge of SCLK. Please refer o Secion 8.2 for furher informaion. 8.2 SPI Proocol The principle of he SPI communicaion is shown in Figure 13. The message from he micro conroller mus be sen MSB firs. The daa from he SO pin is sen MSB firs. The TLE8080EM samples daa from he SI pin on he falling edge of SCLK and shifs daa ou of he SO pin on he rising edge of SCLK. Each access mus be erminaed by a rising edge of CSN. All SPI messages mus be exacly 16-bis long, oherwise he SPI message is discarded. There is a one message delay in he response o each message (i.e. he response for message N will be reurned during message N+1). The SPI proocol of he TLE8080EM provides hree regisers. The conrol regiser, he diagnosis, and he saus regiser. The conrol regiser conains he se up bis for he VR sensor inerface and he conrol bis of channels 2, 4 and 5. The diagnosis regiser conains he diagnosis bis of he five low side swiches. The saus regiser conains he saus bis of he five low side swiches, he wachdog saus bi, and he wachdog ime ou bi. Afer power-on rese, all regiser bis are se o rese sae (see Chaper 8.2.1). Daa Shee 23 Rev. 1.2

24 Serial Peripheral Inerface (SPI) There are four ways of valid access: Wrie access o he command regiser: he answer is 1 for he R/W bi, 00 for he address and he conen of he regiser Read access o he command regiser: he answer is 0 for he R/W bi, 00 for he address and he conen of he regiser Read access o he diagnosis regiser: he answer is 0 for he R/W bi, 01 for he address and he conen of he regiser Read access o he saus regiser: he answer is 0 for he R/W bi, 10 for he address and he conen of he regiser Any oher access is recognized as an invalid message. Saus Flag Indicaion: afer he falling edge of CSN and before he firs rising edge of SCLK, he level of he SO indicaes he saus of he diagnosis regiser: SO = 0 : no error condiion deeced; all diagnosis regiser bis are 0 SO = 1 : one or more error condiions are deeced; one or more diagnosis regiser bis are 1 Wih his feaure during every SPI communicaion a check of he diagnosis saus can be done wihou addiional read access of he diagnosis regiser. CSN ime SCLK don care clock 1 * ) clock 2 clock 3 clock 15 clock 16 don care ime SI don care Bi 15 MSB Bi 14 Bi 13 Bi 1 Bi 0 LSB don care ime SO risae Saus Flag Bi 15 MSB Bi 14 Bi 13 Bi 1 Bi 0 LSB risae ime * ) acive clock edge for reading daa a SI Figure 13 SPI Proocol SPI Answers: during power on rese: SPI commands are ignored, SO is always low afer power on rese: he conen of he command regiser is ransmied wih he nex SPI ransmission during wachdog rese: SPI commands are ignored, SO has he value of he saus flag afer wachdog overflow: he conen of he saus regiser is ransmied wih he firs SPI ransmission afer he low o high ransiion of NRO Daa Shee 24 Rev. 1.2

25 Serial Peripheral Inerface (SPI) afer a read or wrie command: he conen of he seleced regiser is ransmied wih he nex SPI ransmission afer an invalid communicaion: he conen of he diagnosis regiser is ransmied wih he nex SPI ransmission SPI Regiser Overview R/W AD1 AD0 Field Bis Type Descripion AD1:AD0 [14:13] w Address Bis: 00 B Conrol Regiser 01 B Diagnosis Regiser 10 B Saus Regiser R/W 15 w Read - Wrie Bi: 0 B Read Access 1 B Wrie Access CMD Regiser Command Regiser (Idenifier x00x xxxx xxxx xxxx B ) Rese Value: 0 H R/W AD1 AD0 VR_T1 VR_T0 VR_L1 VR_L0 CTR5 CTR4 CTR2 rw rw rw rw rw rw rw Field Bis Type Descripion CTR2 0 rw Conrol Bi Channel 2: 0 B Channel 2 is swiched off (Rese Sae) 1 B Channel 2 is swiched on CTR4 1 rw Conrol Bi Channel 4: 0 B Channel 4 is swiched off (Rese Sae) 1 B Channel 4 is swiched on CTR5 2 rw Conrol Bi Channel 5: 0 B Channel 5 is swiched off (Rese Sae) 1 B Channel 5 is swiched on Daa Shee 25 Rev. 1.2

26 Serial Peripheral Inerface (SPI) Field Bis Type Descripion VR_L1: VR_L0 [10:9] rw Load Regiser of VR Inerface: ( c.f. VR Sensor Inerface Load Selecion ) 00 B R Load = 75kΩ (Rese Sae) 01 B R Load = 4.5kΩ 10 B R Load = 2.2kΩ 11 B R Load = 1.2kΩ VR_T1: VR_T0 [12:11] rw Threshold Regiser of VR Inerface: 00 B -50mV (Rese Sae) 01 B -100mV 10 B -500mV 11 B -1V Diag Regiser Diagnosis Regiser (Idenifier x01x xxxx xxxx xxxx B ) Rese Value: 0 H R/W AD1 AD0 CH45_ OT CH5_O C CH5_O L CH4_O C CH4_O L CH3_O T CH3_O C CH3_O L CH2_O T CH2_O C CH1_O T CH1_O CH1_O C L r r r r r r r r r r r r r Field Bis Type Descripion CH1_OL 0 r Open Load Diagnosis Bi of Channel 1: 0 B no open load in off deeced (Rese Sae) 1 B open load in off deeced CH1_OC 1 r Over Curren Diagnosis Bi of Channel 1: 0 B no over curren deeced (Rese Sae) 1 B over curren deeced CH1_OT 2 r Over Temperaure Diagnosis Bi of Channel 1: 0 B no over emperaure deeced (Rese Sae) 1 B over emperaure deeced CH2_OC 3 r Over Curren Diagnosis Bi of Channel 2: 0 B no over curren deeced (Rese Sae) 1 B over curren deeced CH2_OT 4 r Over Temperaure Diagnosis Bi of Channel 2: 0 B no over emperaure deeced (Rese Sae) 1 B over emperaure deeced CH3_OL 5 r Open Load Diagnosis Bi of Channel 3: 0 B no open load in off deeced (Rese Sae) 1 B open load in off deeced CH3_OC 6 r Over Curren Diagnosis Bi of Channel 3: 0 B no over curren deeced (Rese Sae) 1 B over curren deeced Daa Shee 26 Rev. 1.2

27 Serial Peripheral Inerface (SPI) Field Bis Type Descripion CH3_OT 7 r Over Temperaure Diagnosis Bi of Channel 3: 0 B no over emperaure deeced (Rese Sae) 1 B over emperaure deeced CH4_OL 8 r Open Load Diagnosis Bi of Channel 4: 0 B no open load in off deeced (Rese Sae) 1 B open load in off deeced CH4_OC 9 r Over Curren Diagnosis Bi of Channel 4: 0 B no over curren deeced (Rese Sae) 1 B over curren deeced CH5_OL 10 r Open Load Diagnosis Bi of Channel 5: 0 B no open load in off deeced (Rese Sae) 1 B open load in off deeced CH5_OC 11 r Over Curren Diagnosis Bi of Channel 5: 0 B no over curren deeced (Rese Sae) 1 B over curren deeced CH45_OT 12 r Over Temperaure Diagnosis Bi of Channel 4 and 5: 0 B no over emperaure deeced (Rese Sae) 1 B over emperaure deeced Sa Regiser Saus Regiser (Idenifier x10x xxxx xxxx xxxx B ) Rese Value: 0 H R/W AD1 AD0 WD_DI S WD_T O ST5 ST4 ST3 ST2 ST1 r r r r r r r Field Bis Type Descripion ST1 0 r Saus Bi Channel 1: 0 B Channel 1 is swiched off (Rese Sae) 1 B Channel 1 is swiched on ST2 1 r Saus Bi Channel 2: 0 B Channel 2 is swiched off (Rese Sae) 1 B Channel 2 is swiched on ST3 2 r Saus Bi Channel 3: 0 B Channel 3 is swiched off (Rese Sae) 1 B Channel 3 is swiched on ST4 3 r Saus Bi Channel 4: 0 B Channel 4 is swiched off (Rese Sae) 1 B Channel 4 is swiched on ST5 4 r Saus Bi Channel 5: 0 B Channel 5 is swiched off (Rese Sae) 1 B Channel 5 is swiched on Daa Shee 27 Rev. 1.2

28 Serial Peripheral Inerface (SPI) Field Bis Type Descripion WD_TO 11 r Wachdog Time Ou Bi: 0 B no wachdog ime ou 1 B wachdog ime ou occurred WD_DIS 12 r Wachdog Saus Bi: 0 B Wachdog enabled (V WD_DIS = 0V) 1 B Wachdog disabled (V WD_DIS = 5V) Se and Rese of Diagnosis Regiser Bis Se of he over curren diagnosis bis of channels 1, 3, 4 and 5: The over curren diagnosis bis of channels 1, 3, 4 and 5 are se asynchronously of he inernal clock wih he oupu signal of he deecion circui (deails see Chaper 6.1). Rese of he over curren diagnosis bis of channels 1 and 3: Diagnosis regiser was read ou: inpu pin INx remains high: no rese of he over curren diagnosis bi, he channel remains swiched off inpu pin INx ransiion from high o low: he over curren diagnosis bi is rese, he channel could be swiched on again Diagnosis regiser was no read ou channel remains swiched off and no rese of he over curren diagnosis bi is done inpu pin INx is low: wih he nex read access of he diagnosis regiser he diagnosis bis are rese Rese of he over curren diagnosis bis of channels 4 and 5: Diagnosis regiser was no read ou channel remains swiched off and no rese of he over curren diagnosis bi is done Diagnosis regiser was read ou: SPI command regiser wrie command is no sen: no rese of he over curren diagnosis bi, he channel remains swiched off SPI command regiser wrie command is sen: he over curren diagnosis bi is rese, he channel will be swiched according he saus of he conrol bi Se and Rese of he over curren diagnosis bi of channel 2: The over curren diagnosis regiser bi for channel 2 is se asynchronously of he inernal clock wih he oupu signal of he deecion circui. Wih his signal he oupu is swiched off and he couner for he off ime oc,off of he repeiive swiching cycle sars. Afer oc,off he channel will be swiched on again. Wih an remaining over curren condiion he channel will be swiched on repeiively. This inernal overcurren saus of he channel is lached inernally. The inernal over curren saus is rese in wo siuaions. over curren condiion exiss no longer: he inernal over curren saus is rese afer he ime oc,s over curren condiion remains and he channel is swiched off: he inernal over curren saus is rese afer he ime oc,off The rese of he over curren diagnosis regiser bi for channel 2 is relaed o he inernal over curren saus. In Figure 14 and Figure 15 he behavior of he diagnosis wih emporary and permanen over curren condiion is drawn. Daa Shee 28 Rev. 1.2

29 Serial Peripheral Inerface (SPI) Over Curren No Over Curren Con Reg. Bi 1 oc,f oc,f oc,f I OUT2 I D,oc Inernal Over Curren Saus oc,off oc,off oc,s Diag Reg. Bi 3 SPI Diag Reg. Read Ou SPI Diag Reg. Read Ou SPI Diag Reg. Read Ou Figure 14 Behavior of diagnosis wih emporary over curren condiion a channel 2 Permanen Over Curren Con Reg. Bi 1 oc,f oc,f oc,f I OUT2 I D,oc Inernal Over Curren Saus oc,off oc,off oc,off Diag Reg. Bi 3 SPI Diag SPI Diag Reg. Reg. Read Ou Read Ou SPI Diag Reg. Read Ou Figure 15 Behavior if diagnosis wih permanen over curren condiion a channel 2 Daa Shee 29 Rev. 1.2

30 Serial Peripheral Inerface (SPI) Rese of he over emperaure diagnosis bis: The over emperaure diagnosis bis will be rese wih read access of he diagnosis regiser if no over emperaure condiion is deeced. Rese of he open load in off diagnosis bis: The open load in off diagnosis bis will be rese wih read access of he diagnosis regiser if no open load condiion is deeced. Daa Shee 30 Rev. 1.2

31 Serial Peripheral Inerface (SPI) 8.3 Elecrical Characerisics SPI Table 8 Elecrical Characerisics: SPI V S = 13.5 V, T j = -40 C o +150 C: All volages wih respec o ground. Posiive curren flowing ino pin (unless oherwise specified). Parameer Symbol Values Uni Noe or Tes Condiion Number Min. Typ. Max. Inpu Characerisics (CSN, SCLK, SI): Low Level Inpu Volage V x,l 1 V P_8.1.1 High Level Inpu Volage V x,h 2 V P_8.1.2 Hyseresis V x,hys mv Pull Up Curren CSN I x,pu µa a V IN = 0V P_8.1.3 Pull Up Curren CSN I x.pu -25 µa a V IN = V V5DD - 0.6V P_8.1.4 Pull Down Curren SCLK, SI I x,pu µa a V IN = V V5DD P_8.1.5 Pull Down Curren SCLK, SI I x.pu 2.4 µa a V IN = 0.6V P_8.1.6 Oupu Characerisics (SO): Low Level Oupu Volage V So,L 0.4 V I x = 100µA P_8.2.1 High Level Oupu Volage V SO,H V5DD V I x = -100µA P_ Oupu High Impedance I SO,TRI -3 3 µa 0V < V SO < 5V P_8.2.3 Leakage Curren Timings: Lead Time ns CSN falling o SCLK rising P_8.3.1 Lag Time 2 75 ns SCLK falling o CSN rising P_8.3.2 CSN High Time ns CSN rising o CSN falling P_8.3.3 Period of SCLK ns P_8.3.4 SCLK o CSN Se Up Time 5 10 ns SCLK falling o CSN falling P_8.3.5 SCLK Low Time 7 60 ns P_8.3.6 CSN o SCLK Hold Time 8 15 ns CSN rising o SCLK rising P_8.3.7 SI Se Up Time 9 30 ns SI se up ime o SCLK P_8.3.8 falling SI Hold Up Time ns SI holdup ime afer SCLK P_8.3.9 falling SO Enable Time ns CSN falling o SO acive P_ SO Valid Time ns SO daa valid afer SCLK P_ rising SO Disable Time ns SO high impedance afer P_ CSN rising Number of Clock Pulses while CSN = low pulses P_ Daa Shee 31 Rev. 1.2

32 Serial Peripheral Inerface (SPI) Table 8 Elecrical Characerisics: SPI (con d) V S = 13.5 V, T j = -40 C o +150 C: All volages wih respec o ground. Posiive curren flowing ino pin (unless oherwise specified). Parameer Symbol Values Uni Noe or Tes Condiion Number Min. Typ. Max. SO Rise Time SO_rise 75 ns 20% o 80%, C load =1.6pF SO Fall Time SO_fall 75 ns 80% o 20% C load =1.6pF P_ P_ CSN ime SCLK don care clock 1 clock 2 clock 3 clock 15 clock 16 don care ime 9 10 SI don care Bi 15 MSB Bi 14 Bi 13 Bi 1 Bi 0 LSB don care ime SO risae Saus Flag Bi 15 MSB Bi 14 Bi 13 Bi 1 Bi 0 LSB risae ime Figure 16 SPI Timing Diagram Daa Shee 32 Rev. 1.2

33 K-Line 9 K-Line 9.1 K-Line The K-Line module is a serial link bus inerface device designed o provide bi-direcional half-duplex communicaion inerfacing. I is designed o inerface vehicles via he special ISO K-Line and mees he ISO sandard The device s K-Line bus driver s oupu is proeced agains bus shors. VS RX V5DD KIO TX Driver & Proecion Figure 17 K-Line Block Diagram Daa Shee 33 Rev. 1.2

34 K-Line 9.2 Elecrical Characerisics K-Line Table 9 Elecrical Characerisics: K-Line V S = 13.5 V, T j = -40 C o +150 C: All volages wih respec o ground. Posiive curren flowing ino pin (unless oherwise specified). Parameer Symbol Values Uni Noe or Number Min. Typ. Max. Tes Condiion Oupu RX Low Level Oupu Volage V RX,L 0.4 V I RX = 100µA P_9.1.1 High Level Oupu Volage V RX,H V5DD- V I RX = -100µA P_ Inpu TX Low Level Inpu Volage V TX,L 1 V P_9.2.1 High Level Inpu Volage V TX,H 3.2 V P_9.2.2 Hyseresis V TX,Hys mv P_9.2.3 Pull Up Curren I PU_L µa a V TX = 0V P_9.2.4 Pull Up Curren I PU_L -30 µa a V TX = V V5DD - P_ V K-Line Bus Driver Inpu/Oupu KIO Low Level Oupu Volage V KIO,O,L 1.4 V TX = low, P_9.3.1 R KIO = 480Ω Curren Limiaion I KIO(lim) ma P_9.3.2 Low Level Inpu Volage V KIO,I,L 0.4*VS V P_9.3.3 High Level Inpu Volage V KIO,I,H 0.6*VS V P_9.3.4 Hyseresis V KIO,I,Hys 0.02 *VS V P_9.3.5 *VS Pull Down Curren I KIO,pd µa P_9.3.6 Transfer Characerisics C RX = 25pF; R KIO = 540Ω; C KIO 1.3nF Receive Frequency f KIO,rec 500 khz C KIO = 0pF P_9.4.1 Transmi Frequency f KIO,ran 100 khz P_9.4.2 Delay Time KIO -> RX rising edge 1) drr µs C RX,load = 1.6pF P_9.4.3 Delay Time KIO -> RX falling edge 1) dfr µs C RX,load = 1.6pF P_9.4.4 Delay Time TX -> KIO rising edge 1)2) drt µs C KIO,load = 1.6pF P_9.4.5 Delay Time TX -> KIO falling edge 1) dft µs C KIO,load = 1.6pF P_ ) For definiion see Figure 18. 2) No subjec of producion es, behavior defined by exernal devices. Daa Shee 34 Rev. 1.2

35 K-Line V TxD V V5DD 0.5*V V5DD V bus dft drt V S 0.7*V S 0.3*V S V RxD dfr drr V V5DD 0.5*V V5DD Figure 18 K-Line Transfer Characerisics Daa Shee 35 Rev. 1.2

36 Package Oulines 10 Package Oulines ) ± Sand Off 0.65 (1.47) C 1.7 MAX. 0.2 M C A-B D 24x 0.08 C Seaing Plane 2x 0.1 CD 1) 3.9 ±0.1 D 0.35 x 45 6 ± ± MAX. M D A Index Marking B 8.65 ± C A-B 2x Boom View ± ±0.25 1) Does no include plasic or meal prorusion of 0.15 max. per side 2) Does no include dambar prorusion of 0.13 max. PG-SSOP-24-4-PO V01 Figure 19 PG-SSOP24 Green Produc (RoHS complian) To mee he world-wide cusomer requiremens for environmenally friendly producs, and o be complian wih governmen regulaions, he device is available as a green produc. Green producs are RoHS-Complian (i.e Pb-free finish on leads and suiable for Pb-free soldering according o IPC/JEDEC J-STD-020). For furher informaion on alernaive packages, please visi our websie: hp:// Dimensions in mm Daa Shee 36 Rev. 1.2

37 Revision Hisory 11 Revision Hisory Revision Dae Changes Daa Shee Parameer Rese Reacion Time on Page 12 increased. 1.2 Added varian TLE8080-3EM. Parameer Low Drop Volage on Page 11 is spil in P_ a and P_ b. Removed 50% indicaor for VCSN signals in Figure 7, Figure 8, Figure 9 and Figure 10. Removed pin KIO from P_4.1.5 in Table 1 as covered by P_ Added afer a Diagnosis Read has been performed o descripion of channel 4 and 5 over curren saus rese behavior. Ediorial changes. Daa Shee 37 Rev. 1.2

38 Please read he Imporan Noice and Warnings a he end of his documen Trademarks of Infineon Technologies AG µhvic, µipm, µpfc, AU-ConverIR, AURIX, C166, CanPAK, CIPOS, CIPURSE, CoolDP, CoolGaN, COOLiR, CoolMOS, CoolSET, CoolSiC, DAVE, DI-POL, DirecFET, DrBlade, EasyPIM, EconoBRIDGE, EconoDUAL, EconoPACK, EconoPIM, EiceDRIVER, eupec, FCOS, GaNpowIR, HEXFET, HITFET, HybridPACK, imotion, IRAM, ISOFACE, IsoPACK, LEDrivIR, LITIX, MIPAQ, ModSTACK, my-d, NovalihIC, OPTIGA, OpiMOS, ORIGA, PowIRaudio, PowIRSage, PrimePACK, PrimeSTACK, PROFET, PRO-SIL, RASIC, REAL3, SmarLEWIS, SOLID FLASH, SPOC, SrongIRFET, SupIRBuck, TEMPFET, TRENCHSTOP, TriCore, UHVIC, XHP, XMC. Trademarks updaed November 2015 Oher Trademarks All referenced produc or service names and rademarks are he propery of heir respecive owners. Ediion Published by Infineon Technologies AG Munich, Germany 2016 Infineon Technologies AG. All Righs Reserved. Do you have a quesion abou any aspec of his documen? erraum@infineon.com IMPORTANT NOTICE The informaion given in his documen shall in no even be regarded as a guaranee of condiions or characerisics ("Beschaffenheisgaranie"). Wih respec o any examples, hins or any ypical values saed herein and/or any informaion regarding he applicaion of he produc, Infineon Technologies hereby disclaims any and all warranies and liabiliies of any kind, including wihou limiaion warranies of non-infringemen of inellecual propery righs of any hird pary. In addiion, any informaion given in his documen is subjec o cusomer's compliance wih is obligaions saed in his documen and any applicable legal requiremens, norms and sandards concerning cusomer's producs and any use of he produc of Infineon Technologies in cusomer's applicaions. The daa conained in his documen is exclusively inended for echnically rained saff. I is he responsibiliy of cusomer's echnical deparmens o evaluae he suiabiliy of he produc for he inended applicaion and he compleeness of he produc informaion given in his documen wih respec o such applicaion. For furher informaion on echnology, delivery erms and condiions and prices, please conac he neares Infineon Technologies Office ( WARNINGS Due o echnical requiremens producs may conain dangerous subsances. For informaion on he ypes in quesion please conac your neares Infineon Technologies office. Excep as oherwise explicily approved by Infineon Technologies in a wrien documen signed by auhorized represenaives of Infineon Technologies, Infineon Technologies producs may no be used in any applicaions where a failure of he produc or any consequences of he use hereof can reasonably be expeced o resul in personal injury.