LITIX Basic. 1 Overview GND TLD Channel High-Side Current Source

Transcription

1 3 Channel High-Side Curren Source Package Marking PG-SSOP-14 TLD Overview Applicaions Exerior LED lighing applicaions such as ail/brake ligh, urn indicaor, posiion ligh, side marker,... Inerior LED lighing applicaions such as ambien lighing, inerior illuminaion and dash board lighing. VBATT GND DC/DC Converer DC/DC conroller 10kΩ CVS=4.7nF EN IN_SET PWMI VS Inernal supply Thermal proecion Curren adjusmen Oupu conrol OUT3 OUT2 OUT1 RSET CN-1 CFB RFB N-1 DC/DC conrol FB GND Applicaion Diagram wih Daa Shee Rev

2 Overview Basic Feaures 3 Channel device wih inegraed oupu sages (curren sources), opimized o drive LEDs wih oupu curren up o 120 ma per channel Low curren consumpion in sleep mode PWM-operaion suppored via VS- and EN-pin Inegraed PWM dimming engine o provide wo LED brighness levels wihou exernal logic (e.g. µc) Oupu curren adjusable via exernal low power resisor and possibiliy o connec PTC resisor for LED proecion during over emperaure condiions Dynamic overhead conrol Reverse polariy proecion and overload proecion Undervolage deecion N-1 deecion, lached funcion Wide emperaure range: -40 C < T j < 150 C PG-SSOP-14 package wih exposed heaslug Descripion The LITIX Basic is a hree channel high side driver IC wih inegraed oupu sages. I is designed o conrol LEDs wih a curren up o 120 ma. In ypical auomoive applicaions he device is capable o drive i.e. 3 red LEDs per chain (oal 9 LEDs) wih a curren up o 60 ma, which is limied by hermal cooling aspecs. The oupu curren is conrolled pracically independen of load and supply volage changes. Table 1 Produc Summary Parameer Symbol Value Operaing volage range V S(nom) 5.5 V V Maximum volage V S(max) 40 V V OUTx(max) Nominal oupu (load) curren I OUTx(nom) 60 ma when using a supply volage range of 8 V - 18 V (e.g. Auomoive car baery). Currens up o I OUT(max) possible in applicaions wih low hermal resisance R hja Maximum oupu (load) curren I OUTx(max) 120 ma; depending on hermal resisance R hja Oupu curren accuracy a R SET = 12 kω k LT 750 ± 7% Curren consumpion in sleep mode I S(sleep,yp) 0.1 µa Proecive Funcions ESD proecion Under volage lock ou Over Load proecion Over Temperaure proecion Reverse Polariy proecion Diagnosic Funcions N-1 deecion, lached funcion SC o Vs (indicaed by N-1 diagnosis) Daa Shee 2 Rev. 1.2

3 Block Diagram 2 Block Diagram VS EN IN_SET PWMI Inernal supply Thermal proecion Curren adjusmen Oupu conrol OUT3 OUT2 OUT1 N-1 DC/DC conrol FB GND Figure 1 Basic Block Diagram Daa Shee 3 Rev. 1.2

4 Pin Configuraion 3 Pin Configuraion 3.1 Pin Assignmen VS 1 14 NC VS 2 13 OUT3 EN 3 12 OUT2 NC 4 EP 11 OUT1 PWMI 5 10 FB IN_SET 6 9 GND N NC Figure 2 Pin Configuraion Daa Shee 4 Rev. 1.2

5 Pin Configuraion 3.2 Pin Definiions and Funcions Pin Symbol Inpu/ Funcion Oupu 1, 2 VS Supply Volage; baery supply, connec a decoupling capacior (100 nf - 1 µf) o GND 3 EN I Enable pin 4 NC Pin no conneced 5 PWMI I/O PWM Inpu 6 IN_SET I/O Inpu / SET pin; Connec a low power resisor o adjus he oupu curren 7 N-1 I/O N-1 pin 8 NC Pin no conneced 9 GND 1) Ground 10 FB O Feedback Oupu 11 OUT1 O Oupu 1 12 OUT2 O Oupu 2 13 OUT3 O Oupu 3 14 NC Pin no conneced Exposed Pad GND 1) Exposed Pad; connec o GND in applicaion 1) Connec all GND-pins ogeher. Daa Shee 5 Rev. 1.2

6 General Produc Characerisics 4 General Produc Characerisics 4.1 Absolue Maximum Raings Absolue Maximum Raings 1) T j = -40 C o +150 C; all volages wih respec o ground, posiive curren flowing ino pin for inpu pins (I), posiive currens flowing ou of he I/O and oupu pins (O) (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Max. Volages Supply volage V S V Inpu volage EN V EN V Inpu volage EN relaed o V S V EN(VS) V S - 40 V S + 16 V Inpu volage EN relaed o V OUTx V EN V V EN - V OUTx V OUTx Oupu volage V OUTx V Power sage volage V PS V V PS = V S - V OUTx Inpu volage PWMI V PWMI V IN_SET volage V IN_SET V N-1 volage V N V Feedback volage V FB V Currens IN_SET curren I IN_SET 1) No subjec o producion es, specified by design 2) ESD suscepibiliy, Human Body Model HBM according o ANSI/ESDA/JEDEC JS ) ESD suscepibiliy, Charged Device Model CDM according o JESD22-C101E Noe: Sresses above he ones lised here may cause permanen damage o he device. Exposure o absolue maximum raing condiions for exended periods may affec device reliabiliy. 2 8 ma Diagnosis oupu N-1 curren I N ma Feedback curren I FB 0.5 ma Oupu curren I OUTx 130 ma Temperaures Juncion emperaure T j C Sorage emperaure T sg C ESD Suscepibiliy ESD resisiviy o GND V ESD -2 2 kv Human Body Model (100 pf via 1.5 kω) 2) ESD resisiviy all pins o GND V ESD V CDM 3) ESD resisiviy corner pins o GND V ESD V CDM 3) Daa Shee 6 Rev. 1.2

7 General Produc Characerisics Noe: Inegraed proecion funcions are designed o preven IC desrucion under faul condiions described in he daa shee. Faul condiions are considered as ouside normal operaing range. Proecion funcions are no designed for coninuous repeiive operaion. 4.2 Funcional Range Pos. Parameer Symbol Limi Values Uni Condiions Min. Max Supply volage range for V S(nom) V normal operaion Power on rese hreshold V S(POR) 5 V V EN = V S R SET =12kΩ I OUTx = 80% I OUTx(nom) V OUTx =2.5V Juncion emperaure T j C Noe: Wihin he funcional range he IC operaes as described in he circui descripion. The elecrical characerisics are specified wihin he condiions given in he relaed elecrical characerisics able. 4.3 Thermal Resisance Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max Juncion o Case R hjc 8 10 K/W 1) 2) Juncion o Ambien 1s0p board R hja Juncion o Ambien 2s2p board R hja2 1) No subjec o producion es, specified by design. Based on simulaion resuls. 2) Specified R hjc value is simulaed a naural convecion on a cold plae seup (all pins and he exposed Pad are fixed o ambien emperaure). T a = 85 C, Toal power dissipaion 1.5 W. 3) The R hja values are according o Jedec JESD51-3 a naural convecion on 1s0p FR4 board. The produc (chip + package) was simulaed on a 76.2 x x 1.5 mm 3 board wih 70 µm Cu, 300 mm 2 cooling area. Toal power dissipaion 1.5 W disribued saically and homogenously over all power sages. 4) The R hja values are according o Jedec JESD51-5,-7 a naural convecion on 2s2p FR4 board. The produc (chip + package) was simulaed on a 76.2 x x 1.5 mm 3 board wih 2 inner copper layers (ouside 2 x 70 µm Cu, inner 2 x 35 µm Cu). Where applicable, a hermal via array under he exposed pad conaced he firs inner copper layer. Toal power dissipaion 1.5 W disribued saically and homogenously over all power sages K/W 1) 3) K/W 1) 4) T a =85 C T a = 135 C T a =85 C T a = 135 C Daa Shee 7 Rev. 1.2

8 EN Pin 5 EN Pin The EN pin is a dual funcion pin: Inernal Supply EN Oupu Conrol V EN Figure 3 Block Diagram EN pin Noe: The curren consumpion a he EN-pin I EN needs o be added o he oal device curren consumpion. The oal curren consumpion is he sum of he currens a he VS-pin I S and he EN-pin I EN. 5.1 EN Funcion If he volage a he pin EN is below a hreshold of V EN(off) he LITIX Basic IC will ener Sleep mode. In his sae all inernal funcions are swiched off, he curren consumpion is reduced o I S(sleep). A volage above V EN(on) a his pin enables he device afer he Power on rese ime POR. V S V EN I OUT POR 100% 80% Figure 4 Power on rese Daa Shee 8 Rev. 1.2

9 EN Pin 5.2 Inernal Supply Pin The EN pin can be used o supply he inernal logic. There are wo ypical applicaion condiions, where his feaure can be used: 1) In DC/DC conrol Buck configuraions, where he volage V s can be below 5.5V (see Figure 20 for deails). 2) In configuraions, where a PWM signal is applied a he Vba pin of a ligh module. The buffer capacior C BUF is used o supply he LITIX Basic IC during Vba low (V s low) periods. This feaure can be used o minimize he urn-on ime o he values specified in Pos Oherwise, he power-on rese delay ime POR (Pos ) has o be considered. The capacior can be calculaed using he following formula: C BUF = I EN( LS) LOW( max) V S V D1 V SPOR ( ) See also a ypical applicaion drawing in Chaper 11. (1) V BATT GND CBUF D1 EN IN_SET VS Inernal supply Thermal proecion Curren adjusmen Oupu conrol OUT3 OUT2 OUT1 RSET LITIX Basic GND Figure 5 Exernal circui when applying a fas PWM signal on V BATT Daa Shee 9 Rev. 1.2

10 EN Pin V EN V BATT IOUT ON(VS) 100% 80% Swich off behavior depends on V BATT and load characerisics 20% Figure 6 Typical waveforms when applying a fas PWM signal on V BATT The parameer ON(VS) is defined a Pos The parameer OFF(VS) depends on he load and supply volage V BATT characerisics. 5.3 EN Unused In case of an unused EN pin, here are wo differen ways o connec i: EN - Pull Up o VS The EN pin can be conneced wih a pull up resisor (e.g. 10 kω) o V s poenial. In his configuraion he LITIX Basic IC is always enabled EN - Direc Connecion o VS The EN pin can be conneced direcly o he VS pin (IC always enabled). This configuraion has he advanage (compared o he configuraion described in Chaper 5.3.1) ha no addiional exernal componen is required. Daa Shee 10 Rev. 1.2

11 PWMI Pin 6 PWMI Pin The PWMI pin is designed as a dual funcion pin. PWMI I PWMI(L) Oupu Conrol V PWMI Figure 7 Block Diagram PWMI pin The pin can be used for PWM-dimming via a push-pull sage of a micro conroller, which is connecing he PWMI-pin o a low or high poenial. Noe: The micro conroller s push-pull sage has o able o sink currens according o Pos o acivae he device. Furhermore, he device offers also an inernal PWM uni by connecing an exernal-rc nework according o Figure PWM Dimming A PWM signal can be applied a he PWMI pin for LED brighness regulaion. The dimming frequency can be adjused in a very wide range (e.g. 400 Hz). The PWMI pin is low acive. Turn on/off hresholds V PWMI(L) and V PWMI(H) are specified in parameers Pos and Pos V PWMI IOUT ON(PWMI ) OFF(PWMI ) 100% 80% 20% Figure 8 Turn on and Turn off ime for PWMI pin usage Daa Shee 11 Rev. 1.2

12 PWMI Pin 6.2 Inernal PWM Uni Connecing a resisor and a capacior in parallel on he PWMI pin enables he inernal pulse widh modulaion uni. The following figure shows he charging and discharging defined by he RC-nework according o and he inernal PWM uni. V PWMI Oupus OFF V PWMI(H) Inernal PWM V PWMI(L) Oupus ON OUT- ON OUT - OFF OUT- ON OUT - OFF OUT- ON OUT - OFF OUT- ON OUT - OFF Figure 9 PWMI operaing volages The PWM Duy cycle (DC) and he PWM frequency can be adjused using he formulas below. Please use only ypical values of V PWMI(L), V PWMI(H) and I PWMI(on) for he calculaion of PWMI(on) and PWMI(off) (as described in Pos o Pos ). PWMI( on) = R PWMI off PWMI C PWMI LN V PWMI( H) I PWMI( on) R PWMI ( ) R PWMI CPWMI LN V PWMI ( H ) = 1 f PWMI = DC = PWMI( on) PWMI( off) PWMI( on) f PWMI V PWMI( L) I PWMI( on) R PWMI V PWMI( L) Ou of his equaions he required C PWMI and R PWMI can be calculaed: (2) (3) (4) (5) I PWMI on V ( ) PWMI L ( ) PWMI( off) V PWMI( H) PWMI( on) PWMI( off) 1 C PWMI = LN V PWMI ( L ) V PWMI( H) V V PWMI ( L ) PWMI( L) V PWMI( H) PWMI( on) PWMI( off) V PWMI( H) (6) R PWMI PWMI( off) = C PWMI LN V PWMI ( H ) V PWMI( L) (7) See Figure 10 for a ypical exernal circuiry. Daa Shee 12 Rev. 1.2

13 PWMI Pin Noe: In case of juncion emperaures above T j(crt) (Pos ) he device provides a emperaure dependen curren reducion feaure as descirbed in Chaper In case of oupu curren reducion I IN_SET is reduced as well, which leads o increased urn on-imes PWMI(on), because he C PWMI is charged slower. The urn off-ime PWMI(off) remains he same. V BATT GND 10 kω VS EN Inernal supply PWMI N-1 Thermal proecion Oupu conrol OUT3 OUT2 RPWM I CPWM I CN-1 IN_SET Curren adjusmen OUT1 RSET LI TIX Basic DC/DC conrol FB GND Figure 10 Typical circui using inernal PWM uni 6.3 Elecrical Characerisics Inernal Supply / EN / PWMI Pin Elecrical Characerisics Inernal Supply / EN / PWMI pin Unless oherwise specified: V S = 5.5 V o 40 V, T j = -40 C o +150 C, R SET =12kΩ all volages wih respec o ground, posiive curren flowing ino pin for inpu pins (I), posiive currens flowing ou of he I/O and oupu pins (O) (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max Curren consumpion, sleep mode Curren consumpion, acive mode I S(sleep) µa I S(on) ma 1) V EN = 0.5 V T j < 85 C V S = 18 V V OUTx = 3.6 V 2) V PWMI = 0.5 V I IN_SET = 0µA T j < 105 C V S = 18 V V OUTx = 3.6V V EN =5.5V V EN =18V 1) R EN = 10 kω beween VS and EN-pin Daa Shee 13 Rev. 1.2

14 PWMI Pin Elecrical Characerisics Inernal Supply / EN / PWMI pin (con d) Unless oherwise specified: V S = 5.5 V o 40 V, T j = -40 C o +150 C, R SET =12kΩ all volages wih respec o ground, posiive curren flowing ino pin for inpu pins (I), posiive currens flowing ou of he I/O and oupu pins (O) (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max Curren consumpion, device disabled via IN_SET Curren consumpion, device disabled via PWMI Curren consumpion, acive mode in single faul deecion condiion Power-on rese delay ime 3) Required supply volage for oupu acivaion Required supply volage for curren conrol I S(dis,IN_SET) I S(dis,PWMI) I S(faul) ma ma ma POR 25 µs 2) V S = 18 V T j < 105 C V IN_SET = 5 V V EN =5.5V V EN =18V 1) R EN = 10 kω beween VS and EN-pin 2) V S = 18 V T j < 105 C V PWMI = 3.4 V V EN =5.5V V EN =18V 1) R EN = 10 kω beween VS and EN-pin 2) V S = 18 V T j < 105 C R SET = 12 kω V PWMI = 0.5 V V OUTx = 18 V V EN =5.5V V EN =18V 1) R EN = 10 kω beween VS and EN-pin 1) V S = V EN = V V OUTx(nom) = 3.6 ± 0.3V I OUTx = 80% I OUTx(nom) V S(on) 4 V V EN = 5.5 V V OUTx = 3 V I OUTx = 50% I OUTx(nom) V S(CC) 5.2 V V EN = 5.5 V V OUTx = 3.6 V I OUTx 90% I OUTx(nom) EN urn on hreshold V EN(on) 2.5 V EN urn off hreshold V EN(off) 0.8 V EN inpu curren during low supply volage I EN(LS) 1.8 ma 1) V S = 4.5 V T j < 105 C V EN = 5.5 V Daa Shee 14 Rev. 1.2

15 PWMI Pin Elecrical Characerisics Inernal Supply / EN / PWMI pin (con d) Unless oherwise specified: V S = 5.5 V o 40 V, T j = -40 C o +150 C, R SET =12kΩ all volages wih respec o ground, posiive curren flowing ino pin for inpu pins (I), posiive currens flowing ou of he I/O and oupu pins (O) (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max EN high inpu curren I EN(H) PWMI (acive low) Swiching low hreshold (oupus on) PWMI(acive low) Swiching high hreshold (oupus off) PWMI Swiching hreshold difference V PWMI(H) - V PWMI(L) PWMI (acive low) Low inpu curren wih acive channels (volage <V PWMI(L) ) PWMI(acive low) High inpu curren V PWMI(L) V ma T j < 105 C V S = 13.5 V, V EN = 5.5 V V S = 18 V, V EN = 5.5 V V S = V EN = 18 V 1) V S = 18 V, R EN = 10 kω beween VS and EN-pin 1)4) V S = V V PWMI(H) V 1)4)5) V S = V V PWMI V 1)4)5) V S = V I PWMI(on) I IN_SET *3.1 I IN_SET *4 I IN_SET *4.9 µa 1) T j = C I IN_SET = 100 µa V PWMI = 1.7 V V EN = 5.5 V V S = V I PWMI(off) -5 5 µa V PWMI = 5 V V EN = 5.5 V V S = V 1) No subjec o producion es, specified by design 2) The oal device curren consumpion is he sum of he currens I S and I EN(H), please refer o Pos ) See also Figure 4 4) Parameer valid if an exernal PWM signal is applied 5) If TTL level compaibiliy is required, use µc open drain oupu wih pull up resisor Daa Shee 15 Rev. 1.2

16 FB Pin 7 FB Pin The following block diagram shows he feedback pin funcionaliy. OUT1 OUT2 OUT3 Oupu volage feedback I FB(SOC) FB Figure 11 Block Diagram FB pin 7.1 DC/DC Conrol Wih he FB pin he LITIX Basic IC realizes he dynamic overhead conrol. The IC provides a volage feedback o an exernal DC/DC converer. Using he circui shown in Figure 20 i is possible o adjus he DC/DC oupu volage in a way ha he volage drop over he oupu sages of he LITIX Basic IC is minimized - dynamic overhead conrol. This leads o a significan reducion of he overall driver s power dissipaion and an increased sysem efficiency. Figure 21 shows he same concep bu, using a higher number of LEDs per LED chain (please noe ha he cahode of he LED chain is conneced o V IN ). Noe: For correc oupu curren conrol and dynamic overhead conrol he parameers as specified in Pos and Pos need o be considered. FB source currens higher han given in Pos lead o a drop of he FB regulaion volage V FB(nom). The resisor R FB(PD) can be dimensioned by applying equaions Equaion (8) and Equaion (9). The following parameers are required: V OUT represens he maximum LED loads forward volage, i.e. number of LEDs muliplied wih he maximum LED forward volage. Temperaure drifs of he LED s forward volage needs o be considered! V BO represens he DC/DC oupu volage, which is predefined by he feedback resisors (Figure 20: R FB1, R FB2, R FB3 Figure 21: R FB1, R FB2, R FB3 ). Please refer o he according DC/DC device daa shee for he dimensioning of hose resisors. n len represens he numbers of LITIX Basics using he longes LED-chains (e.g. if here are 3 devices conneced o one DC/DC converer and wo devices using LED chains wih 7 LEDs and one device is used wih LED chain lenghs of 6 LEDs he according n len =2.) β represens he DC gain of he exernal bipolar ransisor, which is conneced o he DC/DC s feedback pin. ( ) min V OUT 0.5 V V Ω = {, } A n len V BO V OUT 1.1 V n len R FB PD, min V OUT 1.1 V ( ) = V BO V OUT β + 1 R FB PD, max R FB1 V OUT (8) (9) Daa Shee 16 Rev. 1.2

17 FB Pin 7.2 Elecrical Characerisics FB Pin Elecrical Characerisics FB pin Unless oherwise specified: V S = 5.5 V o 40 V, T j = -40 C o +150 C, R SET =12kΩ, all volages wih respec o ground, posiive curren flowing ino pin for inpu pins (I), posiive currens flowing ou of he I/O and oupu pins (O) (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max FB regulaion volage V FB(nom) (V OUT - V OUT -1 V I FB(SOC) = 25 µa 1)* FB operaing volage a power sage V PS(FB) = V S - V OUTx V PS(FB) 10 V 1) 1) No subjec o producion es, specified by design Daa Shee 17 Rev. 1.2

18 IN_SET Pin 8 IN_SET Pin The IN_SET pin is a muliple funcion pin for oupu curren definiion, inpu and diagnosics: IN_SET Logic I IN_SET V IN_SET V IN_SET(N-1) GND Figure 12 Block Diagram IN_SET pin 8.1 Oupu Curren Adjusmen via RSET The oupu curren for all hree channels can only be adjused simulaneously. The curren adjusmen can be done by placing a low power resisor (R SET ) a he IN_SET pin o ground. The dimensioning of he resisor can be done using he formula below: R SET k = I OUT (10) The gain facor k (R SET * oupu curren) is specified in Pos and Pos The curren hrough he R SET is defined by he resisor iself and he reference volage V IN_SET(ref), which is applied o he IN_SET during supplied device. 8.2 Smar Inpu Pin The IN_SET pin can be conneced via R SET o he open-drain oupu of a µc or o an exernal NMOS ransisor as described in Figure 13. This signal can be used o urn off he oupu sages of he IC. A minimum IN_SET curren of I IN_SET(ac) is required o urn on he oupu sages. This feaure is implemened o preven glimming of LEDs caused by leakage currens on he IN_SET pin, see Figure 15 for deails. In addiion, he IN_SET pin offers he diagnosic feedback informaion. In case of a faul even he IN_SET volage is increased o V IN_SET(N- Pos Therefore, he device has wo volage domains a he IN_SET-pin, which is shown in Figure 16. 1) Daa Shee 18 Rev. 1.2

19 IN_SET Pin Microconroller (e.g. XC866) OUT R SET /2 R SET /2 IN_SET Curren adjus Basic LED Driver GND V DDP = 5 V IN Figure 13 Schemaics IN_SET inerface o µc The resuling swiching imes are shown in Figure 14: I IN_SET IOUT ON(IN_SET ) OFF(IN_SET) 100% 80% 20% Figure 14 Swiching imes via IN_SET Daa Shee 19 Rev. 1.2

20 IN_SET Pin I OUT [ma] k = I OUTx * V IN_SET(ref) / I IN_SETx I OUTx I IN_SET(ACT) I IN_SETx I IN_SET [µa] Figure 15 I OUT versus I INSET V IN_SET V IN_SET(N-1)max Diagnosic volage range V IN_ SET(N -1) m in V IN _SET(ref )max Normal operaion and high emperaure curren reducion range Figure 16 Volage domains for IN_SET pin, if ST pin is conneced o GND Daa Shee 20 Rev. 1.2

21 Load Diagnosis 9 Load Diagnosis 9.1 N-1 Deecion The N-1 diagnosis is specially designed o deec error condiions in LED arrays wih muliple LED chains used for one ligh funcion. If one LED wihin one chain fails in open condiion he respecive LED chain is off. Differen auomoive applicaions require a complee deacivaion of a ligh funcion, if he desired brighness of he funcion (LED array) can no be achieved due o an inernal error condiion. Such a deacivaion feaure is inegraed in he LITIX Basic IC. The funcionaliy of he N-1 pin is shown in he following block diagram: N-1 I N-1 Oupu Conrol V N-1 Figure 17 Block Diagram N-1 pin In applicaions, where more han one LITIX Basic IC is used, he IN_SET pins can be conneced via he PWMI pins as shown in Figure 20 and Figure 21. This circui can be used o disable all oupu sages (of all LITIX Basic ICs) during an open load even on one channel. The oupus are deacivaed afer a N-1 filer ime N-1, which is defined by he charging curren I N-1 (Pos ). The ime is adjusable wih a capacior conneced o he N-1 pin according he following equaion: C N 1 V N 1( h) yp = I N 1 (11) Daa Shee 21 Rev. 1.2

22 Load Diagnosis V EN VEN(on) V EN(off ) V IN_SET V IN _SET(N-1) Slope depends on R SET VIN_SET(ref ) V N-1 V N- 1(h ) V OUT N-1 V S VS VPS(N-1) V F ON(EN) open load occurs open load disappears Figure 18 IN_SET behavior during open load condiion The N-1 saus is lached. The oupu sages can be re-enabled by a Low o High ransiion a he EN pin or by a Power on rese. To provide a Limp Home funcionaliy (lower number of LEDs insead of complee deacivaion) in he case of a parially damaged LED array, he N-1 filer ime N-1 can be used. If a PWM signal wih an ON-ime of less han N-1 is applied o he VS and EN pins, he N-1 deecion feaure will no be acivaed. If here is more han one device used for N-1 deecion he maximum number of devices, which can be conneced as shown in Figure 20 and Figure 21, is limied o n N-1. The maximum number of devices in N-1 Daa Shee 22 Rev. 1.2

23 Load Diagnosis configuraion is calculaed according o Equaion (12), and he precondiion of Equaion (13) has o be fulfilled. The pull-down resisor R PWMI is calculaed according o Equaion (14) and Equaion (15). V I PWMI( H, max) + V F IN_SET(OL,min) R SET(min) n N 1 V PWMI H, max V PWMI( H, min) R SET(min) ( ) 4 V IN_SET(max) V PWMI( H, min) V IN_SET(min) RSET(min) ( V IN_SET(max) ) 2 > 1 R SET(max) (12) (13) R PWMI(min) = V PWMI( H, max) V I PWMI( H, max) + V F IN_SET(OL,min) R SET(max) (14) R PWMI(max) V PWMI( H, min) = n N 1 4 V IN_SET(max) R SET(min) (15) V F represens he volage drop across he diode beween he IN_SET- and he PWMI-pin. Noe: If one channel of he device should no be used, he according oupu needs o be conneced o GND, which leads o a disabling of his oupu. Noe: In case of a double faul, where he loads of wo channels are fauly a he same ime, he device operaes as in normal operaion. This feaure is implemened o avoid any unwaned swich off during significan supply volage drops. Please refer o Chaper Double Faul Condiions The has an inegraed double faul deecion feaure. This feaure is implemened o deec significan supply volage drops. During such supply volage drops close o he forward volage of he LEDs he drivers oupus remain acive. In case of load fauls on wo or more oupus wihin he ime period N-1 he device disables he diagnosis o avoid any uncorrec open load diagnosis during low supply volages close o he forward volages of he conneced LED chains. If he fauls beween wo or hree channels happen wih a delay of longer han OL he double faul deecion feaure is no acive, i.e. he device is no urned on. 9.3 Elecrical Characerisics IN_SET Pin and Load Diagnosis Elecrical Characerisics IN_SET pin and Load Diagnosis Unless oherwise specified: V S = 5.5 V o 40 V, T j = -40 C o +150 C, R SET = 12 kω, all volages wih respec o ground, posiive curren flowing ino pin for inpu pins (I), posiive currens flowing ou of he I/O and oupu pins (O) (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max IN_SET reference volage V IN_SET(ref) V 1) V OUTx =3.6V T j = C IN_SET N_1 volage V IN_SET(N-1) V 1) V S > 8 V T j = C V S = V OUTx (OL) x Daa Shee 23 Rev. 1.2

24 Load Diagnosis Elecrical Characerisics IN_SET pin and Load Diagnosis (con d) Unless oherwise specified: V S = 5.5 V o 40 V, T j = -40 C o +150 C, R SET = 12 kω, all volages wih respec o ground, posiive curren flowing ino pin for inpu pins (I), posiive currens flowing ou of he I/O and oupu pins (O) (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max IN_SET N_1 volage V IN_SET(N-1) V 1) V S = 5.5 V T j = C V S = V OUTx (OL) x IN_SET N_1 curren I IN_SET(N-1) ma 1) V S > 8 V T j = C V IN_SET = 4 V V S = V OUTx (OL) N-1 high hreshold V N-1(h) V V S > 8 V N-1 oupu curren I N µa V S > 8 V V N-1 = 2 V N-1 deecion volage V PS(N-1) V V S >8V V PS(N-1) = V S - V OUTx IN_SET acivaion curren wihou urn on of oupu sages I IN_SET(ac) 2 15 µa See Figure 15 1) No subjec o producion es, specified by design Daa Shee 24 Rev. 1.2

25 Power Sage 10 Power Sage The oupu sages are realized as high side curren sources wih a curren of 120 ma. During off sae he leakage curren a he oupu sage is minimized in order o preven a slighly glowing LED. The maximum curren of each channel is limied by he power dissipaion and used PCB cooling areas (which resuls in he applicaions R hja ). For an operaing curren conrol loop he supply and oupu volages according o he following parameers have o be considered: Required supply volage for curren conrol V S(CC), Pos Volage drop over oupu sage during curren conrol V PS(CC), Pos Required oupu volage for curren conrol V OUTx(CC), Pos Proecion The device provides embedded proecive funcions, which are designed o preven IC desrucion under faul condiions described in his daa shee. Faul condiions are considered as ouside normal operaing range. Proecive funcions are neiher designed for coninuous nor for repeiive operaion Over Load Behavior An over load deecion circui is inegraed in he LITIX Basic IC. I is realized by a emperaure monioring of he oupu sages (OUTx). As soon as he juncion emperaure exceeds he curren reducion emperaure hreshold T j(crt) he oupu curren will be reduced by he device by reducing he IN_SET reference volage V IN_SET(ref). This feaure avoids LED s flickering during saic oupu overload condiions. Furhermore, i proecs LEDs agains over emperaure, which are mouned hermally close o he device. If he device emperaure sill increases, he hree oupu currens decrease close o 0 A. As soon as he device cools down he oupu currens rise again. I OUT V IN_SET T j(crt) T j Figure 19 Oupu curren reducion a high emperaure Noe: This high emperaure oupu curren reducion is realized by reducing he IN_SET reference volage volage (Pos ). In case of very high power loss applied o he device and very high juncion emperaure he oupu curren may drop down o I OUTx = 0 ma, afer a sligh cooling down he curren increases again Reverse Baery Proecion The has an inegraed reverse baery proecion feaure. This feaure proecs he driver IC iself, bu also conneced LEDs. The oupu reverse curren is limied o I OUTx(rev) by he reverse baery proecion. Daa Shee 25 Rev. 1.2

26 Power Sage Noe: Due o he reverse baery proecion a reverse proecion diode for he ligh module may be obsolee. In case of high ISO-pulse requiremens and only minor proecing componens like capaciors a reverse proecion diode may be reasonable. The exernal proecion circui needs o be verified in he applicaion Elecrical Characerisics Power Sage Elecrical Characerisics Power Sage Unless oherwise specified: V S = 5.5 V o 18 V, T j = -40 C o +150 C, V OUTx = 3.6 V, all volages wih respec o ground, posiive curren flowing ino pin for inpu pins (I), posiive currens flowing ou of he I/O and oupu pins (O) (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max Oupu leakage curren I OUTx(leak) Oupu leakage curren in boos over baery seup 7 3 µa V EN = 5.5 V I IN_SET = 0µA V OUTx =2.5V T j = 150 C 1) T j = 85 C - 50 µa 1) V EN = 5.5 V I OUTx(leak,B2B) I IN_SET =0µA V OUTx = V S = 40 V Reverse oupu curren -I OUTx(rev) 1 µa Oupu curren accuracy limied emperaure range Oupu curren accuracy over emperaure Volage drop over power sage during curren conrol V PS(CC) = V S - V OUTx Required oupu volage for curren conrol k LT k ALL V PS(CC) 0.75 V V OUTx(CC) 2.3 V 1) V S = -16 V Oupu load: LED wih break down volage <-0.6V 1) T j = C V S = V V PS = 2 V R SET = kω R SET = 30 kω 1) T j = C V S = V V PS = 2 V R SET = kω R SET = 30 kω 1) V S = 13.5 V R SET = 12 kω I OUTx 90% of (k LT(yp) /R SET ) 1) V S = 13.5 V R SET = 12 kω I OUTx 90% of (k LT(yp) /R SET ) Daa Shee 26 Rev. 1.2

27 Power Sage Elecrical Characerisics Power Sage (con d) Unless oherwise specified: V S = 5.5 V o 18 V, T j = -40 C o +150 C, V OUTx = 3.6 V, all volages wih respec o ground, posiive curren flowing ino pin for inpu pins (I), posiive currens flowing ou of he I/O and oupu pins (O) (unless oherwise specified) Pos. Parameer Symbol Limi Values Uni Condiions Min. Typ. Max Maximum oupu curren I OUT(max) 120 ma R SET = 4.7 kω The maximum oupu curren is limied by he hermal condiions. Please refer o Pos Pos PWMI urn on ime ON(PWMI) 15 µs 2) V S = 13.5 V R SET = 12 kω PWMI L I OUTx = 80% of (k LT(yp) /R SET ) PWMI urn off ime OFF(PWMI) 10 µs 2) V S = 13.5 V R SET = 12 kω PWMI H I OUTx = 20% of (k LT(yp) /R SET ) IN_SET urn on ime ON(IN_SET) 15 µs V S = 13.5 V I IN_SET = µa I OUTx = 80% of (k LT(yp) /R SET ) IN_SET urn off ime OFF(IN_SET) 10 µs V S = 13.5 V I IN_SET = 100 0µA I OUTx = 20% of (k LT(yp) /R SET ) VS urn on ime ON(VS) 20 µs 1) 3) V EN =5.5V R SET = 12 kω V S = V I OUTx = 80% of (k LT(yp) /R SET ) Curren reducion emperaure hreshold Oupu curren during curren reducion a high emperaure T j(crt) 140 C 1) I OUTx = 95% of (k LT(yp) /R SET ) I OUT(CRT) 1) No subjec o producion es, specified by design 2) see also Figure 8 3) see also Figure 6 85% of (k LT(yp) /R SET ) A 1) R SET =12kΩ T j = 150 C Daa Shee 27 Rev. 1.2

28 2 1 LITIX Basic Applicaion Informaion 11 Applicaion Informaion Noe: The following informaion is given as a hin for he implemenaion of he device only and shall no be regarded as a descripion or warrany of a cerain funcionaliy, condiion or qualiy of he device. VBATT L1 CSEPIC DBO VBO RSET RSET CIN VIVCC IN TLD5097 SET EN / PWMI FREQ / SYNC SWO SWCS SGND OVFB FBH RSWCS L2 CBO ROV1 ROV2 RFB3 RFB2 RFB1 1 nf RFB(PD) CN-1 RSET CVS = 4.7 nf VS Inernal supply EN Thermal proecion PWMI N- 1 IN_SET Curren adjus LITIX Basic VBO Oupu conrol OUT 3 OUT 2 OUT 1 DC/ DC conrol FB GND 4.7 nf** 4. 7 nf** 4. 7 nf** RFREQ RCOMP CCOMP COMP ST CIN GND FBL IVCC CIVCC DPOL RPOL CVS = 4.7 nf EN VS Inernal supply Thermal proecion Oupu conrol OUT 3 4.7nF** 4.7 nf** 4. 7 nf** PWMI OUT 2 CN-1 RSET N-1 IN _ SET Curren adjus LITIX Basic OUT 1 DC / DC conrol FB GND ** For EMI improvemen, if required. Figure 20 Sysem diagram DC/DC conrol SEPIC + N-1 deecion Daa Shee 28 Rev. 1.2

29 Applicaion Informaion D RV L BO DBO V IN VBO V BATT CIN IN ST TLD5095 SWO SWCS SGND OVFB R CS C BO TSW R OVH R OVL R FB1 CVS=4.7nF VS 10kΩ Inernal supply EN Thermal proecion PWMI N-1 CN-1 IN_SET Curren adjus LITIX Basic RSET Oupu conrol OUT3 OUT2 OUT1 DC/ DC conrol FB GND 4.7nF** 4.7nF** 4.7nF** C COMP EN / PWMI FREQ / SYNC COMP IVCC FBH FBL R FB2 RPWMI VBO V IN RFREQ RCOMP CIVCC PWMO GND R FB3 1nF 10kΩ CVS=4.7nF VS Inernal supply EN Thermal proecion PWMI Oupu conrol OUT3 OUT2 4.7nF** 4.7nF** 4.7nF** N-1 OUT1 RFB(PD) RSET CN-1 IN_SET Curren adjus LITIX Basic DC/ DC conrol FB GND VIN * For EMI improvemen, if required, 10nF Figure 21 Sysem diagram DC/DC conrol Boos + N-1 deecion Noe: This is a very simplified example of an applicaion circui. The funcion mus be verified in he real applicaion Furher Applicaion Informaion For furher informaion you may conac hp:// Daa Shee 29 Rev. 1.2

30 Package Oulines 12 Package Oulines Sand Off (1.45) 1.7 MAX. C 0.08 C 0.35 x ±0.1 1) 0.1 C D ± MAX ±0.05 2) 0.15 M C A-B D 14x D 6 ± M D 8x Boom View A B 0.1 C A-B 2x 4.9 ±0.1 1) Exposed Diepad 3 ± ±0.2 Index Marking 1) Does no include plasic or meal prorusion of 0.15 max. per side 2) Does no include dambar prorusion Dimensions in mm PG-SSOP-14-1,-2,-3-PO V02 Figure 22 PG-SSOP-14 Green Produc (RoHS complian) To mee he world-wide cusomer requiremens for environmenally friendly producs and o be complian wih governmen regulaions he device is available as a green produc. Green producs are RoHS-Complian (i.e Pb-free finish on leads and suiable for Pb-free soldering according o IPC/JEDEC J-STD-020). For furher informaion on alernaive packages, please visi our websie: hp:// Daa Shee 30 Rev. 1.2

31 Revision Hisory 13 Revision Hisory Revision Dae Changes Inial revision of daa shee Updaed parameers K LT and K ALL in he chaper Power Sage 1.2 Updaed o laes emplae 1.2 Updaed applicaion drawing 1.2 Updaed package marking 1.2 Updaed package figure 1.2 Updaed Chaper Updaed Figure 20 Daa Shee 31 Rev. 1.2

32 Table of Conens 1 Overview Block Diagram Pin Configuraion Pin Assignmen Pin Definiions and Funcions General Produc Characerisics Absolue Maximum Raings Funcional Range Thermal Resisance EN Pin EN Funcion Inernal Supply Pin EN Unused EN - Pull Up o VS EN - Direc Connecion o VS PWMI Pin PWM Dimming Inernal PWM Uni Elecrical Characerisics Inernal Supply / EN / PWMI Pin FB Pin DC/DC Conrol Elecrical Characerisics FB Pin IN_SET Pin Oupu Curren Adjusmen via RSET Smar Inpu Pin Load Diagnosis N-1 Deecion Double Faul Condiions Elecrical Characerisics IN_SET Pin and Load Diagnosis Power Sage Proecion Over Load Behavior Reverse Baery Proecion Elecrical Characerisics Power Sage Applicaion Informaion Furher Applicaion Informaion Package Oulines Revision Hisory Table of Conens Daa Shee 32 Rev. 1.2

33 Trademarks All referenced produc or service names and rademarks are he propery of heir respecive owners. Ediion Published by Infineon Technologies AG Munich, Germany 2018 Infineon Technologies AG. All Righs Reserved. Do you have a quesion abou any aspec of his documen? erraum@infineon.com Documen reference IMPORTANT NOTICE The informaion given in his documen shall in no even be regarded as a guaranee of condiions or characerisics ("Beschaffenheisgaranie"). Wih respec o any examples, hins or any ypical values saed herein and/or any informaion regarding he applicaion of he produc, Infineon Technologies hereby disclaims any and all warranies and liabiliies of any kind, including wihou limiaion warranies of non-infringemen of inellecual propery righs of any hird pary. In addiion, any informaion given in his documen is subjec o cusomer's compliance wih is obligaions saed in his documen and any applicable legal requiremens, norms and sandards concerning cusomer's producs and any use of he produc of Infineon Technologies in cusomer's applicaions. The daa conained in his documen is exclusively inended for echnically rained saff. I is he responsibiliy of cusomer's echnical deparmens o evaluae he suiabiliy of he produc for he inended applicaion and he compleeness of he produc informaion given in his documen wih respec o such applicaion. For furher informaion on echnology, delivery erms and condiions and prices, please conac he neares Infineon Technologies Office ( WARNINGS Due o echnical requiremens producs may conain dangerous subsances. For informaion on he ypes in quesion please conac your neares Infineon Technologies office. Excep as oherwise explicily approved by Infineon Technologies in a wrien documen signed by auhorized represenaives of Infineon Technologies, Infineon Technologies producs may no be used in any applicaions where a failure of he produc or any consequences of he use hereof can reasonably be expeced o resul in personal injury.