Auto-zero stabilized CMOS amplifiers for very low voltage or current offset

Transcription

1 Auto-zero stabilized CMOS aplifiers for very low voltage or curret offset D. Dzahii, H. Ghazlae To cite this versio: D. Dzahii, H. Ghazlae. Auto-zero stabilized CMOS aplifiers for very low voltage or curret offset. S. Metzler. IEEE Nuclear Sciece Sypiu, Oct 2003, Portlad, Uited States. IEEE Nuclear ad Plasa Scieces Society, N1-2 (5 p.), <i2p > HAL Id: i2p Subitted o 3 Nov 2003 HAL is a ulti-discipliary ope access archive for the depit ad disseiatio of scietific research docuets, whether they are published or ot. The docuets ay coe fro teachig ad research istituti i Frace or abroad, or fro public or private research ceters. L archive ouverte pluridiscipliaire HAL, est destiée au dépôt et à la diffusio de docuets scietifiques de iveau recherche, publiés ou o, éaat des établisseets d eseigeet et de recherche fraçais ou étragers, des laboratoires publics ou privés.

2 Auto-zero stabilized CMOS aplifiers for very low voltage or curret offset Daiel Dzahii (1), Haid Ghazlae (2) (1) Laboratoire de Physique Subatoique et de Cologie 53 aveue des Martyrs, Greoble Cédex Frace (2) Cetre Natioal de l'eergie, des Scieces et des Techiques Nucléaires * BP 1382 Rabat Pricipal Morocco Abstract---I this paper, we preset two aplifiers desiged i CMOS techology ad icludig a auto-zero architecture for very low offset cotrol. The first desig is a high precisio operatioal aplifier focusig o the voltage offset. It is a cotiuous tie auto-zero stabilized architecture, that leads to a typical iput offset voltage of 2µV-100V/ C. The aplifier with its output buffer cues 5W at a supply voltage of /- 2.5V. The gai badwidth product is 2MHz while the slew rate is respectively -6V/µs ad 8.8V/µs o 10pF with 10KΩ load. This aplifier is suitable for the cotrol of large dyaic (>10 5 ) calibratio sigal, ad for very low DC sigal istruetatio. The secod desig is a curret ode charge pulse aplifier based o a secod geeratio pitive curret coveyor topology (CCII). The badwidth, the dyaic rage ad the output ipedace have bee optiized usig a ehaced cascode curret irror. The preaplifier provides two outputs: oe for the sigal itegratio, ad aother goig through a curret coparator for a digital coutig flow. The double hit resolutio is less tha 7s. A auto-zero copesatio has bee added to this preaplifier to cotrol its output curret offset dow to 60A. The total power dissipatio (preaplifier offset cacelatio coparator) is less tha 1W. This secod aplifier has bee desiged for low power space applicati, especially EUSO (Extree Uiverse Space Observatory), which use ultiaode PMT i the cofiguratio of a large gate tie (2.5µs) ope for charge itegratio. I. INTRODUCTION. Voltage offset is a very iportat paraeter for operatioal aplifiers used i ay applicati: calibratio sigal for high eergy physics, low sigal sesor iterfaces, high accuracy istruetatio. I the sae way, curret offset is crucial for curret coveyor aplifiers used i a itegrator cofiguratio. Auto-zero stabilizatio architecture is a efficiet ad elegat solutio for offset cacellatio. Also it helps to copesate the offset drift (with the tie, teperature, power supply etc.). Soe other advatages of autozero aplifiers iclude the psibility to feature a high ope loop gai ad a high CMRR/PSRR. CMOS techology is suitable for such a desig, due to its aalog switch capabilities, lower power architectures ad low ct. This auto-zero cocept has bee adapted ad siplified for a low power curret coveyor preaplifier desiged for the EUSO experiet aalog frot-ed. The output curret offset is crucial for this applicatio because it is cotiuously itegrated o the output capacitor with the sigal pulses, over a log tie of 2.5µs so called Gate Tie Uit (GTU). Hece the output sigal is: (I offset δi sigal ) * GTU/C out. The power dissipatio is a very iportat paraeter for this space applicatio, therefore the offset cacellatio loop ust cue a very low curret. This circuit has bee desiged i a 0.35µ CMOS process. A brief review of the auto-zero cocept is give i sectio II. The desig ad the results of the low voltage offset aplifiers are preseted i sectio III. The low curret offset aplifier desig ad testig results are give i sectio IV. II. AUTO-ZERO AMPLIFIER: OVERVIEW. A cotiuous tie auto-zero aplifier requires two iteral aplifiers [1]. The so called Mai aplifier is uswitched ad cotiuously available for the icoig sigal aplificatio (Figure 1). Null Mai Figure 1 Auto-zero aplifier block diagra Buffer The offset cacellatio cists of two alteratig successive phases. Durig the first oe, the Nullig aplifier is discoected fro the sigal path for its ow auto correctio. A correctio sigal V c is geerated ad held o capacitors C coected at the auxiliary iputs. Durig the secod phase, the Nullig aplifier is recoected to the Mai oe ad seses its iputs offset. Aother correctio voltage V c is geerated this way ad held o capacitor C for the Mai aplifier correctio. Each iteral aplifier (the Nullig ad the Mai) could be odelized with two differetial iputs: a priary ad a auxiliary oe as show i Figure 2. priary iput V i auxiliary iput V i V o Figure 2: Iteral aplifier odel

3 Fro this odel ca be ade the assuptio that the priary ad auxiliary iputs are cobied i the first stage of the aplifier, leadig to a output sigal V 0 (s) expressed as: ( s) A(s).Vi A'(s).V' i A(s). V V o = (1) where V is the offset voltage i the priary iput of the aplifier. Buffer III. INTERNAL AMPLIFIER FOR THE VOLTAGE OFFSET AUTO-ZERO AMPLIFIER A. Architecture The diagra show i figure 4 is used for both iteral aplifiers (the Mai ad the Null). Its geeral architecture is the folded cascode, to provide a high ope loop dc gai ad the capability to drive a large hold capacitor. A high-swig curret irror is used i the cascode aplificatio stage (M 7 -M 10 ) to iprove the badwidth ad the outpout dyaic rage, [3]. The high-swig curret irror will be described i detail i sectio IV-B. vdd! bias M18 M17 M9 M10 M1 vdd! M2 V V- Figure 3: Auto-zero aplifier i feedback loop bias2 va- M11 vdd! M12 va M7 vdd! M8 vout Cider ow the full auto-zero aplifier i a feedback loop cofiguratio as show i figure 3. V ad V are respectively the iheret offset of the Mai ad the Nullig iteral aplifiers. Vc ad Vc are the perturbatio voltages respectively o the capacitors C ad C, related to the charge ijectio, saplig oise ad leakage curret. Durig the phase φ 1, the switch S 1 short-circuits the Nullig aplifier, the its output stores a cotrol voltage V c o the capacitor C through the switch S 2. Durig the followig phase φ 2, the Null aplifier seses the offset of the V c o the Mai ad stores the resultig cotrol voltage capacitor C. After ay successive iterati of φ 1 ad φ 2 phases, the offset will decrease step by step. Let be the ctat ratio betwee the ope loop gais: = A /A ad = A /A (2) Oe ca detrate [2] that the iu value of the residual offset at the Mai aplifier iput is: V ( = ) V A' V V c V If the sae architecture is used for the Mai ad the Null aplifier, the = = ad A =A ; so V becoes: V V = V A' Vc Vc This voltage offset could be iiized with a large value for the auxiliary iputs ope loop gai A, (ore tha 40dB). Moreover, the sesitivity to the fluctuatio voltage V over the capacitors C ad C ca be liited by usig a iteral aplifier architecture that leads to a large value of the ratio, ad by usig also exteral large capacitace. c (4) (3) bias3 bias4 M13 M15 M14 vss! M16 Figure. 4. Iteral aplifier diagra The offset depeds aily o how the quiescet curret is well balaced through the priary differetial iput stage. This equilibriu is cotrolled fro the auxiliary iputs (V a, V a ). A offset cotrol sigal V at the auxiliary iputs will geerate a fluctuatio curret i aroud the quiescet poit i the log tail auxiliary aplifier. The the curret iror (M13,M14), respectively (M15,M16) will create a cotrol curret /- i i the priary stage which after the aplificatio stage will lead ito a offset chage V 0 after the cascode stage. Fro figure 4, oe ca write two equati for V 0 : V 0 = ( * i)/g * A = ( * g * V)/g * A; ad V 0 =A * V Therefore i this cofiguratio the paraeter is: = g /( * g ) where g ad g are respectively the trascoductace for the priary ad auxiliary iput pairs. A output buffer (coo source output stage ot described here) has bee added after the Mai aplifier output to ehace its drivig capability for resistive loads. The siulatio results i figure 5 detrate how i a feedback cofiguratio (as i figure 1), the copesatio is perfored step by step util the voltage offset see at the output is cled to the oise. A iput basic offset of -10V (ad respectively 10V) was take as worst case assuptio for the Mai ad Null aplifiers before the copesatio M3 M5 M6 M4

4 starts. The feedback loop gai is R0/R1=100, ad the saplig frequecy is 100Hz. Figure 5: Voltage offset copesatio step by step B. Experietal results This aplifier has bee desiged i a stadard 0.8µ process, ad 5 prototypes have bee tested. The ea value foud for the offset is less tha 2µV at hoe teperature. A evaluatio of a typical offset drift with the teperature is show i figure 6. Neither the i or the characteristics are liear. But fro the fittig curve a ea value for the drift aroud 100V/ C ca be oticed. Offset (µv) Fittig extrapolatio Experietal curve Teperature ( C) Figure 6: Offset drift with the teperature. The output ipedace of the ai aplifier s buffer was easured to be aroud 400 Ohs. The ope loop gai (fro the priary iputs to the buffer output) is better tha 100dB. The gai badwidth product is 2MHz while the slew rate is respectively -6V/µs ad 8.8V/µs o 10pF with 10KΩ load. Figure 7 shows the equivalet iput oise voltage spectru easured while the total power dissipatio was set at 5W (icludig the output buffer), ad the supply voltage was /- 2.5V. a iput oise voltage of 10V/ Hz beyod 30Khz ca be see. IV. CURRENT CONVEYOR AMPLIFIER WITH A CURRENT OFFSET AUTO-ZERO LOOP The followig sectio describes a secod desig where a auto-zero architecture is used. Curret coveyor preaplifiers have bee successfully used for ay physics applicati [4] [5] [6] where low oise, low power ad high speed were the ai cocer. I recet CMOS processes the low supply voltage becoes a further critical paraeter for the dyaic rage. The EUSO experiet uses a ultiaode PMT ad the frot-ed electroics icludes a digital flow for photo coutig, ad a aalog charge itegrator flow. So a curret coveyor preaplifier appears to be a good coproise. The output stage cists of two curret irrors: oe goig to a curret coparator for the coutig flow, ad the secod oe loaded by a capacitor for the output curret itegratio (see figure 9). Over ad above the low power cuptio, the ai features of this electroics are the tie double hit resolutio (for the coutig flow), the curret offset ad the dyaic rage (for the aalog flow). A. The curret offset auto-zero loop There is a short reset tie (40s) after each GTU itegratio tie (2.5µs). Durig the GTU, the preaplifier is discoected fro the auto-zero loop, lettig the base lie ctat. Durig each reset tie the preaplifier is discoected fro the output capacitor, ad the coected to aother capacitor where the output curret offset is itegrated. The resultig sigal is applied to oe iput of a low gai log tail aplifier which geerates the offset cotrol sigal that will be sapled ad stored o the gate of a trasistor. The curret flowig through this trasistor coes i parallel with the bias curret of the preaplifier s output stage. Therefore we have a offset cacellatio loop which is a cotrolled ad sapled curret copier i parallel with the ai bias curret [7]. Figure 8 shows soe siulatio results: the first curve is the curret offset through the output capacitor. Durig each reset tie (40s) the auto zero loop cotrols this offset, ad step by step reduces it dow to a few A. The secod curve is the sapled cotrol sigal goig o the gate of the trasisors which will iduce the offset cacellatio curret V/Hz1/ Frequecy (Hz) Figure 7: Equivalet iput oise voltage Figure 8: Curret offset cacellatio ad its cotrol sigal

5 Figure 9: Curret preaplifier with the offset cacellatio loop The offset Mote Carlo siulati are show i figure 10 for the preaplifier without ad with the auto-zero loop. (a) basic curret coveyor offset; (b) with the auto-zero loop Figure 10: Curret offset Mote Carlo siulati Over the process isatch we could expect a output curret offset spread fro oly -80A to 70A, istead of - 2uA to 1uA foud i the cofiguratio without the auto-zero loop i spite of usig trasistors with twice the iiu chael legth [8]. The differetial pair (figure 9) is biased with oly 10µA to save power cuptio, ad a great care was take i the layout to liit its ow offset. The logic sigals (reset, resetb, gtu, gtub) coe fro a o overlappig clock geerator cell itegrated iside the chip. The sequeces ad the edge of these sigals cotrollig the CMOS switches are carefully defied to liit the charge ijectio. This circuit has bee desiged i a.35µ CMOS process. The offset testig results statistics over a set of 10 prototypes are show i figure 11. It turs out that with the exceptio of oe chip which has a offset of 150A, this first prototypes set has a offset dispersio fro 50A to 60A. It is very cle to the Mote Carlo siulati of figure 10 (b), ad cofirs the efficiecy of the auto-zero loop. Figure 11: curret offset dispersio over 10 prototypes B. The wide swig curret irror The curret coveyor of figure 9 ad the aplifier described i figure 4 use both a curret irror architecture so called wide swig irror [9][10]. It is show i figure 12(b), beside the classical cascode. Figure 12: Classical cascode (a) ad wide swig curret irror (b) The cascode architecture is a easy way to icrease the output ipedace of a curret irror, ad thus to iprove the output curret accuracy over the dyaic rage. For both architectures, the output ipedace is: Ro = (δi out /δv out ) -1 = Ro (I2) Ro (I4) g (I2)* Ro (I2)* Ro (I4) g (I2)* Ro (I2)* Ro (I4)

6 Figure 13 shows how log this output ipedace is quite ctat, ad also poits at the differece of dyaic rage[]. For trasistors of equivalet size, ad with saturatio coditio for each oe (V ds >V gs V t ), it ca be detrated that the iiu voltage drop for the basic cascode is: V out =V t 2V dssat I the case of high swig structure, a careful choice of the bias voltage could lead ito a voltage drop of Vout=2V dssat. That akes a differece of oe V t, which is cofired also by the siulati of figure 13. Figure 13: Curret irror dyaic rage iproveet I the sae way, a suitable choice for the size of trasitors I 1 ad I 2, helps i iprovig the badwidth as show i figure14. Cequetly, the photo double hit tie resolutio was foud less tha 7s. Figure 14:Badwidth iproveet for curret irrors V. CONCLUSION Two aplifiers icludig a auto-zero loop have bee successfully desiged ad tested. The cotiuous tie offset cacellatio loop is described for both voltage ad curret offset. The first prototypes results are preseted ad show a real efficiecy of the auto-zero loop. The high swig curret irror used i the both aplifiers also described. It was very helpful for the dyaic rage ad the badwidth, especially for the curret aplifier where the low voltage ad low power ctraits were critical. ACKNOWLEDGEMENT The authors would like to thak their colleague G. Bo ad J.P. Richer for helpful discussi. REFERENCES [1] Christia C. Ez ad Gabor C. Tees, Circuit techiques for reducig the effects of Op-Ap iperfecti: Autozeroig, correlated, double saplig ad chopper stabilizatio, Proceedigs of the IEEE, vol. 84, o. 11, pp , Noveber [2] Ivars G. Fivers, J. W. Haslett, ad F. N. Trofiekoff, A high teperature precisio aplifier, IEEE J. Solid- State Circuits, vol. 30, o. 2, pp , February [3] J.N. Babaezhad ad R. Gregoria, A prograable Gai/Ls circuit, IEEE J. Solid-State Circuits, vol. SC- 22, o. 6, pp , Deceber [4] Fracis ANGHINOLFI, Pierre JARRON ICON a curret ode preaplifier i CMOS techology for use with high rate particle detectors IEEE trasacti o uclear sciece, vol 40, N 3, jue 1993 pp [5] Daiel DZAHINI et al A CMOS curret preaplifier ad Shaper with 50 Ohs Lie Driver for Liquid Argo Preshower IEEE Trasacti o uclear sciece, Vol. 42 N 4 August 1995 pp [6] Kio KOLI CMOS Curret Aplifiers: Speed versus Noliearity Thesis, Helsiki Uiversity of Techology, Electroic Circuit Desig Laboratory; Nov 2000 [7] Suharli Tedja ad Ja Va Der Spiegel, A CMOS Lowoise ad low power Charge saplig Itegrated circuit for Capacitice detector/sesor iterfaces IEEE Joural of Solid-State Circuits, vol.30 N 2 February 1995 p [8] Patrick G. DRENNAN ad Coli C. McAdrew, Uderstadig MOSFET isatch for aalog desig IEEE Joural of Solid-State Circuits, Vol.38 N 3 March 2003 p [9] Eduard SÄCKINGER ad Walter GUGGENBÜHL, A High-Swig high-ipedace MOS Cascode Circuit IEEE Joural of Solid-State Circuits, vol.25 NO. 1 February 1990 p [10] Biasig CMOS i low-voltage desigs ELECTRONICS WORLD Noveber 1999 pp This work was supported i part by Le Prograe d Acti Itégrées Fraco-arocai PAI MA/01/05.