Pipelined ADC Design. Mathematical Model for Ideal Pipelined ADC. Sources of Errors

Transcription

1 Pipelied ADC Desig Matheatical Model for Ideal Pipelied ADC Sources of Errors

2 Stadard Pipelied ADC Architecture ref CLK i S/H Stage Stage 2 Stage 3 Stage Stage - Stage Pipelied Assebler res res 2 res 3 res res - D 2

3 Pipelied Coverter Stage i Cl Stage ref res IN S/H AMP RES C LK ADC DAC w REF D OUT 3

4 Pipelied Coverter Stage IN S/H AMP RES C LK ADC DAC w REF D OUT Geerally cobied ito oe switched-capacitor gai stage 4

5 Siplified Pipelied Stage INh AMP RESh ADC DAC REF D OUTh Geerally oitted o last stage 5

6 Modelig of a Pipelied ADC Assue all oliearities ca be eglected 6

7 Pseudo-Static Tie-Ivariat Modelig of a Liear Pipelied ADC Paraaterizatio of Stage Aplifier Closed-Loop Gai Fro iput Fro DAC 2 Fro offset 3 Offset oltage - OS DAC DACi ADC Offset oltages - OSAi Out-Rage Circuit (if used ad ot icluded i ADC/DAC) DAC Levels - DACBi Aplifier Gai 4 IN ADC D OUT DAC AMP REF RES 7

8 Pseudo-Static Tie-Ivariat Modelig of a Liear Pipelied ADC Paraeterizatio of Iput S/H Stage IN S/H IN C LK = i 0 i 20 OS0 8

9 Pseudo-Static Tie-Ivariat Modelig of a Liear Pipelied ADC IN AMP RES ADC DAC DOUT REF For otatioal coveiece, assue bit/stage = d RES i DAC 2 3 OS 9

10 Matheatical Represetatio of the Pipelied Stages = d RES RES2 2 i i2 2 DAC = d DAC OS OS2 = d RES i DAC 2 3 OS = d RES i DAC 2 3 OS 0

11 Matheatical Represetatio of the Pipelied ADC = i 0 i 20 OS0 = d RES RES2 2 i i2 2 DAC = d DAC OS OS2 = d RES i DAC 2 3 OS = d RES i DAC 2 3 OS

12 Matheatical Represetatio of the Pseudo- Static Pipelied ADC = i = d RES RES2 0 2 i i i2 2 DAC = d 20 OS0 DAC OS OS2 = d RES i DAC 2 3 OS = d RES i DAC 2 3 OS RES i( ) = for = - 2 equatios 2- iterediate odal voltages ad i 2

13 3 Solutio of the 2 liear equatios = DAC 2 2 DAC DAC 2 i... d... d d OS 2 3 OS OS RES...

14 Solutio of the 2 Liear Equatios i d d d 2 2 REF = DAC 2 DAC2 DAC OS OS2... OS Ter ivolvig digital output codes RES REF Code-idepedet offset ter Code-depedet but ca be bouded by ½ LSB with out-rage strategy 4

15 Solutio of the 2 Liear Equatios = 2 REF 3 RES REF i d DAC OS = = 2 2 j= j j= j = ij = 2, DAC = REF /2, OS = 0 i REF d REF = RES - 2 = REF 5

16 Solutio of the 2 Liear Equatios i = α d f(offset) α = = DAC j= 2 j f(residue) f(offset) is code-idepedet, ideally zero, ad causes oly overall offset error i ADC f(residue) is code-depedet but ca be bouded by lsb (causig at ost ½ LSB error) with out-rage protectio No errors causig spectral distortio or INL degradatio if α are correctly deteried 6

17 Pseudo-Static Tie-Ivariat Modelig of a Liear Pipelied ADC IN AMP RES ADC DAC DOUT REF If ore tha bit/stage is used ad DAC is biarilyweighted structure ( ) 2 = - d RES i 2 j= j DACj 3 OS 2

18 Pseudo-Static Tie-Ivariat Modelig of a Liear Pipelied ADC IN AMP RES ADC DAC DOUT REF If DAC is characterized by f (, d ) ( ( )) = f, d RES i 2 REF j j= 3 OS REF j j= 22

19 Solutio of the 2 Liear Equatios If ore tha bit/stage is used ad DAC is biarilyweighted structure ( h= j = ) 2 REF 3 RES REF i d j DACj OS = j= = 2 2 j= j j= j = ( ) If DAC is characterized by f, d REF j j= ( ( )) = f, d 2 REF 3 RES REF i REF j OS = j= = 2 2 j= j j= j = No errors causig spectral distortio or INL degradatio if ters ivolvig d j are correctly deteried 23

20 Pseudo-Static Characterizatio of Pipelied ADC with Arbitrary Bits/Stage ad Out-Rage Protectio i = α d f(offset) = f(residue) d are boolea output variables fro stage ADCs (icludig out-rage protectio if icluded) the α are fuctios of DAC levels ad aplifier gais f(offset) is code-idepedet, ideally zero ad causes oly overall offset error i ADC f(residue) is code-depedet but ca be bouded by lsb (causig at ost ½ LSB error) with out-rage protectio Equatio applies to both sub-radix2 ad extra coparator out-rage protectio No errors causig spectral distortio or INL degradatio if α are correctly deteried 7

21 Observatios i = α d f(offset) = for of α : DAC f(residue) Substatial errors are itroduced if α are ot correctly iterpreted! Soe calibratio ad desig strategies focus o accurately settig gais ad DAC levels Aalog calibratio ca be accoplished with either DAC level or gai calibratio Digital calibratio based upo coefficiet idetificatio does ot require accurate gais or precise DAC levels j= 2 j 8

22 Observatios (cot) i = α d f(offset) = for of α : DAC j= 2 f(residue) j If oliearities are avoided, data coversio process with a pipelied architecture is extreely accurate Major challege at low frequecies is accurately iterpretig the digital output codes 9

23 Observatios (cot) i = α d f(offset) = for of α : DAC j= 2 f(residue) j If oliearities are preset, this aalysis falls apart ad the behavior of the ADC is upredictable! 20