Dynamic Data-bit Memory Built-In Self- Repair

Transcription

1 Dyaic Data-bit Meory Built-I Self- Repair M. Nicolaidis, N. Achouri, S. Boutobza iroc Techologies Greoble, Frace Abstract: I oder SoCs, ebedded eories occupy the largest part of the chip area ad iclude a eve larger aout of active devices. As eories are desiged very tightly to the liits of the techology they are ore proe to failures tha logic. Thus, they cocetrate the large ajority of defects ad affect circuit yield draatically. Thus, Built-I Self-Repair is gaiig sigificat iportace. This work presets a dyaic eory built-i self-repair scheer actig o the data-bit level. It allows reducig the size of the repairable uits, or i other words, it allows usig a sigle spare uit for repairig faults affectig several regular uits. As a cosequece, it repairs ultiple faults by eas of low hardware cost. 1. Itroductio Traditioally, eory repair is perfored by usig exteral equipet to test the eory, localize the faults, ad drive a laser bea to perfor the repair. Electrical fuses or ati-fuses ca also be used to avoid laser bea, but agai a exteral test equipet deteries the fuses to be blow. Recet developets replace exteral equipet by Built-I Self-Test (BIST) ad Built-I Self- Repair (BISR) schees i order to aitai a reasoable test ad repair cost for ebedded eories. As a additioal advatage BIST ad BISR ca test ad repair ebedded eories at ay tie durig the product life [1]. This reduces aiteace cost, ad icreases reliability ad product life. Various BISR approaches have bee developed. Row (or word) BISR replaces faulty regular rows (or words) by spare rows (or words). Colu BISR replaces faulty regular colus by spare colus. Data-bit BISR uses a eo ry part geeratig a spare data bit to replace a eory part geeratig a regular data bit. I this work we cosider the data-bit BISR ad the colu BISR schees. Data-bit BISR ca repair faulty cells ad faulty colus, as well as faulty colu -es, faulty read ad write aplifiers, ad faulty data iput/output latches. Repairig read aplifiers ay iprove yield sigificatly, sice the sese aplifiers are very sesitive circuits ad ca be faulty ore frequetly tha other parts. Colu repair ca repair faulty colus, ad also etire faulty bits, if it disposes sufficiet spare colus. Repairig faulty colus i additio to the faulty cells is iportat sice a large uber of defects ay result o a faulty colu. For istace, ay defect creatig a stuck-o fault o oe Perissio to ake digital or hard copies of all or part of this work for persoal or classroo use is grated without fee provided that copies are ot ade or distributed for profit or coercial advatage ad that copies bear this otice ad the full citatio o the first page. To copy otherwise, to republish, to post o servers or to redistribute to lists, requires prior specific perissio ad/or a fee. ICCAD 03, Noveber 11-13, 2003, Sa Jose, Califoria, USA. Copyright 2003 ACM /03/ $ of the two access trasistors of a SRAM cell will result o a faulty colu, sice the cell is peraetly coected to the bit lie. O the other had, row ad word repair caot repair these iportat classes of faults. Row/word repair is the siplest BISR approach. Thus, the ajority of the previous works cosider this schee, although colu repair was the predoiat exteral repair schee used for stad-aloe eories. Word repair was early proposed by K. Sawada et al [2]. It uses a cotet addressable eory for storig the data ad addresses of the faulty words. The work cosidered low ubers of faults. Also, faults i the spare parts are ot cosidered. Subsequet works o word BISR [3] [4], [5] use the sae basic schee but iprove various ipleetatio aspects. These works too cosider a low uber of faults (e.g. two faults i [4]), ad o faults i the spare uits. A ore recet work [8] uses ovolatile eory cells to fix oce forever the repair of aufacturig faults. Fixig aufacturig faults is also treated i [1], where a taxooy of various ways to repair ad fix aufacturig faults ad field faults is preseted. Work o colu/data BISR is ore recet due to the difficulty for elaboratig the recofiguratio fuctios for this repair. Ki et al [6] preset the first colu repair schee. I this schee the recofiguratio iforatio is geerated by a cotroller ad stored i a eory. To aster the coplexity of the recofiguratio process, the schee repairs a sigle fault per test sessio. That is, the eory is tested util a first fault is foud ad repaired. The, the eory is tested agai util a secod fault is foud ad repaired, ad so o. This process siplifies the work of the BISR cotrol uit, but the test ad repair tie will becoe very high whe the uber of faults icreases. The paper cosiders a sall uber of faults (e.g. 2 faulty colus out-of 128 regular colus), ad uses a large uber of storage cells for storig the recofiguratio iforatio. Aother paper [7] cosiders the cobiatio of colu ad row repair. It proposes a algorith that allocates efficietly the spare rows ad colus to repair ultiple faults that ay affect soe colus ad rows. However, it does ot propose BISR circuitry for perforig the eory recofiguratio. Fially a ore recet paper [9] presets optial recofiguratio fuctios for data-bit repair. The derived fuctios perfor repair for ultiple faults affectig both the regular ad spare eleets, iiize the hardware

2 cost for ipleetig the repair cotrol ad for storig the recofiguratio iforatio, ad perfor the repair by eas of a sigle test pass. This optiises the BISR cost ad the repair efficiecy. I additio, the schee does ot require odifyig the eory structure, sice the repair circuitry is placed aroud the eory. Thus, the repair is copatible with stadard eory copilers. I the preset paper we preset a dyaic repair schee that icreases the repair efficiecy of the schee preseted i [9]. This is doe by usig a sigle spare uit for repairig faults affectig several regular uits. I additio the dyaic schee is ehaced to allow usig spare uits of a size saller tha the regular uits (the eory parts geeratig a data-bit). This is iportat for achievig low repair cost i eories havig words of ediu or sall size. For such eories, addig eve a sigle spare bit, as required by the basic dyaic repair approach, leads i a sigificat area cost. The ehaced schee shows a draatic decrease of the area cost. 2. Static data-bit BISR Data-bit BISR is a repair approach that deteries the data-bit positios i which the eory geerates erroeous data, ad replaces the defected parts coected to these bit positios by spare parts. Thus, a replaceable part is the set of eory colus coected through the colu ultiplexer to a data iput/output of the eory. For siplicity, we will call the regular replaceable parts as regular uits ad the spare replaceable parts as spare uits. We ca use k spare uits i order to be able to replace up to k faulty regular uits. This schee is very flexible, sice we do ot eed to odify the eory structure for ipleetig it. Istead, we ca use a stadard eory copiler to geerate a eory havig a word legth of +k bits. I additio, we geerate a BISR circuitry exteral to the eory, able to capture the locatios of the faulty data-bits ad replace the by faultfree data-bits. Such a schee has bee preseted i [9]. +k k X+k X X-1... BIST Coparator Error Idicatio 0 X0 Reset Figure 1: Geeratio of the state of the latches by eas of the BIST coparator Figure 1 shows the circuit used for locatig the faulty-bit positios. It cosists o +k latches (faulty-bit idicatio - - latches) ad +k OR gates. The iput of each latch is geerated by a OR gate that receives as iputs the output the latch ad the output of oe XOR gate of the BIST coparator. Durig the test phase, the whole eory (regular ad spare bits) is tested ad the latch correspodig to ay of these bits is set to 1 whe a error is detected o this bit by the correspodig XOR gate of the BIST coparator. I this schee we used +k faultybit idicatio latches. This way, we ca locate both the regular ad spare faulty bits, ad use oly fault-free spares to replace the faulty regular bits. We uber the fuctioal uits (regular bits) fro 0 to -1 (U0, U1,, U-1) ad the spare uits (spare bits) fro through to +k-1 (U, U+1,, U+k-1). To perfor repair, a set of es is used to replace the faulty bits by spare oes. The recofiguratio ca be doe i a local aer. I this case, a faulty uit is replaced by its left-side closest fault-free uit, as illustrated i figure 2, with =4, ad k=3, where the of positio i is coected to the eory output of positio i, ad to the eory outputs of positios i+1, i+2,, i+k. A distat repair is also possible as illustrated i figure 3. To geerate the cotrol sigals of the es i figures 2 ad 3, we eed to ipleet the recofiguratio fuctios that geerate these sigals i respose to the states of the faulty-bit idicatio latches of figure 1. To ipleet a dyaic schee, ultiple copies of these fuctios have to be used, as we will see later. Thus, it is iportat to dispose low cost recofiguratio fuctios, to ake the dyaic schee practical. [9] proposes copact ipleetatios for these fuctios. For the local repair, these fuctios are described by the recursive equatios (1) ad (2), where i is the state of the faultybit idicatio latch of positio i, ad M j i is the cotrol sigal of iput j, of the of positio i, ad the es are ipleeted without iteral decoders (the sigals M j i are already decoded). (1) M 0 0 = 0, M 1 0 = 1 0,, M k 0 = k 1 0. (2) M j i+1 = i+j+1 (M j i + M j-1 i i+j + M j-2 i i+j- 1 i+j + + M 0 i i+1 i+2 i+j ), 0 j k. The recofiguratio fuctios for the distat repair, are described by the recursive equatios (3), (4), (5), ad (6). I this case we the regular uits are ubered RU 0, RU 1, RU -1, the spare uits are ubered SU 1, SU 2,, SU k. The states of the correspodig fault locatio latches are oted RF 0, RF 1,, RF -1 ad SF 1, SF 2,, SF k. The variables F j are iterediate variables used for coveiece. (3) M 0 0 = RF 0, M 1 0 = SF 1 RF 0,, M k 0 = SF k F k-1 SF 1 RF 0. (4) F j 0 = Mj 0, j {0, 1,, k}. (5) F j i+1 = Fj i RF i+1 + M j i+1 RFi+1, 0 i -2, 0 j k. (6) M 0 i+1 = RF i+1, M j+1 i+1 = SF j+1 RF i+1 (F j i +Fj-1 i SFj +F j- 2 i SF j-1 SF j + + F 0 i SF1 SF 2 SF j ), 0 j k-1, 0 i k

3 U 6 Spare Uits : k =3 Fuctioal Uits : = 4 U 5 U 4 U 3 d3 M 3 0 M 3 1 M 3 2 M 3 3 Figure 2: The local repair schee. Spare Uits : k =3 Fuctioal Uits : = 4 U 2 d2 U 1 d1 U 0 d0 M 0 0 M 0 1 M 0 2 M 0 3 icrease the eory size cosiderably. I additio, this approach requires a cosiderable effort to odify the eory copilers. Thus, it is suitable to repair the eory by usig access oly to the eory iputs ad outputs. The static data-bit repair schee preseted [9] has this advatage, but it uses a large spare uit to repair a sigle fault (a spare block icludes a uber of cells equal to the uber of eory words). To reduce the size of repairable uits, while perforig the recofiguratio by accessig oly the exteral iputs/outputs of the eory, we propose a dyaic repair. It odifies dyaically the cotrol sigals of the es, so that they use a spare bit to replace a faulty regular bit oly for a subset of the eory addresses ad other faulty regular bits for other subsets of the eory addresses. To explai this schee let us first cosider the static schee of figure 4. SU3 SU2 SU1 RU3 RU2 RU1 RU0 Meory [words of (+k) bits] +k d3 M 3 0 M 3 1 M 3 2 M 3 3 d2 Figure 3: The distat repair schee. d1 3. Dyaic data-bit BISR A ajor attribute of a repair schee is the size of the replaceable uits. This size ipacts the extra area required for repairig a fault. If the replaceable uit is too sall, the, we will have a large uber of such uits, ad the area occupied by the recofiguratio logic ad the itercoectios added for localizig ad replacig the faulty uits will be very large. For istace, if the replaceable uit is the cell, the the uber of possible faulty locatios is very high, requirig a large aout of eory for storig this iforatio, ad a large aout of routig area together with a very coplex recofiguratio logic. O the other had, if the size of the replaceable uit is very large, the, to repair a sigle faulty-cell withi a replaceable uit will require to use a spare uit of large size, akig high the repair cost per faulty-cell. Therefore, there is a optial size of the replaceable uit for each eory size ad for the target uber of repairable faults. However, oce this optial size is deteried, it is ot always easy to ipleet the repair schee usig this replaceable uit size, due to topological costraits of a eory desig. I fact, eories have a very regular ad copact layout. Isertig withi this layout extra routig ad extra logic for perforig the repair ay break this regularity ad d0 M 0 0 M 0 1 M 0 2 M 0 3 Recofiguratio Logic es +k Latches Data Bus Figure 4. Static data-bit repair schee I this figure, the eory icludes +k blocks of cells, each correspodig to oe fuctioal or oe spare data bit. The recofiguratio circuitry icludes +k latches storig the fault locatio iforatio (+k latches), es allowig to coect the bits of the data BUS to the fault-free regular ad spare data bits of the eory, ad a recofiguratio logic that geerates the cotrol sigals of the es. The repairable uit is the block of cells coected to a data-bit iput/output. Thus, its size is equal to N w cells, N w is the uber of eory words. To divide the size of the repairable uits by a factor R, the ew schee uses R blocks of +k latches as show i figure 5. I this figure, durig the test phase, we use r address bits (A 1 through to A r ) to select a differet set of latches for each value of these address bits. Thus, for each of the R = 2 r values of these bits, a differet set of latches stores the fault-locatio iforatio. +k +k BIST Coparator +k Figure 5: Selectig a block of latches durig the test phase 590

4 Durig the regular operatio of the syste, the address bits A 1, A 2,, A r, are oitored to deterie which block of latches will be selected to drive the recofiguratio of the eory durig each eory access cycle, as show i the figure 6. +k Recofiguratio Logic +k Meory [words of (+k) bits] es +k Data Bus +k Figure 6: Selectig a block of latches durig oral operatio I figure 4, we ote that durig the oral operatio, the outputs of the recofiguratio fuctios are costat, sice the iputs of these fuctios are fixed at costat values durig the repair phase. Thus, there is o delay added to the eory operatio due to the coputatio of the output values of these fuctios. O the other had, i figure 6, the iputs of the recofiguratio fuctio are ot fixed, itroducig extra delay i the eory operatio. To avoid this delay, we replicate the recofiguratio fuctios R ties (blocks RFL 0, RFL 1, RFL R-1 ), ad place the ultiplexers cotrolled by the address bits A1, A2,, Ar o the outputs of these blocks (see figure 7). A1 Ar Meory [words of (+k) bits] es +k I/Out RFL 0 RFL 1 RFL R-1 +k +k +k Figure 7: A faster schee for dyaic repair I this case, the hardware cost is higher, sice we use R recofiguratio logic blocks istead of 1, but the recofiguratio speed is higher, sice the iputs ad the outputs of the recofiguratio fuctios are fixed durig the repair phase. Thus, the logest path of the recofiguratio circuit icludes the two es, while i figure 7 it icludes the two es, ad the recofiguratio fuctios. 3.1 Trade-offs i repair paraeters, ad experiets Usig the dyaic recofiguratio schee described above, we ca icrease the repair efficiecy sice the size of the repairable uit is divided by R = 2 r. Thus, the size of the repairable uits ca becoe arbitrarily sall. For istace, by usig all the address bits of the eory to drive the used i the dyaic recofiguratio, the size of the repairable uit is reduced to a sigle cell. Fro this poit of view, the repair becoes optial, but the cost of the recofiguratio circuitry becoes excessive sice it icreases liearly with R. There is a optial R that gives the best cost trade-offs. Cosider for istace that we eed to repair up to 8 faults i a 1 Mbit eory havig a 32-bit word size. The block of cells coected to each data iput/output icludes 32K cells. This is the size of the repairable uit used by the static recofiguratio schee. Thus, to repair 8 faults we eed 8 spare repairable uits correspodig to 256K spare cells. By selectig r = 1, we divide by 2 the size of the spare uits, so we will eed 128 K spare cells (a gai of 128 K spare cells,) but we will eed 2x40 latches istead of 40 latches (a icrease of 40 latches) for the schee of figure 6 (ad also a secod block of recofiguratio logic for the schee of figure 7). The iproveet is sigificat sice we have a gai of 128 K eory cells by payig 40 extra latches ad a block of recofiguratio logic. If we use r = 2, the, with respect to the case of r = 1 we gai 64 K eory cells ad we pay 80 extra latches (ad also two extra blocks of recofiguratio logic for the schee of figure 7). The gai is still iportat, but it is divided by 2, while the cost of the extra circuitry is ultiplied by 2. This happes each tie we icreet r. So, at soe poit the gai becoes less iportat tha the extra cost. This poit correspods to the optial ipleetatio of the schee. Deteriig this poit will eable a optial repair. This aalysis is pertiet for eory techologies affected by very high defect desities, as expected for ao-techologies [10] [11], where we will eed to repair huge ubers of faults. However, for the oderate ubers of faults affectig CMOS ICs, the optial poit will correspod to k=1 ad R=Nf (Nf beig the axiu target fault ultiplicity). Table 1, shows the area overhead required for applyig the dyaic schee for various values of k ad r, as well as for the static schee (r=0) for various values of k. The cosidered eory is a 64K X 32 SRAM. The area overhead is estiated for a coercial 0.18 icro CMOS techology. The area cost of the recofiguratio fuctios ad of the routig is estiated usig the 591

5 AMBIT tool. The axiu uber of repairable faults is equal to k2 r. Thus, we ca use k=1, r=3, to repair a eory icludig up to 8 faults, at a extra area of 3.4%, while usig k=2, r=2, will repair the sae uber of faults at a uch higher area cost (6.1%). We also observe that the static schee for r=0, k =6, ca repair oly 6 faults at a drastically higher area cost (17.44%). Table 1. Area overhead of various BISR ipleetatios for a 64K X 32 SRAM r k = 6 k = 5 k = 4 k = 3 k = 2 k = Table 2. Area overhead of various BISR ipleetatios for a 256K x 8 SRAM r k = 6 k = 5 k = 4 k = 3 k = 2 k = Table 2 shows the area cost for a eory usig 8-bit words. We observe that i this case, the iiu cost, required for repairig a sigle fault (k=1, r=0) is 12.27%. This cost is uch higher, tha the cost required for the 32-bit word width eory, eve whe we use the later to target a uch higher fault ultiplicity. Whe usig the dyaic repair approach, this cost icreases very slightly for repairig a uch higher uber of faults (e.g % for repairig 8 faults, whe k=1, r=3). 4. Dyaic repair usig spares of reduced size I the previous data-bit repair schees, a spare uit icludes a uber of cells equal to the uber of eory words N w. Thus, the iiu area overhead (use of a sigle spare uit) is equal to (#spare uit cells)/(#regular eory cells) %= N w /( N w x N wc ) % = 1/ N wc %, where N wc is the uber of regular cells per eory word. Thus, the iiu area overhead ca be sigificat for eories with ediu or sall word size. To reduce this cost, we eed to reduce the size of the spare uits. This sectio describes a extesio of the dyaic repair schee that allows achievig this goal. The schee is illustrated i figures 8 ad 9. We use regular uits ad k spare oes. As for figures 6 ad 7, we use r address bits to perfor dyaic repair, but we use spare uits with size equal to the 1/2 r of the size of the regular uits. We illustrate this schee by cosiderig that each spare uit is coposed of oe eory colu. I this case we select r to be equal to the uber of the address bits of the colu decoder (bits ), but the schee is valid for ay other value of r. Fro this choice, each regular uit icludes R= 2 r colus. We use R sets of latches for the regular positios, but oly oe set of latches for the spare positios (sice each spare positio is coposed of a sigle colu). The schee is described for local repair. A siilar approach ca be used for distat repair. Figure 8 illustrates the operatio durig the test phase. Siilarly to the dyaic schee of figure 5, durig this phase, the curret value of the address sigals coects oe set of to the outputs of the XOR gates of the BIST coparator. This is doe by eas of a cotrolled by the sigals. This arrageet is used oly for the regular positios. O the other had, o is eployed for the k spare positios, sice we use oly oe set of latches for these positios. k Latches k BIST Coparator Figure 8: Selectio of the latches durig test k Latches Meory [words of (+k) bits] +k es I/Out RFL 0 RFL 1 RFL R-1 Figure 9: Iteractios of recofiguratio fuctios i dyaic repair usig sigle-colu spares Figure 9 illustrates how the repair is perfored durig the circuit operatio. This operatio is siilar as for the dyaic schee of figure 7. However, i figure 7, ay two differet blocks of recofiguratio logic (blocks LFL i) have iputs coig fro two differet sets of latches. O the other had, i figure 9, the differet blocks of recofiguratio logic share soe iputs (i.e. the outputs of the k latches of the spare positios). Also, i figure 7, the blocks of the recofiguratio logic do ot 592

6 exchage ay iforatio (they ipleet utually idepedet fuctios. O the other had, i figure 9, the blocks of recofiguratio logic ipleet iterdepedet fuctios. Thus, they exchage soe iforatio. Let us ow deterie the iterdepedet recofiguratio fuctios used i figure 9. Due to the iterdepedecies, derivig these fuctios becoes quite coplex. To siplify this task we itroduce soe iterediate variables. Thaks to these variables we are able to use the recofiguratio fuctios described i the sectio 2. Let FBi be the state of the latch of the spare positio i ( i +k-1). Let FBi q be the state of the latch used for the colu q of the regular positio i (0 i -1). Let Mj y,x be the cotrol variable of the of positio y that idicates if the colu x of the positio y has to be shifted by j positios. Mj y,x is coputed by the recofiguratio logic RFLy. We itroduce the iterediate variables FBi b,q. This variable is used oly by the recofiguratio logic RFLq. For positios that dispose the coplete set of colus (i.e. for the regular positios), we have FBi b,q = Fbi q (7). For positios that dispose oly oe colu (i.e. the spare positios) FBi b,q is defied as follows. FBi b,q takes the value 1 to idicate that the positio i is ot available for a possible shift of the colu q of positio b, due to oe of the followig reasos: - the positio i is faulty, - the positio i is already occupied by a faulty colu of ay positio lower tha b, exceptig the colus of rak q, or by a colu of the positio b, havig rak lower tha q. - I all other cases the value of FBi b,q is 0. I this defiitio of FBi b,q we have ot cosidered the occupatio of the positio i by a colus of rak q, because this occupatio is treated by the fuctios Mj y,x as defied i sectio 2. Fro this defiitio of FBi b,q for the spare positios, we obtai: R b-1 q-1 (8) FBi b,q = FB i + Mi-y y,x + Mi-b b,x x=1 y=i-k x=1 xq The, by replacig the variables FBi b by the variables FBi b,q i the equatios (1),(2) of the variables Mj y for the static recofiguratio schee described i sectio 2, we obtai the equatios of the variables Mj y,q, geerated by the recofiguratio fuctios of figure 9. These equatios are: (9) M 0 1,q = FB 1 1,q, M1 1,q = FB1 1,q FB2 1,q, M 2 1,q = FB1 1,q FB2 1,q FB3 1,q M k 1,q = FB1 1,q FB2 1,q FBk-1 1,q FBk 1,q M j = M j i,q FBi+j+1 + M j-1 i,q FBi+j FBi+j+1 + Mj-2 i,q FBi+j-1 FBi+j FBi+j M 0 i,q FBi+1 FBi+2 FBi+j FBi+j+1 The equatios 7, 8, ad 9, defie the recofiguratio fuctios used i figure 9. A last proble cocers the fact that the spare colus are ot usig ay colu decoder. Thus, they are ot isolated fro the write aplifiers ad will be accessed durig each read ad write cycle. While the access durig a read cycle ay ot be a proble, this access ay destroy the cotets of the cells of the spare colus durig the write cycles. To cope with we ca use oe of the followig two solutios: - Use the sigals Mj y,x eablig the coectio of a spare colu to the data iput/outputs to activate the write aplifier. I this case the write aplifier is activated oly whe the spare colu is coected to soe data iput/output, - Place a write aplifier to each brach of a coectig a data iput to the spare colus, but before the trasistors of the that create this coectio. Thus, each spare colu will be drive by a write aplifier oly whe oe of these trasistors is o (for activatig the coectio of the spare colu). This is illustrated i figure 10, where the data iput d3 is coected through a cotrolled by M 3 0, M 3 1, M 3 2, ad M 3 3, to the regular uit U3 ad the spare uits U4, U5, ad U6. The first solutio is preferable sice it uses a lower uber of write aplifiers ad avoids a icrease of power dissipatio. The read aplifiers of the spare colus ca also be activated selectively i a siilar aer, but this is ot ecessary as said above. U 6 U 5 U 4 apli U 3 d3 M 3 3 M 3 2 M 3 1 M 3 0 Figure 10. Write aplifier for the spare uits The schee preseted i figures 8, 9, allows usig a sigle colu as spare uit. However, with this schee, each spare colu ca be used to repair a fault affectig a sigle colu. To eable usig a sigle spare colu for repairig faults affectig several colus, we ca add a secod level of dyaic repair, as illustrated i figure 11. For doig so, we use Q=2 q copies of the k latches used i figures 8, 9 for the k spare uits, ad Q copies of the R sets of latches used i these figures for the regular uits. We also use Q copies of the R blocks of the recofiguratio fuctios show i figure 9 ad described by equatios 7,8,9. Each of these copies is fed by the outputs of oe of the Q copies of the sets of latches, ad provide Q copies of Rx output sigals. A 593

7 cotrolled by the address bits reduces these sigals ito Q copies of sigals. A secod cotrolled by the address bits Ar+1 Ar+q, reduce these Qx sigals ito the sigals that cotrol the ultiplexers used to recofigure the +k regular ad spare uits. Note that the two es cotrolled by the address bits ad Ar+1 Ar+q, ca be cobied ito a sigle cotrolled by the address bits +q. Qxk Ar+1 Ar+q es I/Out Q RFL 0 Q RFL 1 RFL R-1 Qx Qx Meory [words of (+k) bits] +k Qx Figure 11. Dyaic repair with a secod-level ultiplexig Table 3 shows the area overhead for a eory usig 8-bit words. This schee repairs k2 r 2 q faults. We observe a draatic reductio of the area cost with respect to the dyaic schee of sectio 3 (table 2). For istace, for repairig up to 64 faults, this schee requires a area overhead of 5.13% (k=1, r=3, q=3), while for the sae eory the dyaic schee of sectio 3 requires a area overhead of 12.27% for repairig oly oe fault (k=1, r=0). Table 3. Area overhead of various BISR ipleetatios usig spares of reduced size, for a 256K x 8 SRAM k r q = 1 q = 2 q = Coclusios This paper presets a data iput/output dyaic Built-I Self-Repair schee able to repair eories at the data iput-output level. The dyaic approach allows to use each spare uit for repairig faults affectig ultiple regular uits, thus, icreasig drastically the repair efficiecy. A drawback of the schee is that the size of each spare uit is equal to (#eory cells)/(#word cells). It results i a sigificat area overhead for eories with sall ad ediu word width. Therefore, a extesio of the dyaic BISR schee is also preseted. It allows usig spare uits of ay desired size. It reduces draatically the area overhead for ay word width, ad ore particularly for sall ad ediu word widths. Refereces [1] Zoria Y., Ebedded Meory Test & Repair: Ifrastructure IP for SOC Yield, 2002 IEEE Iteratioal Test Coferece. [2] Sawada K., Sakurai T., Uchio Y., Yaada K., Built-I self repair circuit for High Desity ASMIC, IEEE 1999 Custo Itegrated Circuits Coferece. [3] Taabe A. et al A 30-s 64-Mb DRAM with Built-i Selftest ad Self-Repair Fuctio, IEEE Joural Solid State Circuits, pp , Vol 27, No 11, Nov [4] Bhavsar D. K., Edodso J. H., Testability Strategy of the Alpha AXP Microprocassor, I994 IEEE Iteratioal Test Coferece. [5] Beso A. et al A Faily of Self-Repair SRAM Cores, 2000 IEEE Iteratioal Test Coferece I Proc. IEEE Iteratioal O -Lie Testig Workshop, July 3-5, [6] Ki I., Zoria Y., Kooriya G., Pha H., Higgis F. P., Newadowski J.L. "Built-I self repair for ebedded highdesity SRAM" Proc. It. Test Coferece, 1998, pp [7] Ki H. C., Yi D.S., Park J.Y., Cho C.H., A BISR (Buil-I Self-Repair) circuit for ebedded eory with u ltiple redudacies, 1999 IEEE Iteratioal Coferece o VLSI ad CAD, Oct , 1999, Seoul, Korea, pp [8] V. Schober, S. Paul, O. Picot, Meory Built-I Self-Repair usig redudat words, 2001 IEEE Itl Test Coferece. [9] M. Nicolaidis, N. Achouri, S. Boutobza, Optial Recofiguratio Fuctios for Colu or Data-bit Built-I Self- Repair, 2003 Desig Autoatio ad Test i Europe (DATE 03), March 3-7, 2003, Muich, Geray. [10] Heath J.R., Kuekes P.J., Sider G.S., Staley Willias R., A Defect-Tolerat Coputer Architecture: Opportuities for Naotechology, SCIENCE, Vol. 280, Jue 12, 1998 [11] M. Nicolaidis, N. Achouri L. Aghel, Meory Built-I Self-Repair for Naotechologies, 2003 IEEE Iteratioal O-Lie Testig Syposiu. 594