Compaction-based concurrent error detection for digital circuits

Transcription

1 Microelectroics Joural 36 (2005) Copactio-based cocurret error detectio for digital circuits Sobeeh Aluhaizi a, *, Petros Drieas b, Yiorgos Maris a a Electrical Egieerig Departet, Yale Uiversity, 5 Prospect Str. #20, New Have, CT 06520, USA b Coputer Sciece Departet, Resselaer Polytechic Istitute, Troy, NY 20, USA Received 26 July 200; received i revised for March 2005; accepted 20 March 2005 Available olie 5 July 2005 Abstract We preset a o-itrusive cocurret error detectio () ethod for cobiatioal ad sequetial digital circuits. We aalyze the optial solutio odel ad poit out the liitatios that prevet logic sythesis fro yieldig a iial-cost oolithic ipleetatio. We the propose a copactio-based alterative approach for restricted error odels. The proposed ethod alleviates these liitatios by decoposig the fuctioality ito: copactio of the circuit outputs, predictio of the copacted resposes, ad copariso. We odel the fault-free ad erroeous resposes as coected vertices i a graph ad perfor graph colorig i order to derive the copacted resposes. The proposed ethod is first discussed withi the cotext of cobiatioal circuits, with zero detectio latecy, ad subsequetly exteded to Fiite State Machies (FSMs), with a costat detectio latecy of oe cloc cycle. Experietal results deostrate that the proposed ethod achieves sigificat hardware reductio over duplicatio-based, while detectig all possible errors. q 2005 Elsevier Ltd. All rights reserved. Keywords: Copactio; O-lie testig; Reliability; Self-checig; Self-testig. Itroductio Cocurret error detectio () ethods are used to oitor the behavior of a circuit durig its oral operatio to idicate ay deviatio fro the correct fuctioality. Such cotiuous oitorig of the fuctioality is highly desirable i safety critical applicatios where data itegrity is of paraout iportace. The eed for is accetuated by the various ethods that have bee devised i the literature [ 7]. Quality assesset of these ethods relies o several paraeters, icludig the odel of detectable faults or errors, the worst-case detectio latecy, ad the icurred area overhead. Additioally, a iportat cosideratio is whether a cocurret test ethod is itrusive or o-itrusive, i.e. whether the circuit is odified or left itact, respectively. I this paper, we exaie a low-cost, zero-latecy, oitrusive ethod for logic circuits. The ethod is based o copactio of the circuit outputs, predictio of the copacted resposes, ad copariso. As opposed to duplicatio-based, which targets the urestricted error odel, this ethod achieves sigificat hardware cost reductio by utilizig the iforatio available through a restricted error odel. The geeral uderlyig priciple of this ethod was first odeled i []. We provide a extesive review of related wor i cocurret test i Sectio 2. For the purpose of copleteess, we review the optial solutio i Sectio 3. We the focus o logic sythesis liitatios that prevet the optial odel fro yieldig a iial-cost ipleetatio, which we deostrate through a exaple i Sectio. Copactio-based ethod, which follows the paradig of duplicatiobased ad addresses these liitatios through decopositio is discussed i Sectio 5. Experietal results i support of this ethod are provided i Sectio 6, followed by a discussio regardig optiality, possible reedies, ad extesio to FSMs i Sectio 7. * Correspodig author. Tel.: C ; fax: C E-ail address: sobeeh.aluhaizi@yale.edu (S. Aluhaizi) /$ - see frot atter q 2005 Elsevier Ltd. All rights reserved. doi:0.06/j.ejo Related wor A plethora of research efforts have bee expeded i developig techiques that provide high levels of

2 S. Aluhaizi et al. / Microelectroics Joural 36 (2005) reliability. Several low-cost, o-itrusive, Cocurret fault detectio (CFD) ethods have bee proposed for cobiatioal circuits. C-BIST [] eploys iput oitorig to perfor cocurret self-test. While hardware overhead is very low, the ethod relies o a ordered appearace of all possible iput vectors before a sigature idicatig circuit correctess ca be calculated, resultig i very log detectio latecy. This proble is alleviated i R-CBIST [9], where the requireet for a uiquely ordered appearace of all iput cobiatios is relaxed at the cost of a sall RAM. Alteratively, latecy is reduced through the copariso-based ethod i [0], which uses additioal logic to predict the circuit resposes for a coplete test set. Siilar CFD ethods have bee recetly proposed for FSMs as well [,2]. Towards the high-cost ed, several zero-latecy ethods have bee proposed for cobiatioal ad sequetial circuits []. Reducig the area overhead below the cost of duplicatio typically requires redesig of the origial circuit, thus leadig to itrusive ethodologies. Several redesig ad resythesis ethods are described i [3 5], wherei parity or various uordered codes are eployed to ecode the states of the circuit. Liitatios of [5], such as structural costraits requirig a iverterfree desig, are alleviated i [3], where partitioig is eployed to reduce the icurred hardware overhead. Utilizatio of ultiple parity bits, first proposed i [], is exaied i [7] withi the cotext of FSMs. These ethods reder totally self-checig circuits ad guaratee zerolatecy error detectio; o the dow side, they are itrusive ad relatively expesive. No-itrusive ethods have also bee proposed. The geeral algebraic odel is itroduced i [5]. Ipleetatios based o Bose-Li ad Berger codes are preseted i [6] ad [7], respectively. Fially, parity-based ethods for cobiatioal circuits ad FSMs are described i [,6]. The circuit is resythesized to iclude based o ultiple parity groups. A cost fuctio reflectig the total cost of the odified origial circuit ad the parity predictio circuit guides the foratio of parity groups. 3. Optial o-itrusive We first review the optial odel for o-itrusive []. It is iportat to ephasize that this discussio is based o the assuptio that a restricted error odel is specified. Ideed, for a urestricted error odel, wherei a errorfree respose ay be trasfored ito a arbitrary erroeous respose, iforatio theory proves that ay o-itrusive circuit will be as coplex as the origial circuit []. I this case, duplicatio (possibly with desig diversity to avoid coo-ode failures) costitutes the ost appropriate o-itrusive ethod. I order to preserve geerality, the error odel is ot defied through peraet or trasiet faults i the hardware, but rather i ters of the erroeous behavior that such faults iduce. Thus, ay fault odel ca be prescribed by providig, for every iput cobiatio, the error-free respose ad all erroeous resposes resultig fro faults i the odel. Cosider, for exaple, the cobiatioal circuit with iputs ad outputs show i Fig.. For every iput cobiatio a2[0,.,2 K], Let the error-free respose of the circuit be GM(a), the set of erroeous resposes resultig fro faults i the prescribed fault odel be BM(a), ad the set of resposes that will ever occur for faults i the prescribed fault odel be DC(a). Note that the above sets do ot itersect ad that jbm(a)gdc(a)jz2 K. As depicted i Fig., the oitrusive circuit oitors the iputs ad outputs ad idicates errors through the -bit output. The fuctioality of the circuitry ay be defied for every a2[0,.,2 K] as follows: 9 : IN Z ao Z GMðaÞ >< >= Z 0 : IN Z ao2bmðaþ () >: >; X : IN Z ao2dcðaþ Give this fuctio defiitio, a sythesis tool could be eployed to produce the actual circuit. If sythesis algoriths [9] were able to search exhaustively ad geerate the circuit with iial area cost, this process would yield the optial o-itrusive solutio. However, i order to deal with the large search space, sythesis tools [20] eploy heuristics that ay lead to suboptial solutios. Thus, it is possible that alterative proble odellig ay result i ore cost-effective circuits.. Sythesis liitatios Exact optiizatio ethods for sythesis of circuits as ulti-level etwors are ot cosidered to be practical [9]. The flexibility offered by ulti-level etwors i circuit ipleetatio coes at the cost of a large search space ad, cosequetly, great difficulty i iiizig the circuit cost. Although several heuristics exist for this purpose, their effectiveess deteriorates as the uber of iputs, the uber of outputs, ad the uber of do t care coditios i the circuit defiitio icrease. A icrease i the uber IN Cobiatioal Circuit Cocurret Error Detectio Circuit Fig.. No-itrusive odel.

3 5 S. Aluhaizi et al. / Microelectroics Joural 36 (2005) of iputs iplies a larger uber of boolea sub-cubes. A icrease i the uber of outputs iplies ore opportuities for coo boolea sub-cube extractio. A icrease i the uber of do t care coditios iplies ore flexibility i ebeddig a boolea fuctio withi a eviroet. I all three cases, the search space icreases rapidly ad heuristics have a hard tie fidig the optial solutio. To deostrate the ipact of sythesis liitatios o optiality of cost, cosider the exaple of usig duplicatio, the siplest o-itrusive ethod. More specifically, cosider the -bit ultiplier show i Fig. 2(a). The ultiplier is defied i pla forat, sythesized usig the rugged script of SIS [20], ad apped oto a stadard library coprisig 2-iput gates. The cost of the ultiplier is provided through the prit_ap_stats coad of SIS. The hardware added for duplicatio-based icludes a replica of the circuit alog with a -bit coparator, the cost of which is also idicated i Fig. 2(a). Alteratively, as show i Fig. 2(b), the fuctioality of the hardware ca be described as a sigle boolea fuctio of 6 variables, aely the iputs ad the outputs of the ultiplier. Essetially, for every iput cobiatio ad correspodig error-free output the fuctio is equal to, while for every iput cobiatio ad erroeous output the fuctio is equal to 0. Presuably, sythesizig the behavior of the duplicate circuit ad the coparator as a oolithic etity should result i ore opportuities for hardware sharig ad optiizatio across the two odules. However, whe this fuctio is sythesized through the exact sae process as above, its cost exceeds the su of the costs of the duplicate circuit ad the coparator as sythesized separately. Clearly, this is a shortcoig of the sythesis syste, which is attributed to the aforeetioed reasos. Essetially, i this exaple, decoposed sythesis of the fuctio fids a less costly solutio tha oolithic sythesis. For a circuit with iputs ad outputs, oolithic sythesis searches i the space created by C variables, while decoposed sythesis searches i a uch saller space of oly variables. Therefore, the latter is ore efficiet i reducig the circuit cost sice it has a uch saller search space to explore. Moreover, the cost of the - bit coparator is sall, despite the fact that it is a fuctio of 2 variables. The reaso for this is that a -bit coparator is essetially a collectio of fuctios of two variables each, followed by a tree of depth log of 2-iput gates. Therefore, decoposed sythesis of duplicatio circuitry proves to be ore cost-effective. Of course, oe ay ot argue that this will always be the case. There is a circuit coplexity threshold below which the sythesis heuristics will yield better results for the oolithic circuit. Give the NP-hard ature of the proble, however, a ifored a priori decopositio ay sigificatly assist the sythesis tas ad reduce cost. 5. Copactio-based Extedig this observatio to the optial o-itrusive fuctio for restricted error odels discussed i Sectio 3, we aticipate that it will also lead to sub-optial results. I order to alleviate this proble, we propose a ethod that exploits the sae decopositio priciple i order to reduce the cost of o-itrusive for restricted error odels. 5.. Methodology overview The proposed solutio is a copariso-based, oitrusive ethod that utilizes the iforatio available i the restricted error odel i order to reduce the area cost. More specifically, it exploits the fact that for every iput a, the circuit eeds to distiguish betwee the error-free respose GM(a) ad erroeous resposes i the set BM(a), but ot betwee the error-free respose GM(a) ad erroeous resposes i the set DC(a), sice the latter will ever occur for faults i the prescribed odel. As a result, the resposes of the circuit ay be copacted ito a saller uber of bits, while preservig the iforatio ecessary to idetify all errors i the restricted error odel. Subsequetly, it is ot ecessary to predict through A B A B -Bit Multiplier C Duplicate -Bit Multiplier Cost = Bit Coparator Cost = Bit Multiplier C Cocurret Error Detectio Circuit = iff C=A*B Cost = 9920 (a) (b) Fig. 2. Decoposed vs. oolithic sythesis of duplicatio-based circuit.

4 S. Aluhaizi et al. / Microelectroics Joural 36 (2005) duplicatio the value of all output bits ad copare to the actual respose of the circuit. Istead, it is sufficiet to predict ad copare to the copacted resposes which coprise fewer bits. The proposed schee is depicted i Fig. 3 for a circuit with iputs ad outputs. A copactor is added to copact the -bit output ito bits, sufficiet to distiguish betwee error-free ad possible erroeous resposes. A predictor is cosequetly required to predict the value of the -bit resposes for each -bit iput. Fially, a -bit coparator is eployed to idicate ay discrepacy betwee the predicted ad the actual copacted respose. I essece, this ethod decoposes the odel of the optial solutio discussed i Sectio 3 ito a copactor, a predictor, ad a coparator. This ca be thought of as a istace of the geeral schee of separate processig of chec sybols described i []. I a fashio siilar to duplicatio, this decopositio ca reedy the liitatios of sythesis discussed i Sectio ad provide a low cost circuit. As copared to duplicatio, the width reductio of the predicted respose is aticipated, o average, to result i a proportioal cost reductio. Additioally, the size of the coparator is also reduced, leadig to further cost savigs. I total, ad despite the additioal cost icurred by the copactor, the proposed ethod is expected to icur less area overhead tha duplicatio. I ters of effectiveess, the objective of the ethod is to detect all errors i a restricted error odel, as opposed to duplicatio that detects all errors i the urestricted error odel. Essetially, this is the trade-off for reducig the hardware cost of o-itrusive. I order to eet this objective, however, a alias-free copactor is required. Therefore, success of the proposed ethod relies o the ability to desig a alias-free copactor give the error-free ad possible erroeous resposes for each iput cobiatio Alias-free copactio Withi the cotext of the proposed ethod depicted i Fig. 3, a copactor is alias-free if the -bit copacted error-free respose GM(a) differs fro all -bit copacted erroeous resposes i BM(a), ca2[0,.,2 K]. I IN Cobiatioal Circuit Predictor -Bit Coparator Copactor Fig. 3. Copactio-based o-itrusive. essece, duplicatio ay also be viewed as a extree case of this ethod, wherei BM(a) coprises all 2 K possible erroeous resposes ad, therefore, Z. Cosequetly, the copactor i duplicatio-based is eliiated ad the predictor becoes a replica of the circuit. For the restricted error odel, however, the set DC(a), which cosists of circuit resposes that will ever occur for faults i the prescribed odel, allows alias-free copactio. As the size of the set BM(a) decreases ad the size of the set DC(a) icreases, the uber of copacted outputs reduces, resultig i a lower cost for the predictor circuit ad the copactor circuit. I order to idetify groups of copatible resposes, we costruct a graph G(V, E), through which we will evetually derive the fuctioality of the copactor. The set of vertices, V, icludes a vertex for every distict error-free ad erroeous respose of the circuit, while the set of edges, E, icludes all pairs of vertices represetig error-free ad erroeous resposes for ay circuit iput. More forally: V Z g fgmðaþ; BMðaÞg (2) ca2½0;.;2 KŠ ad ( E Z ðv ) ; v 2 Þ : v ; v 2 2V oda : (3) v Z GMðaÞov 2 2BMðaÞ I order to eet the costraits of a alias-free copactor, ay two odes coected by a edge i the graph eed to be copacted ito distict resposes. As a result, alias-free copactio reduces to the well-ow graph colorig proble. More specifically, the outputs of the copactor correspod to the bits ecessary to represet the uber of distict colors of the graph. Miiizatio of the uber of ecessary colors results i iiizatio of ad, o average, iiizatio of the cost of the copactor ad the predictor. While the proble is NP-coplete, several approxiatio algoriths have bee devised [2]. 6. Experietal results I order to evaluate the proposed copactio-based oitrusive ethod, we apply it o several circuits. To preserve geerality, we experiet with arbitrary circuits that were geerated through tables filled uiforly at rado. I these experiets, the circuits have a equal uber of iputs ad outputs. The restricted error odel coprises all errors resultig fro the sigle stuc-at fault odel, however, ay fault odel ca be used to geerate the error-free ad erroeous resposes. The circuits are coverted i pla forat, sythesized usig the rugged script of SIS [20] ad apped oto a stadard library coprisig 2-iput gates. Iterally developed software eployig fault siulatio is used to idetify the error-free ad

5 60 S. Aluhaizi et al. / Microelectroics Joural 36 (2005) erroeous resposes ad, thus, to geerate the coflict graph. Subsequetly, the graph colorig heuristic described i [2] is used to color the odes of the coflict graph. The fuctioality of the copactor ad the predictor is defied through assiget of biary codes to each color of a ode i the graph. Color ecodig is perfored radoly. Additio of a siple coparator copletes the costructio of the proposed ethod. We also costructed the three alterative approaches, aely decoposed sythesis of duplicatio-based, oolithic sythesis of duplicatio-based, ad oolithic sythesis of the optial fuctio for restricted error odels which was described i Sectio 3. For fairess, the sae sythesis process eployig the rugged script of SIS [20] is applied i all cases. The circuits are apped oto a stadard library coprisig 2-iput gates ad the area cost is obtaied through the prit_ap_stats coad. The results are aalytically preseted for the copoets of each ethod ad copared i the Table. The cost of duplicatio ad the proposed ethod are detailed i Table 2. The first observatio fro these tables is that due to the reasos outlied i Sectio, decoposed sythesis ideed outperfors oolithic sythesis. For the urestricted error odel, decoposed sythesis of duplicatiobased costs cosistetly less tha oolithic sythesis of duplicatio-based. Siilarly, for restricted error odels, the proposed decoposed ethod costs cosistetly less tha oolithic sythesis of the optial fuctio. Therefore, the proposed decopositio of fuctioality alleviates the sythesis liitatios. The secod observatio cocers the cost of the proposed ethod as copared to the cost of duplicatio. As ca be see, duplicatio is cheaper for the saller circuits, while the proposed ethod outperfors duplicatio for the larger circuits. I sall circuits, the coflict graph is deser, thus requirig relatively ay colors. For exaple, i the circuit with I/O, 3 bits are ecessary to achieve alias-free copactio of the four outputs. The predictor ad the coparator are ow cheaper tha i the case of duplicatio, yet ot eough to copesate for the cost of the copactor. As the uber of output bits icreases, however, the coflict graph becoes sparser ad fewer colors are eeded to color it. For exaple, i the circuit with 7 I/O, 3 bits are still adequate to achieve aliasfree copactio of the seve outputs. I this case, the cost reductio of the predictor ad the coparator surpluses the additioal cost of the copactor. Iterestigly, as the circuit size icreases, the uber of erroeous resposes appears to be growig uch slower tha the expoetially growig uber of possible resposes. As a result, coflict graphs becoe sparser ad the uber of bits ecessary to color the is a diiishig proportio of the output width. Thus, as the circuit size icreases, the proposed ethod is expected to provide higher savigs over duplicatio-based. 7. Discussio As deostrated above, the proposed decoposed approach outperfors oolithic sythesis ad reduces the cost of o-itrusive for restricted error odels well below the cost of duplicatio. Nevertheless, there are several poits where optiality is lost ad future iproveets ay therefore be achieved by addressig the. The first ad ost iportat optiality loss poit cocers colorig of the graph. While the ultiate objective is the iiizatio of the copactor, the proposed odel ais at iiizig the uber of colors i the graph. Eve if the solutio space is restricted to the iial uber of colors, a large uber of alterative colorigs exist. The colorig algorith, however, does ot tae hardware iiizatio ito accout while selectig aog the. As a result, the selected colorig ay lead to sub-optial cost results. Ufortuately, this is a very hard proble requirig that hardware cosideratios becoe part of the colorig algorith ad very little is ow i this area. The secod poit of optiality loss cocers the assiget of biary codes to the colors of the graph. Oce agai, the actual color ecodig ipacts directly the cost of the copactor. At preset, the proposed ethod Table Copariso of alterative ethods Circuit Decoposed duplicatio Proposed ethod Copariso Moolithic duplicatio (MD) Decoposed duplicatio (DD) Moolithic optial (MO) Proposed ethod (PM) DD/MD PM/MO PM/DD I/O I/O I/O I/O I/O I/O I/O N/T N/T N/T: sythesis did ot teriate withi the allocated CPU tie.

6 S. Aluhaizi et al. / Microelectroics Joural 36 (2005) Table 2 Detailed cost of the proposed copactio-based ethod ad the decoposed duplicatio Circuit Decoposed duplicatio Copactio-based Replica Coparator Copactor Predictor Coparator Colors Bits I/O I/O I/O I/O I/O I/O I/O assigs radoly biary codes to colors, thus possibly leadig to sub-optial cost results. This proble of assigig the optial biary codes to the colors reduces, essetially, to sybolic iiizatio ad ecodig [9] that has bee studied extesively both for two-level ad for ulti-level logic optiizatio. The third poit of optiality loss cocers the decoposed sythesis of the predictor ad the copactor. The aforeetioed decisios o graph color assiget ad color ecodig affect ot oly the cost of the copactor but also the cost of the predictor. Optiizig these decisios for oe of these two odules ay adversely affect the other. Oe way to alleviate this proble is to copare ad select aog the two sequetial choices, wherei decisios are tued towards optiizig oe of the two odules. O a positive ote, the proposed ethod is extedible to FSMs. Cotrollers are typically optiized for perforace ad, therefore, o-itrusive techiques are highly desirable. Cosider, for exaple, the FSM odel depicted i Fig., coprisig a Next State/Output cobiatioal logic of C iputs ad C 2 outputs, as well as a state register of bits. The proposed ethod ay be applied directly to the cobiatioal logic. However, errors caused by the State Register will ot be detected. To resolve this proble, the 2 output bits are held i a additioal register ad the copactio is perfored with a latecy of oe cloc cycle, siilar to the approach i [7]. Siilarly, the predictio results are delayed by a cloc cycle through a register ad the copariso is perfored i the ext cloc cycle. Errors i both the cobiatioal logic ad the State Register will be detected, at the cost of a costat latecy of oe cloc cycle.. Coclusio Despite the siplicity of odellig the optial oitrusive ethod for restricted error odels, obtaiig the circuit through sythesis does ot always yield a optial ipleetatio. The o-itrusive ethod proposed herei deostrates that alterative proble odellig, which taes ito accout the shortcoigs of sythesis, reduces sigificatly the cost of the circuit. Sythesis liitatios are alleviated through a decoposed schee, siilar to duplicatio-based for the urestricted error odel. Cost reductio over duplicatio is achieved through alias-free copactio of circuit resposes, which results i predictio ad copariso of a saller uber of fuctios, ad thus, to sigificatly less hardware. While liitatios exist ad a uber of opportuities for further optiizatio have bee idetified ad are curretly explored, the proposed ethod costitutes -BIT INPUT 2 -BIT PUT NEXT STATE/PUT COMBINATIONAL LOGIC 2 -BIT PUT PREDICTION LOGIC PREDICTION HOLD REGISTER -BIT PREVIOUS STATE -BIT NEXT STATE STATE REGISTER PUT HOLD REGISTER 2 COMPACTION LOGIC INEQUALITY COMPARATOR Fig.. Extesio to FSMs.

7 62 S. Aluhaizi et al. / Microelectroics Joural 36 (2005) a first step towards applicable, low-cost, o-itrusive for restricted error odels. Refereces [] M. Gossel, S. Graf, Error Detectio Circuits, McGraw-Hill, Lodo, 993. [2] S. Mitra, E.J. McClusey, Which cocurret error detectio schee to choose Iteratioal Test Coferece (2000) pp [3] G. Aseova, E. Sogooya, Desig of self-checig built-i chec circuits for autoata with eory Autoatio ad Reote Cotrol 36 (7) (975) [] S. Dhawa, R.C. De Vries, Desig of self-checig sequetial achies, IEEE Trasactios o Coputers 37 (0) (9) [5] N.K. Jha, S.-J. Wag, Desig ad sythesis of self-checig VLSI circuits, IEEE Trasactios o Coputer-Aided Desig of Itegrated Circuits ad Systes 2 (6) (993) 7 7. [6] S. Taric, Boudig error asig i liear output space copressio schees Asia Test Syposiu (99) pp [7] C. Zeg, N. Saxea, E.J. McClusey, Fiite state achie sythesis with cocurret error detectio Iteratioal Test Coferece (999) pp [] K.K. Saluja, et al., A cocurret testig techique for digital circuits, IEEE Trasactios o Coputer-Aided Desig of Itegrated Circuits ad Systes 7 (2) (9) [9] I. Voyiatzis, et al., R-CBIST: a effective RAM-based iput vector oitorig cocurret BIST techique Iteratioal Test Coferece (99) pp [0] R. Shara, K.K. Saluja, A ipleetatio ad aalysis of a cocurret built-i self-test techique Fault Tolerat Coputig Syposiu (9) pp [] P. Drieas, Y. Maris, No-itrusive desig of cocurretly selftestable FSMs Asia Test Syposiu (2002) pp [2] P. Drieas, Y. Maris, SPaRe: selective partial replicatio for cocurret fault detectio i FSMs Iteratioal Coferece o VLSI Desig (2003) pp. 9. [3] N.A. Touba, E.J. McClusey, Logic sythesis of ultilevel circuits with cocurret error detectio, IEEE Trasactios o Coputer- Aided Desig of Itegrated Circuits ad Systes 6 (7) (997) [] E. Sogooya, Desig of built-i self-checig oitorig circuits for cobiatioal devices, Autoatio ad Reote Cotrol 35 (2) (97) [5] V.V. Dailov, N.V. Kolesov, B.P. Podopaev, A algebraic odel for the hardware oitorig of autoata, Autoatio ad Reote Cotrol 36 (6) (975) [6] D. Das, N.A. Touba, Sythesis of circuits with low-cost cocurret error detectio based o Bose-Li codes, Joural of Electroic Testig: Theory ad Applicatios 5 (2) (999) [7] R.A. Parehji, et al., Cocurret error detectio usig oitorig achies, IEEE Desig ad Test of Coputers 2 (3) (995) [] J.F. Meyer, R.J. Sudstro, O-lie diagosis of urestricted faults, IEEE Trasactios o Coputers 2 (5) (975) [9] G. De Micheli, Sythesis ad Optiizatio of Digital Circuits, third ed., McGraw-Hill, New Yor, 99. [20] E.M. Setovich et al., SIS: a syste for sequetial circuit sythesis, ERL MEMO. No. UCB/ERL M92/, EECS UC, Bereley, CA 9720, 992. [2] Networ resources for colorig a graph, Available fro gsia.cu.edu/color/color.htl