MICROLOK II Integrated Vital Interlocking, Coded Track Circuit, and Non-Vital Code Line Controller

Transcription

1 \ Unin Switch & Signal Inc., an Ansald Signal cmpany 1000 Technlgy Drive, Pittsburgh, PA Russell Street, Batesburg, SC SM 6800B MICROLOK II Integrated Vital Interlcking, Cded Track Circuit, and Nn-Vital Cde Line Cntrller Hardware Installatin Installatin Maintenance Cpyright 2005 SM 6800B, December 2005 Unin Switch & Signal Inc. Rev. 3

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3 Prprietary Ntice This dcument and its cntents are the prperty f Unin Switch & Signal Inc. hereinafter US&S). This dcument has been furnished t yu n the fllwing cnditins: n right r license under any patents r any ther prprietary right in respect f this dcument r its cntent is given r waived in supplying this dcument. This dcument and its cntent are nt t be used r treated in any manner incnsistent with the rights f US&S, r t its detriment, and are nt t be cpied, reprduced, disclsed t thers, r dispsed f except with the prir written cnsent f US&S. Imprtant Ntice US&S cnstantly strives t imprve ur prducts and keep ur custmers apprised f changes in technlgy. Fllwing the recmmendatins cntained in the attached service manual will prvide ur custmers with ptimum peratinal reliability. The data cntained herein purprts slely t describe the prduct, and des nt create any warranties. Within the scpe f the attached manual, it is impssible t take int accunt every eventuality that may arise with technical equipment in service. Please cnsult yur lcal US&S sales representative in the event f any irregularities with ur prduct. We expressly disclaim liability resulting frm any imprper handling r use f ur equipment, even if these instructins cntain n specific indicatin in this respect. We strngly recmmend that nly apprved US&S spare parts be used as replacements. SM 6800B, Rev. 3, December 2005 i

4 Revisin Histry Revisin Histry Rev. Date Nature f Revisin 3 December 2005 Incrprate ECO ; Crrected vltage levels fr Part N. N fr the Vital Input PCBs. ii SM 6800B, Rev. 3, December 2005

5 Appendix I Table f Cntents 1 General Infrmatin Intrductin Rail Team and Technical Supprt Hardware General Descriptin System Cmpnents Cardfile and Plug-In Cmpnents Installing a Micrlk II System Cardfile and Circuit Bard Installatin Installing the Cardfile Munting and Envirnment General Wiring Practices Pwer Input Surce Wiring and Surge Prtectin Cardfile Grunding Installing the Micrlk II Cardfile Plug-ins Circuit Bard Installatin Rules Keying Plug Installatin Printed Circuit Bard Jumper and Firmware Cnfiguratins Cnfiguring the CPU Bard Cnfiguring the Cde System Interface PCB Cnfiguring the Cab Amplifier PCB Cnfiguring the Cder Output PCB (Cde Rate Selectin) Cnfiguring the OS Track Circuit PCB Installing Micrlk II Circuit Bards and a Lcal Cntrl Panel PCB Cnnectr Assembly and Cardfile Address Setting General Cnnectr/Cable Assembly Cnstructin Ntes Shelf Munting Assembly Ntes Circuit Bard Cnnectins t External Circuits CPU Bard Vital Input PCBs Standard Vital Output PCBs Nise Prtectin Bi-plar Output PCB Vital Lamp Driver PCB Mixed Vital I/O Bards Nn-Vital I/O PCBs Cde System Interface PCB Cded Track Circuit PCBs OS Track Circuit PCB Cab Signal Cder PCBs and Cab Amplifier PCBs Address Select Jumper Settings AC Lamp Drive SM 6800B, Rev. 3, December 2005 iii

6 Appendix I 3 Installing Micrlk II System Peripheral Devices INSTALLING CODED TRACK AND CAB SIGNAL INTERFACE PANELS Cded Track and Cab Signal Panel Selectin Munting the Panels Cded Track Interface Panel Wiring, Grunding, and Surge Prtectin Track Leads and Surge Prtectin Grunding Track Plarity Installing a Terminatin Capacitr PCB Quick Shunt Mdule Applicatin and Installatin Cab Signal Interface Panel Wiring, Grunding and Surge Prtectin Single-Cab Signal Cnfiguratin Wiring Dual-Cab Signal Cnfiguratin Wiring VITAL CUT-OFF RELAY (VCOR) INSTALLATION AND WIRING POWER-OFF RELAY INSTALLATION AND WIRING ISOLATION MODULE INSTALLATION AND WIRING CONNECTING MICROLOK II TO EXTERNAL SERIAL DEVICES Cnnecting MICROLOK and GENISYS Prtcl Serial Prts Using Mdems Cnnecting GENISYS Prtcl Serial Prts Using Mdems Cnnecting MICROLOK Prtcl Serial Prts Using Mdems Cnnecting t RS-485 Serial Prts (Refer t Figure 3-10) Cnnecting t RS-423 Serial Prts (Refer t Figure 3-11) Cnnecting t RS-232 Serial Prts Islatin f Serial Prt Signal Cmmn Physical Cnnectins t Serial Prts Cnfiguring MICROLOK II Serial Prts Serial Prt Cnfiguratin fr Operatin n a Direct Wire, Pint-t-Pint, Cmmunicatin Circuit GENISYS Prtcl Serial Prt Cnfiguratin MICROLOK Prtcl Serial Prt Cnfiguratin Cnfiguring MICROLOK II CPU Serial Cmmunicatin Jumpers Panel Installatin and Pwer Input Interface Wiring SERIAL INTERFACE SCHEMATIC DIAGRAMS Installatin Parts List MAJOR SYSTEM ASSEMBLIES MAJOR CARDFILE COMPONENTS Plug-in Printed Circuit Bards and Frnt Panels Cde System Interface PCB Executive EPROMs PCB Interface Cable Assembly Cmpnents and Tls* Misc. Cardfile Installatin Parts POWER/SIGNAL CONDITIONING AND PROTECTION EQUIPMENT MISCELLANEOUS UNIT INSTALLATION HARDWARE iv SM 6800B, Rev. 3, December 2005

7 Appendix I List f Figures Figure Page Figure Cardfile Installatin Dimensins Figure Cardfile Pwer Input Wiring and Prtectin Figure Cardfile PCB and Panel Installatin Guidelines Figure Cardfile Slt Keying Plug Installatin Figure CPU Bard Jumper and Jumper Psitin Checks Figure Cde System PCB EPROM Installatin and Jumper Psitins Figure Cab Amplifier PCB Frequency-Select and Current-Limiting Jumpers Figure Cder Output PCB Jumper Setting fr Cab Signal Figure OS Track Circuit PCB Shunting Vltage Adjustment (Jumper) Figure PCB Wiring Cnnectr Munting and Integral Address Switch Bard Figure Shelf-Munting Kit Figure CPU PCB - Basic Interface Wiring Figure Vital Input PCB - Basic Interface Wiring Figure Standard Vital Output PCB - Basic Interface Wiring Figure Nn-vital Bi-plar Output PCB - Basic Interface Wiring and Crrespndence with Frnt Panel LEDs Figure Vital Lamp Driver PCB - Basic Interface Wiring Figure Mixed Vital I/O PCB - Basic Interface Wiring Figure Nn-Vital I/O PCB, LCP Versin - Basic Interface Wiring Figure Nn-vital I/O PCB, 32/32 Versin - Basic Interface Wiring Figure Nn-Vital, Islated NV.OUT32 PCB Basic Interface Wiring Figure Nn-Vital, Islated NV.IN32 PCB Basic Interface Wiring Figure Cded Track Circuit PCBs Basic Interface Wiring Figure Cde System Interface PCB - Basic Interface Wiring Figure Cded Track Circuit PCBs - Basic Interface Wiring Figure OS Track Circuit PCB - Basic Interface Wiring Figure Cder Output and Cab Amplifier PCBs - Basic Interface Wiring Figure Munting Dimensins fr Cded Track/Cab Signal Interface Panels and Quick Shunt Mdule. 3-2 Figure Cded Track Interface Panels - Basic Track Wiring Figure Terminatin Capacitr PCB Installatin n Cded Track Interface Panels Figure Cab Signal Interface Panel Basic Wiring - Single Cab Cnfiguratin Figure VCOR Relay Wiring Figure Pwer-ff Relay Design and Interface Wiring Figure Islatin Mdule Mechanical Design Figure Islatin Mdule Typical Wiring Figure Typical Adapter Panel Applicatin - Master and Slave Micrlk II Systems Figure Typical Micrlk II Master T Micrlk II Slave RS-485 Direct Wire Serial Interface Units Pwered By Same Battery (Micrlk Prtcl Or Half-Duplex Genisys Prtcl) Figure Typical Micrlk II Master T Micrlk II Slave RS-423 Direct Wire Serial Interface Units Pwered By Same Battery (Micrlk Prtcl Or Half-Duplex Genisys Prtcl) Figure Typical Micrlk II Master r Slave t RFL Mdem Serial Interface RS-232 Prt 4 with Serial Islatr (Micrlk r Genisys Prtcl) Figure Typical Micrlk II Master r Slave t RFL Mdem Serial Interface RS-423 Prt 3 with Serial Islatr (Micrlk r Genisys Prtcl) Figure Typical Micrlk II Master t Micrlk Slave Serial Interface RS-232 Prt 4 with Serial Islatr (Micrlk r Genisys Prtcl) Figure Typical Micrlk Master t Micrlk II Slave Serial Interface RS-423 Prt 3 with Serial Islatr (Micrlk Prtcl) Figure Typical Micrlk II Master t Micrlk Cmb Track Slave Serial Interface RS-423 Direct Wire Interface (Micrlk Prtcl) Units Pwered By Same Battery Figure Typical Micrlk II Master t Micrtrax EOS Slave RS-423 Direct Wire Serial Interface (Micrlk Prtcl) Units Pwered By Same Battery SM 6800B, Rev. 3, December 2005 v

8 Appendix I Figure Typical Cde System PCB Interface t Serial Line Carrier Figure Typical GENISYS 2000 Master T Micrlk II Slave RS-232 Direct Wire Serial Interface Units Pwered By Same Battery (Genisys Prtcl) Figure Typical GENISYS Master T Micrlk II Slave RS-232 Direct Wire Serial Interface Units Pwered By Same Battery (GENISYS Prtcl) List f Tables Table Page Table Micrlk II System Majr System Cmpnents Table Micrlk II Cardfile Plug-In Cmpnents Table Cardfile Mtherbard Keying Plug Lcatins Table CPU Bard Jumper Psitins Table Micrlk II PC Bard Cnnectr Cmpnents and Tls Table Micrlk II PC Shelf Munting Kit Table Cded Track and Cab Signal Interface Panel Applicatins vi SM 6800B, Rev. 3, December 2005

9 General Infrmatin 1 General Infrmatin 1.1 Intrductin This manual prvides the basic infrmatin necessary t install the Micrlk II system and its peripheral equipment (subject t cmpletin f training by a US&S -apprved surce). Tpics cvered include equipment preparatin, cnfiguratin and munting, cnnectin f perating pwer, installatin f plug-in bards, and typical printed circuit bard external circuit interfaces. Fr reference, related Micrlk II system manuals include: SM-6800A - Micrlk II System Descriptin SM-6800C - Micrlk II System Startup, Trubleshting, and Maintenance SM-6800D - Micrlk II System Applicatin Lgic Prgramming Other manuals that prvide infrmatin n related US&S systems include: SM-6700A - GENISYS Multi-Purpse Nn-vital Cntrl/Cmmunicatins System (Applicatin Lgic Prgramming) SM-6470A - MicrTrax Cded Track Circuit System Applicatin Lgic Prgramming SM-6470B - MicrTrax Cded Track Circuit System Hardware Installatin and Cnfiguratin SM-6700B - GENISYS-2000 Multi-Purpse Nn-vital Cntrl/Cmmunicatins System Hardware Installatin and Cnfiguratin US&S prvides n shp maintenance prcedures fr the Micrlk II system circuit bards. These bards are nt repairable in the field. 1.2 Rail Team and Technical Supprt The Rapid Actin Infrmatin Link (RAIL) team was created in 1996 t serve the technical needs f current and ptential US&S custmers. Cnvenient 24-hur access and a rapid reslutin t custmer prblems are the trademarks f this rganizatin. The RAIL team, which is staffed primarily by US&S prduct and applicatin engineers, is ready t assist and reslve any technical issues cncerning the Micrlk II system r any ther US&S prduct. Any questins regarding the cntents f this service manual shuld be directed t the RAIL team by telephne at r thrugh Internet at railteam@switch.cm. 1.3 Hardware General Descriptin The Micrlk II system cnsists f mdular cardfile-munted equipment and external peripheral devices that are used t interface the cardfile circuitry t the tracks and t ther assciated interlcking cntrl systems. SM 6800B, Rev. 3, December

10 General Infrmatin Sectins and that fllw prvide an verview f the hardware available fr use in the Micrlk II system System Cmpnents The Micrlk II interlcking cntrl system is a multi-purpse mnitring and cntrl system designed fr railrad and rail mass transit wayside interlcking functins such as switch machine and signal lamp cntrl, track circuit ccupancy mnitring, and nn-vital cde line cmmunicatins. Table 1-1 lists the majr cmpnents f the Micrlk II system that are cvered in this manual: Table Micrlk II System Majr System Cmpnents Name US&S Part N. Basic Functin(s) Micrlk II cardfile N Huses all plug-in printed circuit bards and an ptinal lcal cntrl panel. VCOR relay N (US&S PN-150B) Switches pwer t all cardfile vital utput circuits under the cntrl f the Micrlk II CPU bard. pwer-ff relay J Detects the failure f cmmercial pwer. islatin mdule N (12V) N (50V) N (24V) Prvides the equivalent f duble-break utput circuit islatin (fr line circuits r relays in a separate huse). Als enables bi-plar peratin f standard vital utputs. cded track interface panels N N N N cab signal interface panels N N Interfaces the Micrlk II system t mainline cded track circuits in nn-cab signal territry applicatins. Interfaces the Micrlk II system t mainline cded track circuits in cab signal territry applicatins. quick shunt mdule N Prvides reduced cded track circuit shunt respnse time in heavy traffic areas. Type A serial link islatr unit N Interfaces the cde system interface circuit bard (cardfile) t a Glenaire mdem r MCP in ARES and serial line carrier cde systems. Type B serial link islatr unit (t be determined) Interfaces the cde system interface circuit bard (cardfile) t ATCS systems. serial cmmunicatins adapter panel N Cnverts vital EIA serial link signals t 20mA current lp signals. Prtects serial cmmunicatins between different huses/cases. lcal cntrl panel N Optinal built-in LCP Cardfile and Plug-In Cmpnents The Micrlk II cardfile is designed t huse standard 6UX220 Eurcard plug-in printed circuit bards. Mst Micrlk II printed circuit bards are equipped with integral cntrls and indicatins n the bard s frnt panel. Sme Micrlk II circuit bards, hwever, (the OS track circuit PCB and ne versin f the pwer supply 1-2 SM 6800B, Rev. 3, December 2005

11 General Infrmatin bard, fr example) d nt have any cntrls r indicatins. These bards are munted behind blank frnt panels. In sme applicatins, the cardfile may be equipped with a lcal cntrl panel (LCP) that takes up several cardfile slts. The LCP is interfaced t the cardfile circuitry and t the external I/O thrugh a dedicated nnvital I/O printed circuit bard that ccupies a cardfile slt directly behind the LCP. Unused cardfile slts are cvered with blank shield panels. These panels cme in single slt and multi-slt widths. Each circuit bard/panel is attached t the cardfile frame with tw sltted-head machine screws. Tw extractin levers are prvided n each bard t make bard remval easier. The Micrlk II cardfile can be wall r shelf munted, and can be easily installed in a standard 19 equipment rack. External wiring is cnnected t each circuit bard thrugh a 48-pin r 96-pin cnnectr. Each cnnectr attaches directly t the bard s upper edge cnnectr at the rear f the card file. Certain cnnectr husings incrprate jumpers that are used t set the electrical address fr the assciated circuit bard. The CPU cnnectr husing has an internal EEPROM that is used t stre site-specific cnfiguratin data. Even if the CPU bard is replaced, the cnfiguratin data remains intact within the CPU cnnectr s EEPROM. The Micrlk II cardfile plug-in cmpnents cvered in this manual are listed in Table 1-2. See service manual SM-6800A fr a detailed descriptin f each circuit bard type. Table Micrlk II Cardfile Plug-In Cmpnents Name US&S Part N. Basic Functins CPU PCB N Prvides system vital cntrlling lgic, vital I/O management, external serial cmmunicatins, applicatin lgic executin, internal and external diagnstics, event lgging, and a user prgramming and diagnstics interface. pwer supply PCB N * N ** standard vital utput PCBs Bi-plar nn-vital utput PCB (12 bi-plar utputs) N (12V) N (24V) N Regulates and prtects external pwer input, cnditins and cnverts the battery input vltage t the varius vltage levels required fr cardfile circuitry peratin, prvides an islated surce fr external cntact sensing, and energizes the VCOR relay under the cntrl f the CPU bard. * Withut frnt panel (munted behind LCP) ** With frnt panel (n LCP installed in cardfile) Cntrls standard +/- vital utputs (switch machine relay cil r Micrlk II islatin mdule, fr example). Cntrls bi-plar utputs (t searchlight signal psitining mechanism, fr example). vital lamp driver PCB (16 lamps) N Cntrls signal lamps in clr lights and searchlight signals. SM 6800B, Rev. 3, December

12 General Infrmatin vital Input PCBs (16 inputs) Name US&S Part N. Basic Functins mixed vital I/O PCBs (eight inputs and eight utputs) N (12V) N (24V) N (50V) N (12V) N (24V) N (Input 50V, utput 24V)) Receives standard +/- r bi-plar vital inputs (search light mechanism psitin check, switch machine crrespndence, r OS track circuit ccupancy, fr example). Lw and high minimum threshld versins available. Prvides same I/O functins as standard vital utput PCB and vital input PCB n ne bard. Lw vltage (12V) and high vltage (50V in, 24V ut) versins are available. cde system interface PCB N Interfaces vital CPU with nn-genisys 2000 external cde system. nn-vital I/O PCB N (LCP) N (32/32) nn-vital islated PCB N (9.5-35V) nn-vital islated PCB N (9.5-35V) nn-vital islated PCB N (9.5-35V) cded track circuit PCBs N N N N LCP versin interfaces cardfile LCP nn-vital I/O with CPU. 32/32 versin used fr cnnectin t external I/O. LCP versin. 16 separate inputs fr cnnectin t external inputs. 32 utputs fr cnnectin t external utputs. 32 inputs fr cnnectin t external inputs. Prvides train detectin in mainline cded track circuits. Versins fr nn-cab applicatins and cab applicatins at varius frequencies. OS track circuit PCB N Prvides OS track circuit train detectin in endf-siding applicatins. cder utput PCB N Generates standard 75, 120 and 180 CPM cab signal cdes auxiliary cder utput PCB N Generates tw 50 CPM cab signal cdes 60/100 Hz cab amplifier PCB N Generates 60 r 100 Hz cab signal carrier 40/50 Hz Cab amplifier PCB N Generates 40 r 50 Hz cab signal carrier 1.4 Installing a Micrlk II System WARNING Failure t btain apprved training, and t act in accrdance with the prcedures and warnings utlined in these manuals, may result in serius persnal injury and/r prperty damage. This manual is generic in nature and is intended t cver the installatin f the Micrlk II system cardfile and its external supprt equipment fr all pssible applicatins f the system. The extent and cmplexity f each installatin depends n the applicatin, the equipment rdered fr the applicatin, and the as-shipped cnfiguratin f the equipment when it leaves the US&S factry. 1-4 SM 6800B, Rev. 3, December 2005

13 General Infrmatin In sme cases, the entire cmpliment f equipment may be pre-cnfigured and assembled at the factry. In ther cases, bard cnfiguratin and installatin may be dne at the installatin site. All f these factrs are determined mainly by custmer preference. Thus, the installatin prcess will differ smewhat frm jb t jb. Regardless f the specific cnfiguratin, there are five basic steps invlved in the installatin f a Micrlk II system. These are: 1. Install the Micrlk II cardfile. 2. Install the Micrlk II printed circuit bards and make the necessary wiring cnnectins fr each specific bard. 3. Install the necessary Micrlk II peripheral devices and make the necessary wiring cnnectins between the cardfile and the rails/interlcking equipment. 4. Make the necessary cmmunicatins cnnectins between the Micrlk II cardfile and ther remte train cntrl equipment. 5. Pwer up, cnfigure, and test the Micrlk II system. Steps 1 thrugh 4 are detailed in this manual. Nte that it may nt be necessary t perfrm all f these steps fr all Micrlk II applicatins. Step 5 actually includes a number f system checks and cnfiguratin prcedures. This infrmatin is cntained in service manual SM-6800C - Micrlk II System Startup, Trubleshting, and Maintenance. SM 6800B, Rev. 3, December

14 General Infrmatin 1-6 SM 6800B, Rev. 3, December 2005

15 2 Cardfile and Circuit Bard Installatin 2.1 Installing the Cardfile Munting and Envirnment Cardfile and Circuit Bard Installatin The Micrlk II cardfile may be munted in a standard 19-inch equipment rack, r n a wall r shelf using the fiberglass munting brackets supplied with the unit.* Keep the cardfile away frm surces f excessive heat r battery vaprs. Psitive ventilatin is nt required. Cardfile perating temperature limits are -40 t +70 C. Cardfile munting dimensins (including rear cnnectrs) are shwn in Figure 2-1. * The fiberglass munting bracket shuld be used t islate the cardfile frm earth grund Fiberglass Munting Brackets PCB Interface Cnnectr Husing Figure Cardfile Installatin Dimensins General Wiring Practices Micrlk II installatins that are wired in the field shuld be cnfigured t minimize crss talk between wires. Dirty wiring (cnnectins t external equipment) shuld be separated as much as pssible frm wires carrying electrnic data signals. Cables and wires in general shuld be kept as shrt as pssible t minimize induced line nise. (The input and utput wires shuld be twisted in pairs.) Case/huse wiring layuts shuld als be arranged t minimize nise. Switch heater wire runs, track leads, switch machine pwer wiring and any ther nisy wiring shuld be separated as much as pssible frm Micrlk II wiring, bth in the case r huse and in utside cable runs. Battery leads shuld be as shrt as pssible and must be islated as much as pssible frm nisy wiring. SM 6800B, Rev. 3, December

16 Cardfile and Circuit Bard Installatin Pwer Input Surce The Micrlk II cardfile requires a single, 12 Vdc (nminal) battery fr perating pwer. The requirements fr the dc input vltage are as fllws: Vltage: Startup Ripple Range Nminal Min. 9.8 t 16.2 Vdc 12.0 Vdc 11.5 Vdc 0.5 VP-P Current draw n the battery is determined by the applicatin cnfiguratin, (number f signal lamps, cab signal carrier frequency, etc.). A cnstant vltage type charger is recmmended fr the battery. Nte that the battery must be capable f prviding a minimum vltage f 11.5 Vdc at system start-up. (This means that anytime the OFF/On switch is perated, battery vltage must be at least 11.5 V. r the unit will nt start.) Wiring and Surge Prtectin Input pwer wiring t the Micrlk II cardfile is cnnected thrugh the 48-pin cnnectr attached t the back f the pwer supply PCB (N r N ). Figure 2-2 shws the typical installatin fr the battery input t the Micrlk II cardfile. Refer t sectin fr cnnectr wiring data. Internal system pwer (+5V, +/-12V) may als be supplied by an externally munted pwer supply instead f the plug-in PCB (N r N ). In this case the system VCOR must be cntrlled by the plug-in CPS Bard N The secnd drawing in Figure 2-2 shws the typical wiring fr this bard. CAUTION The surge suppressin devices described belw must be installed fr all Micrlk II applicatins. Failure t install these devices may result in damage t the pwer supply r the Micrlk II system circuitry due t vltage transients. restrictins are nt fllwed, damage t equipment culd result. Observe the fllwing guidelines when cnnecting battery pwer t the cardfile: 1. T minimize nise, keep the battery leads as shrt as pssible. Whenever pssible, the battery leads shuld be lcated entirely within the case r huse. 2. Lightning arrestrs shuld nt be used n the wiring between the battery and the cardfile. 3. Install 40 mm r 60 mm line-t-line and line-t-grund MOVs as fllws: a) If the feed is 110 Vac, use a Siemens B40K130 r B60K130, r a GE V131DA40 r V131BA60 (J582324). 2-2 SM 6800B, Rev. 3, December 2005

17 Cardfile and Circuit Bard Installatin b) If an islatin transfrmer is used, als install a blck type MOV n the transfrmer secndary line-tline. 4. Secndary surge suppressin (US&S USSP units) and cmmn mde filtering are nt required n the battery wiring t the cardfile. 250 Hz INPUT FROM CPU B12 IN E6 A12 A14 C12 SYSTEM POWER SUPPLY N A2 C2 A6 (+ ) (-) -12V ISOLATED OUTPUT 20MA. (-) VCOR (+ ) N12 USE FOR INPUTS OUTSIDE THIS CASE - MAX = 20MA. C14 A22 +5 E12 C22 N12 IN E14 A16 A18 C16 E22 A24 C24 E USE ONLY TO POWER O. S. TRK BD C18 A26-12 E16 C26 E18 E26 AUX SHUTDOWN (+ 5) C6 CPS ONLY BOARD N VCOR 250 Hz INPUT E6 A6 (-) (+ N12 FROM EXTERNAL SYSTEM POWER SUPPLY +5V +12 N12 A22 C22 E22 E24 A28 C28 E28 A30 C30 E30 SM 6800B, Rev. 3, December

18 Cardfile and Circuit Bard Installatin N12 (BATT-) T cardfile pwer supply PCB r external pwer supply cnverter B12 (BATT+) Transient Vltage Suppressr 5KP16A r 6KZ16A (US&S J ) 1 2 MOVs fr use in 110V system: US&S J582324, G.E. V131DA40, r Siemens B40K130 Prime Grund Bus 9.8V t 16.2V Battery 0.5V P-P Ripple Cnstant Vltage Charger 110V 1 1 Cmmercial 110 Vac Figure Cardfile Pwer Input Wiring and Prtectin 2-4 SM 6800B, Rev. 3, December 2005

19 2.1.4 Cardfile Grunding Cardfile and Circuit Bard Installatin All Micrlk II circuitry is islated frm the Micrlk II cardfile chassis. This allws the cardfile t be cnnected t earth grund fr shielding purpses if desired. Fr CE-cmpliant installatins, cardfiles must be grunded via the metal cardfile-munting brackets supplied with all Micrlk II units beginning in late Fr ther installatins, ptinal fiberglass munting brackets are available frm US&S t electrically insulate the cardfile frm its munting structure if desired. The part numbers fr these fiberglass brackets are: Right Left M M Installing the Micrlk II Cardfile Plug-ins Installing the Micrlk II system cardfile plug-ins is a fur-step prcess. Each f the fllwing steps must be perfrmed fr each circuit bard t be installed: Selecting the apprpriate cardfile slt fr each circuit bard (sectin 2.2.1). Cnfiguring the cardfile keying plugs fr each circuit bard (sectin 2.2.2). Cnfiguring the circuit bard jumpers and firmware just prir t installatin (sectin 2.2.3). Install the circuit bards (sectin 2.2.4) Circuit Bard Installatin Rules Observe the fllwing arrangement rules when installing Micrlk II printed circuit bards and a lcal cntrl panel (when applicable) int the card file: A. Refer t Figure 2-3. With the fllwing exceptins, any plug-in PCB may be installed in any cardfile slt: Slt 19 cannt be used because there is n crrespnding buss cnnectr. The cde system interface PCB shuld be installed in slt 20 at the far right hand side f the cardfile. This slt accmmdates the special width (1.1 inches) f this bard. Pwer supply PCB N , which has a tw slt wide frnt panel, shuld be used when a lcal cntrl panel is nt being used fr the applicatin. Pwer supply PCB N (n frnt panel) shuld nly be used when a lcal cntrl panel is t be installed. If the cardfile is t be equipped with a lcal cntrl panel: Nn-vital I/O PCB N must be psitined behind the lcal cntrl panel s that the rear 48-pin cnnectr n the panel engages the frnt cnnectr f the I/O bard. Fr example, if the LCP cvers slts 1 thrugh 7, the nn-vital I/O bard must be installed in slt 5. SM 6800B, Rev. 3, December

20 Cardfile and Circuit Bard Installatin Pwer supply bard N (withut frnt panel) must be psitined behind the LCP s that its LEDs are visible in the hles prvided n the panel. Fr example, if the LCP cvers slts 1 thrugh 7, the pwer supply bard must be installed in slt 6. The OS track circuit PCB is typically munted behind the LCP in any pen slt. US&S recmmends that the CPU bard be installed in slt 18 because it is a duble-width mdule that cvers the unusable space f slt 19. B. If needed, tw useable cardfile bard slts can be gained by nt installing a pwer supply bard. In this case, the cardfile must be pwered frm an external pwer supply that meets the applicable rating requirements (see sectin 3.1 f service manual SM-6800A). Refer t sectin in this manual fr the recmmended pwer supply wiring scheme. C. Any tw bards can be installed adjacent t ne anther withut cncern fr EMI r RF effects between the bards. Typically, the bards are gruped accrding t general functin (I/O with I/O and cded track with cded track, fr example). D. All unused slts and slts must be fitted with a blank shield panel s that the entire frnt face f the cardfile is cvered. Available blank panels include: Single slt shield panel: N Duble slt shield panel: N Blank LCP replacement panel: N E. Once the full set f PCBs is defined fr the applicatin, keying plugs must be installed in the lwer mtherbard cnnectrs. These plugs prevent insertin f the wrng replacement bard fr a given slt. Refer t sectin fr keying plug installatin prcedures. 2-6 SM 6800B, Rev. 3, December 2005

21 Cardfile and Circuit Bard Installatin Cde System Interface PCB (N ) Standard Lcatin fr Cde System Interface PCB (N ) Cardfile Slt N Nn-vital I/O PCB (N ) Pwer Supply PCB (N ) (withut frnt panel) Lcal Cntrl Panel Sample Lcatins fr LCP, Nn-vital I/O PCB (N ) and Pwer Supply PCB (N ) (N ) Typical PCB Installatin Slt N , 15 16, 17 18, PCB r Panel Lcal Cntrl Panel Bi-Plar Output PCB Blank Panel Vital Input PCB Mixed Vital I/O PCB Vital Lamp Driver PCB Blank Panel Cded Track PCB Cded Track PCB CPU PCB Cde System Interface PCB d Figure Cardfile PCB and Panel Installatin Guidelines SM 6800B, Rev. 3, December

22 Cardfile and Circuit Bard Installatin Keying Plug Installatin Each f the Micrlk II cardfile slts includes a 12-way female keying guide next t the 96-pin cnnectr. The guide is used t ensure installatin f the prper circuit bard in each cardfile slt after the cmplete cardfile bard cnfiguratin has been determined. Each bard is equipped with a crrespnding 12-way male keying guide; individual keying tabs are remved at the factry in a specific pattern fr the bard part number. Prir t installing a bard, insert keying plugs (part number J ) int the crrespnding cardfile mtherbard keying guide as shwn in Figure 2-4 and as listed in Table 2-1. If it becmes necessary t change the type f bard installed in a given slt, the previusly installed keying plugs can be remved using a knife r a pair f needle nse pliers. 96-pin (Female) Cnnectr n Cardfile Mtherbard Keying Plug N. 96-pin (Male) Cnnectr n PCB Insert Keying Plug J Per Table Printed Circuit Bard Adjacent Keying Plug Cnnectr (Female) Adjacent Keying Plug Cnnectr (Male) PCB Keying Tabs Set at Factry Figure Cardfile Slt Keying Plug Installatin 2-8 SM 6800B, Rev. 3, December 2005

23 Cardfile and Circuit Bard Installatin Table Cardfile Mtherbard Keying Plug Lcatins Printed Circuit Bard Part N. Keying Plug Lcatin (Figure 2-4) CPU N pwer supply (withut panel) N pwer supply (with panel) N standard vital utput (12V) N standard vital utput (24V) N nn-vital bi-plar utput N vital lamp driver N vital input (12V) n vital input (24V) n vital input (50V) N mixed vital I/O (12V) N mixed vital I/O (24V) N mixed vital I/O (50V) N Serial Link Relay PCB N cde system interface n nn-vital I/O N nn-vital I/O N nn-vital, islated N nn-vital, islated n nn-vital, islated N cded track circuit n cded track circuit n cded track circuit n cded track circuit n OS track circuit N cder utput N auxiliary cder utput N SM 6800B, Rev. 3, December

24 Cardfile and Circuit Bard Installatin Printed Circuit Bard Part N. Keying Plug Lcatin (Figure 2-4) /100 Hz cab amplifier N /50 Hz cab amplifier N CPS nly pwer supply n frnt panel CPS nly pwer supply - with frnt panel N N keying plugs N N keying plugs Printed Circuit Bard Jumper and Firmware Cnfiguratins There are five types f Micrlk II printed circuit bards that cntain jumpers and firmware that must be cnfigured befre each bard is installed. These bards are the CPU bard, the cde system interface PCB, the cab amplifier PCB, the cder utput PCB, and the OS Track Circuit PCB Cnfiguring the CPU Bard Jumper Settings (See Figure 2-5) Prir t installing the CPU bard in the Micrlk II cardfile, the fllwing jumpers (Table 2-2) shuld be checked t make certain they are in their prper psitins per the system applicatin lgic sftware r factry requirements. NOTE Bld face letters indicate basic peratin with the 21mHz system clck SM 6800B, Rev. 3, December 2005

25 Cardfile and Circuit Bard Installatin O P E N Currently, nly Rcker 1 is used. Rcker 1 is used t determine the frnt panel serial prt baud rate during bt mde peratins. OPEN=57600 BAUD CLOSED=19200 BAUD J M P 1 BOT L TOP F COM R J J J J J J J J J M M M M M M M M M P P P P P P P P P JMP25 L S J M P SW1 JMP27 N HZ JMP29=Bttm JMP28=Tp 1-2 = Lck 2-3 = Prgram J M P 2 8 J M P Jumpers 20-24: Psitin 1-2 = Lck Psitin 2-3 = Prgram F1 J M P2 1 F3 J M P2 0 J M P2 4 F2 J M P2 2 B O O T F4 J M P =OFF 2-3 = +5V 3-4 = +12V J M P1 J M P1 J M P1 J M P1 J M P1 J M P1 J M P J JMP M P 3 1 J M P Figure CPU Bard Jumper and Jumper Psitin Checks SM 6800B, Rev. 3, December

26 Cardfile and Circuit Bard Installatin Table CPU Bard Jumper Psitins Jumper ID Descriptin Psitin Ntes JMP1 Bttm PCMCIA 2 Wait States Psitin 2-3 JMP2 Nt installed JMP3 On-Bard RAM 1 Wait State Psitin JMP4 Tp PCMCIA 2 Wait States Psitin 2-3 JMP5 Nt installed JMP6 FLASH 1 Wait State Psitin JMP7 Enable COM4 RXD Psitin 1-2 JMP8 Enable COM4 DCD Psitin 1-2 JMP9 Disable Backplane CPU Reset Psitin 1-2 JMP10 COM1 TX.CLK is an Output Psitin 2-3 JMP11 COM3 Vltage Drive Levels RS-232 RS-423 Psitin 1-2 Psitin 2-3 JMP12 COM3 Vltage Drive Levels RS-232 RS-423 Psitin 1-2 Psitin 2-3 JMP13 COM3 TX.CLK is an Output Psitin 2-3 JMP14 COM3 TX.CLK is an Output Psitin 1-2 JMP15 COM4 RX.CLK=9.83Mhz Psitin 1-2 JMP16 COM3 RX.CLK=9.83Mhz Psitin 1-2 JMP17 COM2 RX.CLK=9.83Mhz Psitin 1-2 JMP18 COM1 RX.CLK=9.83Mhz Psitin 1-2 JMP19 Nt Available N/A JMP20 FLASH 3 Prgramming Language Lcked Psitin (Applicatin space) Prgram Psitin 2-3 JMP21 FLASH 1 Prgramming Language Lcked Psitin (Executive space) Prgram Psitin 2-3 JMP22 FLASH 2 Prgramming Language Lcked Psitin (Executive space) Prgram Psitin 2-3 JMP23 FLASH 4 Prgramming Language Lcked Psitin (Applicatin space) Prgram Psitin 2-3 JMP24 FLASH 1 Bt Blck Lcked Psitin (Bt space) Prgram Psitin 2-3 JMP25 Speaker Vlume Sft Lud Off Psitin 2-3 Psitin 1-2 Nt Installed JMP26 IRQ7 Off Psitin 2-4 JMP Nrmal Psitin JMP28 Tp PCMCIA Prgramming Vltage Lcked Prgram Psitin 1-2 Psitin SM 6800B, Rev. 3, December 2005

27 Cardfile and Circuit Bard Installatin Jumper ID Descriptin Psitin Ntes JMP29 Bttm PCMCIA Prgramming Vltage Lcked Psitin 1-2 Prgram Psitin 2-3 JMP30 FLASH Prgramming Vltage Off Psitin V Psitin V Psitin 3-4 JMP31 CPS Drive Nrmal Psitin Ntes: 1. If header psts are nt installed in these lcatins, n jumper is required. 2. Settings shwn in bldface are the nrmal jumper psitins, which lck the FLASH devices and prevent their cntents frm being mdified. Refer t the FLASH Prgramming Instructins fr further infrmatin DIP Switch SW1 This is an unused input; the rckers may be left in any psitin withut affecting nrmal system peratin PCMCIA Cards The CPU bard is designed t incrprate a PCMCIA memry card mdule t prvide additinal lgging capability fr the User Data Lg. Installatin The PC Card can be installed in the tp r bttm slt n the Micrlk II cntrller bard. The fllwing jumpers must be set crrectly: ID Descriptin Psitin JMP28 Tp PCMCIA Prg Vlt Prgram 2-3 JMP29 Bttm PCMCIA Prg Vlt Prgram 2-3 JMP30 FLASH Prg Vlt 5V r 12 V 2-3 r 3-4 Use f the PC Card The PC Card is used t expand the User Data Lg lgging capability. Currently nly ne type f FLASH card will be recgnized by the executive sftware: INTEL 28F008S5. This chip has an Intelligent Identifier f 89A6h. Any SRAM card may be used in the system. Current restrictins f the hardware limit the size f the PC Card t a maximum f 6Mb. A 4Mb FLASH Card (J ) is available frm US&S. Infrmatin stred n the PC Card includes: Executive and Applicatin CRCs First and last numeric ID numbers All ID Names fr applicatin variables User Data Lg infrmatin If n PC Card is installed, then the User Data Lg is stred in internal RAM. SM 6800B, Rev. 3, December

28 Cardfile and Circuit Bard Installatin At reset, the card is detected and checked fr crrect CRCs and IDNames. IF the CRCs r IDNames d nt match the nes present in the executive and applicatin sftware, the PC Card will be erased and started as a new card. If these items are valid, the executive sftware finds the starting and ending lcatin fr any data stred n the card. If the sftware cannt find a starting/ending lcatin, r finds an invalid recrd n the card, it will be erased. Suggested Applicatin Cde Display PC Card's Health n a frnt panel NV.ASSIGN ((PCMCIA.INSTALLED & BATTERY.HEALTH) & (LOG.OK flasher)) TO LED.X; PCMCIA.INSTALLED - System Bit BATTERY.HEALTH - System Bit LOG.OK - System Bit flasher - Tggling 0.5 secs ON / 0.5 secs OFF X - 1 thrugh 8 fr frnt panel LED The LED will be ON steady whenever the PC Card is installed and lgging infrmatin. It will be dark if n PC Card is installed. It will be flashing if a PC Card is installed but write-prtected Cnfiguring the Cde System Interface PCB EPROM Installatin (see Figure 2-6) CAUTION When handling any Micrlk II circuit bard r bard cmpnent, bserve all electrstatic discharge (ESD) precautins. Imprper handling f bards r cmpnents may result in damage t static sensitive circuitry. The Micrlk II cde system interface PCB is shipped withut executive r applicatin sftware EPROMs. Fur EPROMs are required fr system peratin. This includes tw executive EPROMs and tw applicatin EPROMs. The sckets fr these chips are marked as fllws: EXEC EVEN - scket U7 EXEC ODD - scket U6 APPL EVEN - scket U5 APPL ODD - scket U SM 6800B, Rev. 3, December 2005

29 Cardfile and Circuit Bard Installatin Install the executive and applicatin sftware EPROMs accrding t their labels, with the Even EPROMs inserted in the EVEN sckets, and the Odd EPROMs inserted in the ODD sckets. When installing an EPROM, make certain the chip has the prper pin rientatin and is fully inserted. Executive EPROMs must be selected accrding t the type f cde system emulatin. Check the label n the chip t make certain the prper EPROM is installed fr the cde applicatin. Refer t the fllwing tabulatin fr applicatin EPROM part numbers. Applicatin US&S Part N. ATC/PTS N US&S GENISYS N Harmn MCS-1 N WB&S S2 N Allen Bradley DF1 N ARES N GRS Datatrain II N GRS Datatrain VIII N US&S GENISYS Dual Slave N US&S GENISYS Dual Ind. N Slave Refer t Service Manual SM-6700A fr EPROM prgramming prcedures. SM 6800B, Rev. 3, December

30 Cardfile and Circuit Bard Installatin C J P 4 J P 2 J P 3 A A C A C J P 5 J P 1 A C A C A P P L E X E C O D D E V E N U4 U6 U5 U7 J P 6 A C J P 7 A C J P 8 A C Figure Cde System PCB EPROM Installatin and Jumper Psitins 2-16 SM 6800B, Rev. 3, December 2005

31 Cardfile and Circuit Bard Installatin Genisys 2000 CSIB Cntrller Bard Jumpers GENISYS 2000 CSIB Cntrller Bard Jumpers JUMPER FUNCTION POSITION EFFECT JP1 Slave prt 2 - AB External synchrnus transmit clck BC* Internal JP2 Slave prt 1 - AB External synchrnus transmit clck BC* Internal Slave prt 2 - AB External JP3 asynchrnus clck; synchrnus receive clck BC* (1) Internal Slave prt 1 - AB External JP4 asynchrnus clck; synchrnus receive clck BC* (1) Internal JP5 Slave prt 2 - AB* Internal synchrnus transmit clck BC External JP6 Watchdg functin AB Disabled BC* (2) Enabled AB* (3) 1200 ms. JP7 Watchdg time-ut BC 150 ms. OPEN 600 ms. JP8 Bus enable AB* Disabled BC Enabled * Indicates factry cnfiguratin. 1. Fr asynchrnus serial prt peratin, asynchrnus clck must be set t internal. External psitin is used fr synchrnus cmmunicatin nly. 2. Watchdg MUST be enabled fr all nrmal peratin. Disabled psitin is fr factry test nly. 3. Factry watchdg setting shuld nt be changed. Lwering watchdg time-ut culd affect cntrller reliability Jumper Settings fr GENISYS / 5XX, S2, and MCS-1 Slave Applicatins Jumper Settings fr GENISYS / 5XX, S2, and MCS-1 Slave Applicatins Jumper Psitin Jumper Psitin JP1 BC JP5 BC JP2 BC JP6 BC JP3 BC JP7 AB JP4 BC JP8 AB SM 6800B, Rev. 3, December

32 Cardfile and Circuit Bard Installatin Jumper Settings fr ATCS Cmmunicatin Applicatin Jumper Settings fr ATCS Cmmunicatin Applicatin Jumper Psitin Jumper Psitin JP1 BC JP5 AB JP2 BC JP6 BC JP3 AB JP7 AB JP4 AB JP8 AB Jumper Settings fr ARES Cmmunicatin Applicatin Jumper Settings fr ARES Cmmunicatin Applicatin Jumper Psitin Jumper Psitin JP1 AB JP5 BC JP2 AB JP6 BC JP3 AB JP7 AB JP4 AB JP8 AB Cnfiguring the Cab Amplifier PCB Fr Micrlk II installatins that are cnfigured fr cab signal generatin, the apprpriate carrier frequency must be jumper-selected n the cab amplifier PCB. Set jumper JMP-2 as shwn in Figure 2-7 t select 60 Hz r 100 Hz peratin n PCB 6401, r 40 Hz r 50 Hz peratin n PCB Als, psitin jumper JMP-1 t the HIGH psitin as shwn in Figure 2-7. The psitin f this jumper may be changed during system cnfiguratin after the cab signal current levels have been set. Sectin f service manual SM-6800C cvers this prcedure SM 6800B, Rev. 3, December 2005

33 Cardfile and Circuit Bard Installatin 60/100 Hz Cab Amplifier PCB r 40/50 Hz Cab Amplifier PCB Current Limiter Jumper: LOW Psitin: Shrt Track Circuits. Set when using taps 1 and/r 2 n cab interface panel. Frequency Select Jumper: 60 r 100 Hz (40 r 50 Hz)* HIGH Psitin: Lng Track Circuits. Set when using taps 3 and/r 4 n cab interface panel. HIGH JMP1 LOW 60 Hz 100 Hz JMP2 *NOTE: On the 40/50 Hz Cab Amplifier PCB, these jumper psitins are labeled 40 Hz and 50 Hz. Figure Cab Amplifier PCB Frequency-Select and Current-Limiting Jumpers SM 6800B, Rev. 3, December

34 Cardfile and Circuit Bard Installatin Cnfiguring the Cder Output PCB (Cde Rate Selectin) The cder utput PCB is equipped with a single jumper fr setting the number f different cde rates used by the Micrlk II system. Set this jumper t the 3-CODE psitin when the system is t be set up fr the three standard cde rates f 75, 120 and 180 CPM. When the system incrprates additinal cde rates frm the auxiliary cder PCB, set this jumper t the 6-CODE psitin. Figure 2-8 shws the jumper psitin n the bard. 6-CODE JP1 3-CODE Number Of Cab Signal Cde Rates: 3-CODE Psitin: 75, 120, 180 CPM 6-CODE Psitin: 75, 120, 180 CPM Plus Additinal Cdes frm Auxiliary Cder PCB Cder Output PCB Figure Cder Output PCB Jumper Setting fr Cab Signal 2-20 SM 6800B, Rev. 3, December 2005

35 Cardfile and Circuit Bard Installatin Cnfiguring the OS Track Circuit PCB As shwn in Figure 2-9, a jumper is prvided n the OS Track Circuit PCB (N ) fr the purpse f selecting ne f the fur pssible psitins. JP1 represents the lwest pwer setting and JP4 represents the highest. 1. Cnnect vltmeters acrss the MICROTRAX inputs. 2. Select the lwest pwer setting that results in at least 12V dc n bth inputs. 3. Verify this setting by playing a 0.06 hm track shunt acrss each leg f the OS circuit, ne leg at a time. Each shunt must result in at least ne f the tw input vltages drpping belw 3V dc. SM 6800B, Rev. 3, December

36 Cardfile and Circuit Bard Installatin JP1 JP2 JP3 JP4 O.S. TRACK CIRCUIT PCB N O.S. TRACK SHUNTING VOLTAGE ADJUSTMENT MOVE ONE JUMPER BETWEEN JP1 AND JP4 TO ADJUST SHUNTING VOLTAGE OS Receiver 1 OS Transmitter OS Receiver 2 T MICROTRAX Vital Inputs V V MICROTRAX RIGHT CONNECTOR Figure OS Track Circuit PCB Shunting Vltage Adjustment (Jumper) 2-22 SM 6800B, Rev. 3, December 2005

37 Cardfile and Circuit Bard Installatin Installing Micrlk II Circuit Bards and a Lcal Cntrl Panel US&S recmmends that pwer is remved frm the cardfile befre remving r installing circuit bards. Use the fllwing the prcedure t install the Micrlk II plug-in circuit bards: 1. US&S prvides stickers with each Micrlk II system that are used t identify the type f circuit bard installed in each cardfile slt. Obtain the prper sticker fr the bard t be installed. Attach the sticker t the inside bttm surface f the cardfile. Make certain that the arrw n the sticker pints tward the apprpriate card slt. 2. Hld the circuit bard t be installed vertically in frnt f the cardfile. 3. Insert the bard upper and lwer edges int the plastic card guides inside the cardfile. CAUTION When installing any Micrlk II circuit bard int the card file, d nt attempt t frce the bard int the slt. Damage t the circuit bard and mtherbard 96-pin cnnectrs may result. If resistance is encuntered when installing a bard, gently rck the bard t engage the male and female cnnectrs. If the bard still cannt be fully inserted int the card slt, remve the bard frm the cardfile and attempt t determine the surce f the resistance. 4. Gently push the bard int the cardfile until the bard and cardfile 96-pin cnnectrs are fully engaged. If the bard has an integral frnt panel, make certain that the rear face f the frnt panel is flush against the frnt f the cardfile. 5. If the bard has an integral frnt panel, secure the bard int psitin using the tw retaining screws attached t the frnt panel. Use the fllwing prcedure t install a lcal cntrl panel: 1. Psitin the LCP ver the frnt f the cardfile. 2. Align the cnnectr n the rear f the LCP with the cnnectr n the frnt f the nn-vital I/O bard (N ) in cardfile slt Gently press the LCP nt the frnt face f the cardfile. Make certain that the rear f the LCP is flush with the frnt face f the cardfile. Als, ensure that the tw LEDs n the pwer supply bard (installed behind the LCP) are prperly aligned with the assciated hles in the LCP. 4. Secure the LCP in psitin using the fur retaining screws that are attached t the LCP frnt panel. SM 6800B, Rev. 3, December

38 Cardfile and Circuit Bard Installatin 2.3 PCB Cnnectr Assembly and Cardfile Address Setting General NOTE Refer t Sectin 3 fr Micrlk II printed circuit bard interfaces t external circuits. Individual Micrlk II circuit bards are interfaced (as applicable) t external circuits using cnnectr/cable assemblies with a 48-pin r 96-pin female cnnectr husing that attaches directly t the matching cnnectr n the applicable circuit bard. All bards except the 96-pin nn-vital I/O PCB (N ) use the 48-pin cnnectr. Each cnnectr husing is secured t the cardfile backplane with fur small machine screws (see Figure 2-10). The cmplete cnnectr/cable assemblies may be assembled t rder by US&S, r assembled by the user. The cnnectr cable assemblies prvide discrete wiring fr all available I/O pints n each PCB. As shwn in Figure 2-9, wire bundles are ruted thrugh a prtective sleeve n ne f the tw wiring penings f the cnnectr husing. Fr mst applicatins, the cable assemblies utilize nly ne cable pening n the cnnectr husing. Hwever, nn-vital I/O PCB N may need t use bth penings t accmmdate the full set f 32 input and 32 utput wires. Fr sme Micrlk II circuit bards, the cnnectr husing als includes an Address Select PCB with six twpsitin jumpers used t set the cardfile electrical address f the assciated bard. These addresses are defined in the Micrlk II vital applicatin lgic (refer t sectin ). The jumper settings must exactly match the values set in the applicatin prgram t ensure nrmal system peratin. The fllwing circuit bards d nt require a cardfile bus address and d nt have jumpers included with the cnnectr husing: CPU bard cde system interface pwer supply OS track circuit cab amplifier auxiliary cder utput US&S prvides stickers with each Micrlk II system that depict individual cnnectr jumpers. After each jumper has been attached t the assciated cardfile cnnectr, affix a sticker t the cardfile frame directly belw the cnnectr. Use a pen r indelible marker t mark each jumper psitin n the sticker. An EEPROM is included within the special cnnectr husing used fr the CPU bard. This chip hlds sitespecific cnfiguratin data and allws the CPU t be changed while keeping the chip prgramming intact Cnnectr/Cable Assembly Cnstructin Ntes User assembly f the Micrlk II cnnectr/cable requires the parts and tls shwn in Table 2-3: 2-24 SM 6800B, Rev. 3, December 2005

39 Cardfile and Circuit Bard Installatin Table Micrlk II PC Bard Cnnectr Cmpnents and Tls Figure 2-9 Item Descriptin US&S Part N. Cmments/Vendr Part N. cnnectr husing assembly 48-pin 96-pin J J Used with mst PCBs. Used with nn-vital I/O PCB N cnnectr receptacle 48-pin J pin J receptacle munting screw J Munts bth 48-pin r 96-pin receptacle. guide pin J pin J wire crimp cntact 48-pin, #16 t #20 wire j Harting pin, #20 t #26 wire j Harting pin, #20 t #28 wire j Harting crimp tl, fr: pin, #16 t #20 wire Harting tl pin, #20 t #26 wire Harting tl pin, #20 t #28 wire Harting tl extractin tl, fr: pin, #16 t #20 wire Harting tl pin, #20 t #26 wire (Cntact US&S) 96-pin, #20 t #28 wire Harting tl insertin tl, fr: pin, #16 t #20 wire (Cntact US&S) 48-pin, #20 t #26 wire (Cntact US&S) 96-pin, #20 t #28 wire Harting tl lcatr tl, fr: pin, #16 t #20 wire Harting tl pin, #20 t #26 wire (Cntact US&S) 96-pin, #20 t #28 wire Harting tl Address Select PCB Used t set cardfile slt address 48-pin husing n n selected PCBs. 96-pin husing n N replaces N N replaces N SM 6800B, Rev. 3, December

40 Cardfile and Circuit Bard Installatin Fig Item Descriptin US&S Part N. Cmments/Vendr Part N. cnnectr husing assembly 1 48-pin 96-pin J J Used with mst PCBs. Used with nn-vital I/O PCB N cnnectr receptacle 2 48-pin 96-pin J J SM 6800B, Rev. 3, December 2005

41 Cardfile and Circuit Bard Installatin Narrw (96-pin) Cnnectr Per View A C1 B1 A1 Wide (48-pin) Cnnectr per View A E1 C1 A1 4 1 C32 B32 A32 E32 C32 A SW1 0 1 SW2 0 1 Narrw 96-pin Cnnectr: Fr Nn-Vital I/O PCB N Only Wide 48-pin Cnnectr: Fr All Other PCBs SW3 0 1 SW4 0 1 SW5 0 1 SW6 0 1 Husing Cver Husing Assembly Screws Address Select PCB Figure PCB Wiring Cnnectr Munting and Integral Address Switch Bard SM 6800B, Rev. 3, December

42 Cardfile and Circuit Bard Installatin Shelf Munting Assembly Ntes Shelf munting requires the use f the kit shwn in Table 2-4: Table Micrlk II PC Shelf Munting Kit Figure 2-11 Item Descriptin US&S Part N. Cmments/Vendr Part N. 1 Shelf munting kit X Installatin standffs included - in Shelf Munting Kit using existing hardware frm frnt-munting angles. 1 Figure Shelf-Munting Kit 2-28 SM 6800B, Rev. 3, December 2005

43 Cardfile and Circuit Bard Installatin 2.4 Circuit Bard Cnnectins t External Circuits The cnfiguratin f the external wiring t each Micrlk II printed circuit bard depends entirely n the bard type and the selected applicatin. Sectins thrugh that fllw, detail the specific cnnectin requirements fr each type f Micrlk II circuit bard CPU Bard The CPU bard cntains the central cntrlling lgic and diagnstic mnitring fr the Micrlk II system, and prvides serial five data prts. Fur f these prts are used fr cmmunicatin with external systems (see Figure 2-25). The fifth prt enables the cnnectin f a laptp PC fr sftware maintenance, diagnstics, and data lg dwnlading. This diagnstic prt is terminated at the 9-pin cnnectr n the CPU bard frnt panel The fur general purpse prts can be used fr vital serial cmmunicatins with anther Micrlk II system, a Micrlk system, r ne f the MicrTrax systems (cded track, end-f-siding r cab signal cntrller). Fr installatins where the Micrlk II system is cmmunicating with anther vital system in the same huse r case, the maximum serial cable length is 50 ft. A mdem is required fr cables lnger than 50 ft. Fr lcatins where the Micrlk II system and the remte vital system are lcated in different cases r huses, US&S recmmends the use f a serial cmmunicatins adapter panel (N ). This device cnverts EIA-level signals t 20mA current lp signals, and is designed t prtect signal lines frm transient line nise. Serial cmmunicatins adapter panels are required at bth the Micrlk II lcatin and the remte lcatin. Refer t sectin 3.6 fr panel installatin and wiring. The fur cnfigurable prts can als be used as a nn-vital channel t interface the Micrlk II system t an external GENISYS-2000 nn-vital cde system. In this cnfiguratin, the nn-vital applicatin lgic resides in the CPU bard alng with the vital applicatin lgic. Alternately, the cde system interface PCB can be used t interface the Micrlk II system t an external GENISYS-2000 system. In this applicatin, the nn-vital applicatin lgic resides n the cde system interface PCB. Refer t sectin fr external cnnectins t the cde system interface PCB. SM 6800B, Rev. 3, December

44 Cardfile and Circuit Bard Installatin Figure CPU PCB - Basic Interface Wiring 2-30 SM 6800B, Rev. 3, December 2005

45 2.4.2 Vital Input PCBs Cardfile and Circuit Bard Installatin Each f the vital input PCBs can accept up t 16 islated inputs. The specificatins fr these bards are as fllws: US&S Part N. Nm. Input Vltage Min. Vltage t Ensure ON State Vltage t Ensure OFF State Max. Sustained Input Vltage N V 9.5V 7.0V r less 34V N V 17.0V 9.0V r less 62V N V 35.0V 15.0V 72V There are n pwer cnnectins required thrugh the upper cnnectr. When wiring a vital input PCB t a relay cntact circuit cntained in the same huse as the Micrlk II cardfile, the signal battery may be used as the energy surce t activate the inputs. Terminals designated (-) may be cnnected t battery N12 and B12 switched ver relay cntacts. When wiring a vital input PCB t a relay cntact circuit utside the Micrlk II huse, use the islated surce that is part f the pwer supply. This is cnsistent with the practice f cnfining signal battery t the case in which the Micrlk II unit is hused. External wiring shuld be prtected with equalizer lightning arrestrs frm line-t-line (US&S part number N ) and with high vltage arrestrs frm line-t-grund (US&S part number N ). As shwn in Figure 2-13, inputs can als be wired in a bi-plar cnfiguratin. Nte in the Figure 2-12 example that input 7 is n and input 8 is ff fr the plarity indicated. Fr the reverse plarity, input 7 is ff and input 8 is n. Nise Prtectin 1. US&S recmmends the use f twisted pair wiring (2-3 turns per ft) fr all input t minimize pssible nise. 2. US&S recmmends the separatin f clean and dirty wiring. Ideally, all inputs are gathered in a bundle, all utputs are gathered in a bundle, and pwer wiring is gathered in a bundle. Each f these bundles is physically separated frm ther huse wiring. It is particularly imprtant t maintain this physical separatin frm high-current dirty wiring. SM 6800B, Rev. 3, December

46 Cardfile and Circuit Bard Installatin 48-pin Cnnectr Pin N. + - Bi-Plar Input Detectin Example: Fr Indicated Plarity, Input 7 ON, Input 8 OFF Fr Reverse Plarity, Input 7 OFF, Input 8 ON SW1 SW2 SW3 SW4 SW5 SW6 Address Select PCB SEL+ GND E32 White E30 Brwn C30 Red A30 Orange E28 Yellw C28 Green A28 Blue A26 Black E2 E4 C2 C4 A2 A4 E6 E8 C6 C8 A6 A8 E12 E14 C12 C14 A12 A14 E16 E18 C16 C18 A16 A18 E22 E24 C22 C24 A22 A24 E26 C T Bard Addressing Circuits Input#1 Input#2 Input#3 Input#4 Input#5 Input#6 Input#7 Input#8 Input#9 Input#10 Input#11 Input#12 Input#13 Input#14 Input#15 Input#16 Vital Input PCB N N Figure Vital Input PCB - Basic Interface Wiring 2-32 SM 6800B, Rev. 3, December 2005

47 2.4.3 Standard Vital Output PCBs Cardfile and Circuit Bard Installatin Each f the standard vital utput PCBs prvides up t 16 utputs. The specificatins fr these bards are as fllws: US&S Part N. Vltage V BATT Range Lad Resistance Range Max. OFF Vltage Min. ON Vltage N V 50 Ω V V BATT - 1V N V 100 Ω - 1.5V V BATT - 1V Outputs are cntrlled by high side sftware-cntrlled switches. Lads shuld be cnnected frm utputs t battery negative. The high side switch is used t cnnect battery (+) t the utput. Each utput is prtected with a plyswitch, which acts like a circuit breaker. When the vercurrent trip pint is reached (apprximately 0.75A), the plyswitch switches t a high impedance. The switch resets t its nrmal lw impedance when the additinal lad r shrt is remved. A shrt t battery (-) will trip the plyswitch and cause the VCOR relay t drp, but will nt cause any damage. A shrt t battery (+) will nt cause any damage, but since this cnditin is equivalent t a false utput, the Micrlk II CPU will cause the VCOR relay t drp. Figure 2-13 shws the suggested wiring cnnectins fr the standard vital utput PCBs. There are multiple cnnecting pints available fr bth the B12 and N12 cnnectins. A single cntact can handle up t 3 amps f lad current. If the anticipated lad current exceeds 3 amps, use additinal cnnecting pints fr the B12 and N12 feeds (ne pint fr each additinal 3 amps) Nise Prtectin Relay Cil Snub Relay snubs are intended t dissipate large electrmagnetic surges frm the cil inductance and t prevent these surges frm interfering with nrmal peratin f the Micrlk system. It is recmmended that all relays being driven by Micrlk be snubbed t prevent unwanted mnitr errrs. This is particularly true where the cil lad t the Micrlk relay driver is being brken by a series cntact. Relay snubs can als be installed n ther relays that are nt directly cntrlled by Micrlk utputs, but may be cntributing t pssible nise due t their clse prximity t the Micrlk wiring. US&S recmmends the use f transrbs (J ) fr relay snubbing. They will have minimal effect n relay timing. Resistrs are als suitable relay snubs. When using a resistr lading f the Micrlk utput an effect n timing (relay drp away) must be cnsidered. Dides can als be used as snubs but: 1. They will definitely increase relay drp time. They may cause cntact burning in sme circuits. SM 6800B, Rev. 3, December

48 Cardfile and Circuit Bard Installatin WARNING D nt use dides r any devices that culd functin as a dide in ac r dc electrified territry; therwise, vltage induced by the device culd cause a relay t remain falsely energized. Twisted Wire US&S recmmends the use f twisted pair wiring (2 t 3 turns per ft) fr all relay lads t minimize pssible nise. This shuld be dne wherever pssible n all I/O wiring. Wire Separatin US&S recmmends the physical separatin f clean and dirty wiring. Ideally, all utputs are gathered in a bundle, inputs are gathered in a bundle, and pwer wiring is gathered in a bundle. Each f these bundles is physically separated frm each ther (6 preferred) and all bundles are physically separated frm ther huse wiring. It is particularly imprtant t maintain this physical separatin frm high-current dirty wiring SM 6800B, Rev. 3, December 2005

49 Cardfile and Circuit Bard Installatin 48-pin Cnnectr Pin N. SW1 SEL+ E32 White E30 Brwn B12 VCOR Relay SW2 SW3 SW4 SW5 SW6 Address Select PCB GND C30 A30 E28 C28 A28 A26 A16 C16 E16 Red Orange Yellw Green Blue Black T Bard Addressing Circuits 24 Vdc Required fr High Vltage Versin f PCB (N ) E2 C2 Output#1 Output#2 - + A2 Output#3 - + E4 Output#4 - + C4 Output#5 - + A4 Output#6 - + E6 Output#7 - + C6 Output#8 - + A6 Output#9 - + E8 Output# C8 Output# A8 Output# E10 Output# C10 Output# A10 Output#15 Output# E12 E22 C22 A22 * N12 * A24, C24, E24, A26, C26, and E26 are als cmmn cnnectin Standard Vital Output PCBs N and N Figure Standard Vital Output PCB - Basic Interface Wiring SM 6800B, Rev. 3, December

50 Cardfile and Circuit Bard Installatin Bi-plar Output PCB The bi-plar utput PCB prvides 12 utputs and is typically used t drive searchlight signal psitining mechanisms. The specificatins fr this bard are as fllws: Vltage V BATT Range 12V Lad Resistance Range 250 Ω - The 12 physical utputs change plarity under the cntrl f 24 paired virtual utputs (VO). Alternate assertin f a virtual pair changes the plarity f the physical utput. Each utput circuit has tw LEDs (ne green and ne yellw) n the bard frnt panel that indicate the n/ff state and the plarity f the utput. If either VO assciated with a bi-plar utput is asserted, the assciated LED, green r yellw, will be illuminated. If neither element f the pair is asserted, the utput is ff and the crrespnding LEDs are bth ff. Example: Physical utput #1 is cnnected t terminals E2 and E4 and is cntrlled by virtual utputs VO1 and VO2. If VO1 is asserted, B12 is ruted t E2, N12 is ruted t E4, and the yellw LED will be illuminated. If VO2 is asserted, B12 is ruted t E4, N12 is ruted t E23, and the green LED will be illuminated. Figure 2-14 shws the relatinships f the remaining virtual utputs, physical utputs, and frnt panel LEDs. Outputs n the nn-vital bi-plar utput PCB are prtected frm shrt circuits and inadvertent cnnectin t either B12 r N12. If bth virtual utputs f a pair are asserted, a warning will be lgged n the CPU bard and the utput will default t an ff state. NOTE These utputs are nn-vital. When used with searchlight mechanisms, vitality is ensured by feedback f the mechanism cntacts t Micrlk II r a vital input. The status f the call is cmpared in the applicatin sftware. If a vital bi-plar utput is required, the islatin mdule shuld be used. (See sectin 3.4 in this manual.) 2-36 SM 6800B, Rev. 3, December 2005

51 Cardfile and Circuit Bard Installatin 48-pin Cnnectr Pin N. B12 VCOR Relay Frnt Panel LEDS Yellw Green SW1 SW2 SW3 SW4 SW5 SW6 Address Select PCB SEL+ GND E32 White E30 Brwn C30 Red A30 Orange E28 Yellw C28 Green A28 Blue A24 Black A22 C22 E22 E2 E4 Out #1 Nn-vital Bi-plar Output PCB N T Bard Addressing Circuits 1 2 Paired Yellw Green 1 ON E2+, E4-2 ON E2-, E4+ C2 C4 Out #2 3 4 Paired Yellw Green 3 ON C2+, C4-4 ON C2-, C4+ A2 A4 Out #3 5 6 Paired Outputs Yellw Green Yellw Green Yellw Green Yellw Green Yellw Green 5 ON A2+, A4-6 ON A2-, A4+ 7 ON E6+, E8-8 ON E6-, E8+ 9 ON C6+, C8-10 ON C6-, C8+ 11 ON A6+, A8-12 ON A6-, A8+ 13 ON E12+, E14-14 ON E12-, E14+ E6 E8 C6 C8 A6 A8 E12 E14 C12 C14 Out #4 Out #5 Out #6 Out #7 Out # Paired Paired Paired Paired Paired Yellw LEDS Green LEDS Nn-vital Bi-plar Output PCB Frnt Panel Yellw Green Yellw Green Yellw Green 15 ON C12+, C14-16 ON C12-, C ON A12+, A14-18 ON A12-, A ON E16+, E18-20 ON E16-, E18+ A12 A14 Out #9 E16 E18 Out #10 C16 C18 Out # Paired Paired Yellw Green 21 ON C16+, C18-22 ON C16-, C18+ N12 23 ON A16+, A18-24 ON A16-, A18+ A16 A18 Out #12 A26 C26 E Paired Paired Figure Nn-vital Bi-plar Output PCB - Basic Interface Wiring and Crrespndence with Frnt Panel LEDs SM 6800B, Rev. 3, December

52 Cardfile and Circuit Bard Installatin Vital Lamp Driver PCB Depending n the lamp pwer ratings, the vital lamp driver PCB can perate up t 8, 12, r 16 signal lamps. The specificatins fr this bard are as fllws: Signal Lamp Vlt. Range Signal Lamp Watt. Range Max. Activated Lad Max. N. f 25W Lamps Max. N. f 18W Lamps Max. N. f 36W Lamps 10V - 12V 16W - 36W 300W Outputs frm this bard are cntrlled by lw side sftware switches, thus lamps must be cnnected frm the utput thrugh a frnt cntact f the VCOR relay t battery (+). A shrt frm an utput t N12 r B12 will nt cause damage, but the system will detect an errr and shut dwn due t the false lighting f a lamp. A variable drpping resistr shuld be installed in the cmmn return fr each signal head t prvide a means f adjusting lamp vltage. This resistr limits current in the event f a shrt circuit utside the huse r case. This arrangement prtects vital lamp driver circuitry frm damage. T accmmdate unusually lng signal lamp leads, battery vltage n the lamp driver PCB can be increased t 18 Vdc. Figure 2-15 shws the typical wiring f the vital lamp driver PCB. Nte in the lwer part f the figure that fr each pair f lamps that can be lit at the same time, ne return t N12 shuld be used. Fr the example shwn in the figure, five lamps can be turned n at the same time, thus three N12 return cnnectins are required SM 6800B, Rev. 3, December 2005

53 Cardfile and Circuit Bard Installatin * B12 Only ne f the lamps sharing a cmmn adjusting resistr can be n at any ne time. VCOR Relay * 48-pin Cnnectr SW1 SW2 SW3 SW4 SW5 SW6 Address Select PCB SEL+ GND E32 E30 C30 A30 E28 C28 A28 E26 E18 E20 E2 C2 White Brwn Red Orange Yellw Green Blue Black BATT+ L.Drive #1 L. Drive #2 Pin N. T Bard Addressing Circuits Sftware Cntrlled Switches E4 C4 E6 C6 L. Drive #3 L. Drive #4 L. Drive #5 L. Drive #6 C10 L. Drive #7 E10 L. Drive #8 B12 VCOR Relay A16 L. Drive #9 A18 L. Drive #10 A20 L. Drive #11 E22 L. Drive #12 C22 L. Drive #13 C24 L. Drive #14 E24 L. Drive #15 NOTE Fr each pair f lamps that can be simultaneusly lit, use ne return t N12. Fr this case, five lamps can be n simultaneusly. Therefre, use three return cnnectins. N12 A24 A2 A4 A6 A8 A10 A12 A14 C8 C12 C14 L. Drive #16 Vital Lamp Driver PCB N Figure Vital Lamp Driver PCB - Basic Interface Wiring SM 6800B, Rev. 3, December

54 Cardfile and Circuit Bard Installatin Mixed Vital I/O Bards The mixed vital I/O bards prvide up t 8 islated inputs and 8 nn-islated utputs. This bard type is used fr smaller applicatins that d nt require full vital input r standard vital utput bards. The specificatins fr the mixed vital I/O bards are as fllws: US&S Part N. Vltage V BATT Range Output Specificatins Lad Resistance Range Max. OFF Vltage Min. ON Vltage N V 50 Ω V V BATT - 1V N V 100 Ω - 1.5V V BATT - 1V N V 100 Ω - 1.5V V BATT - 1V US&S Part N. Nm. Input Vltage Input Specificatins Min. Vltage t Ensure ON State Vltage t Ensure OFF State Max. Sustained Input Vltage N V 9.5V 7.0V r less 34V N V 16.0V 12.0V r less 62V N V 35.0V 15.0V 72V Inputs can be wired in a bi-plar cnfiguratin. Nte in the Figure 2-16 example that input 7 is n and input 8 is ff fr the plarity indicated. Fr the reverse plarity, input 7 is ff and input 8 is n SM 6800B, Rev. 3, December 2005

55 Cardfile and Circuit Bard Installatin Bi-plar Input Detectin Example: Fr Indicated Plarity, Input 7 ON, Input 8 OFF Fr Reverse Plarity, Input 7 OFF, Input 8 ON pin Cnnectr SW1 SW2 SW3 SW4 SW5 SW6 Address Select PCB SEL+ GND E32 E30 C30 A30 E28 C28 A28 A26 E2 E4 C2 C4 A2 A4 E6 E8 C6 C8 A6 A8 E12 E14 C12 C14 * VCOR A24 White Brwn Red Orange Yellw Green Blue Black Pin N. T Bard Addressing Circuits Input#1 Input#2 Input#3 Input#4 Input#5 Input#6 Input#7 Input#8 Mixed Vital I/O PCB N N B12 N C24 E18 C18 A18 E20 C20 A20 E22 C22 E24 E26 Output#1 Output#2 Output#3 Output#4 Output#5 Output#6 Output#7 Output#8 Figure Mixed Vital I/O PCB - Basic Interface Wiring * Nte: Even if yu are using nly inputs n this bard, yu must cnnect B12 t A24 and/r C24. This may r may nt be thrugh the VCOR. SM 6800B, Rev. 3, December

56 Cardfile and Circuit Bard Installatin Nn-Vital I/O PCBs Tw versins f the nn-vital NV.IN32.OUT32, I/O PCBs are available. The LCP versin (N ) is designed fr use with the ptinal Micrlk II Lcal Cntrl Panel (LCP) N This versin f the bard is fitted with a 48-pin cnnectr n the frnt and back. The frnt cnnectr engages the LCP. The remaining I/O (16 inputs and 8 utputs) are available n the rear cnnectr. The ther versin f the NV.IN32.OUT32 bard (N ) cnnects each f it s 32 inputs and utputs t a 96-pin cnnectr munted n the rear f the bard. Bth bards are treated as the same type f bard in the Micrlk II applicatin sftware. Nn-vital, ptically islated I/O PCBs are available as NV.OUT32 (N ), NV.IN32 (N ), and NV.IN32.OUT16 (N ). See Figures 2-19A, B, and C fr basic interface wiring diagrams. The NV.OUT32 PCB prvides 32 islated, utputs fr cntrl f external devices such as indicatrs and relays. The utputs are divided int tw grups f 8 utputs and ne grup f 16 utputs, each grup having a separate bussed cmmn (negative DC) reference utput. Islatin allws switching pwer frm surces islated frm the Micrlk II pwer supply battery. Outputs are designed t perate at battery vltages between 9.5 and 35VDC. Outputs switch psitive battery and are capable f supplying up t.5amps. Nminal vltage drp per utput is lad dependent and usually less than 2.5vlts. The NV.IN32 PCB prvides 32 islated external inputs. The 32 inputs are divided int tw grups f 8 inputs and ne grup f 16 inputs, each grup having a separate bussed cmmn (negative DC) reference input. External input vltages between 6 and 35VDC represent lgical 1. The NV.IN32.OUT16 PCB prvides 16 islated external inputs. These external inputs each have separate (+) and (-) cnnectins and present a lgical 1 when the applied vltage is 6 t 35VDC. This bard als utilizes a Lcal Cntrl Panel (LCP) N X cnnected via a 96-pin cnnectr t the frnt edge f the PCB. The LCP cntrls and mnitrs lcal nn-vital circuits and devices thrugh 16 inputs frm the PCB and 16 utputs frm the LCP t the PCB. Sixteen f the inputs are selectable by the frnt panel LCP pushbuttns. The 16 PCB utputs feed the LED indicatrs n the LCP. Specificatins fr the nn-vital I/O PCBs are as fllws: US&S Part N. Input and Output Vltage Range Nn-Vital I/O Printed Circuit Bards Externally Available Inputs Externally Available Outputs Current Rating On Outputs N t 30.0VDC 16 8 Outputs 25-30: 0.5A fuse Outputs 31, 32: 5.0A fuse* N t 30.0VDC Outputs 1-30: 0.25A (plyswitch-prtected) Outputs 31, 32: 5.0A fuse* N t 35VDC 0 32 Outputs 1-32: 0.5AMPS N t 35VDC 16** 0 N t 35VDC 32 0 N t 16.2VDC 0 12 bi-plar 250Ω min lad utputs *Suitable fr lighting lamp up t 25W. **Other 16 inputs and utputs are used by LCP panel SM 6800B, Rev. 3, December 2005

57 Cardfile and Circuit Bard Installatin Figure 2-18 and Figure 2-7 shw the generic interface wiring fr bth versins f the bard. 48-pin Rear Cnnectr Pin N. Cnnect Lads as Shwn Belw B12 Prtected with 5A Fuses N12 SW1 SW2 SW3 SW4 SW5 SW6 Address Select PCB SEL+ GND E32 White E30 Brwn C30 Red A30 Orange E28 Yellw C28 Green A28 Blue A22 Black A2 A4 A6 A8 A10 A12 A14 A16 C2 C4 C6 C8 C10 C12 C14 C16 E2 E4 E8 E12 E16 E18 E20 E22 A24 A26 C24 C26 E24 E26 Input 17 Input 18 Input 19 Input 20 Input 21 Input 22 Input 23 Input 24 Input 25 Input 26 Input 27 Input 28 Input 29 Input 30 Input 31 Input 32 Output 25 Output 26 Output 27 Output 28 Output 29 Output 30 Output 31 Output 32 T Bard Addressing Circuits Pin N. 48-Pin Frnt Cnnectr Input 1 Input 2 Input 3 Input 4 Input 5 Input 6 Input 7 Input 8 Input 9 Input 10 Input 11 Input 12 Input 13 Input 14 Input 15 Input 16 +5V Nn-Vital +5V I/O PCB +5V N N12 N12 N12 Output 1 Output 2 Output 3 Output 4 Output 5 Output 6 Output 7 Output 8 Output 9 Output 10 Output 11 Output 12 Output 13 Output 14 Output 15 Output 16 Output 17 Output 18 Output 19 Output 20 Output 21 Output 22 Output 23 Output 24 A2 A4 A6 A8 A10 A12 A14 A16 A22 A20 A18 A24 A26 A28 A30 A32 E2 E4 E6 E28 E30 E32 C6 C4 C2 C8 C10 C12 C14 C16 E14 E12 E10 E18 E16 E20 E22 E24 C22 C20 C18 C24 C26 C28 C30 C32 LCP Figure Nn-Vital I/O PCB, LCP Versin - Basic Interface Wiring SM 6800B, Rev. 3, December

58 Cardfile and Circuit Bard Installatin 96-pin Cnnectr SW1 SW2 SW3 SW4 SW5 SW6 Address Select PCB SEL+ GND C32 White C31 Brwn B31 Red A31 Orange C30 Yellw B30 Green A30 Blue B13 Black A1 Input 1 B1 Input 2 C1 Input 3 A2 B2 C2 A3 B3 A4 B4 C4 A5 B5 C5 A6 B6 A7 B7 C7 A8 B8 C8 A9 B9 A10 B10 C10 A11 B11 C11 A12 B12 Input 4 Input 5 Input 6 Input 7 Input 8 Input 9 Input 10 Input 11 Input 12 Input 13 Input 14 Input 15 Input 16 Input 17 Input 18 Input 19 Input 20 Input 21 Input 22 Input 23 Input 24 Input 25 Input 26 Input 27 Input 28 Input 29 Input 30 Input 31 Input 32 T Bard Addressing Circuits B12 Cnnect Lad as Shwn Abve Prtected with 5Amp Fuses N12 This cnnectr cntinued at right Nn-vital Output PCB N Figure Nn-vital I/O PCB, 32/32 Versin - Basic Interface Wiring 2-44 SM 6800B, Rev. 3, December 2005

59 SW1 SW2 SW3 SW4 SW5 SW6 Address Select PCB SEL+ GND 48-pin cnnectr Outputs E2 C2 A2 C4 A4 C6 A6 E8 E4 E6 C8 A8 C10 A10 C12 A12 E14 C14 E10 E12 A14 E16 C16 A16 E18 C18 A18 C20 A20 C22 A22 E24 C24 A24 E26 C26 E20 E22 A32 C32 E32 E30 C30 A30 E28 C28 A28 A26 Output 1 Output 2 Output 3 Output 4 Output 5 Output 6 Outut 7 Output 8 Output Gnd 1-8 Output Battery Output 9 Output 10 Output 11 Output 12 Output 13 Output 14 Output 15 Output 16 Output Gnd 9-16 Output Battery Output 17 Output 18 Output 19 Output 20 Output 21 Output 22 Output 23 Output 24 Output 25 Output 26 Output 27 Output 28 Output 29 Output 30 Output 31 Output 32 Output Gnd Output Battery CONNECTIONS TO PCB ADDRESS SELECT CIRCUITS Cardfile and Circuit Bard Installatin N NV.OUT32 nn-vital islated Output PCB Figure Nn-Vital, Islated NV.OUT32 PCB Basic Interface Wiring SM 6800B, Rev. 3, December

60 Cardfile and Circuit Bard Installatin NOTE In Figure 2-18,, pins A13 C29 are cmmn cnnectr pins. The number f required cmmn returns depends n the number f utputs activated. The general guidelines are:. a. Outputs 31 and 32 are intended fr high current; add a return fr each used. b. Fr each f the ther utputs, add ne return fr every 8 utputs used SM 6800B, Rev. 3, December 2005

61 SW1 SW2 SW3 SW4 SW5 SW6 Address Select PCB SEL+ GND 48-pin cnnectr Inputs E2 C2 A2 C4 A4 C6 A6 E8 E4 C8 A8 C10 A10 C12 A12 E14 C14 E10 A14 E16 C16 A16 E18 C18 A18 C20 A20 C22 A22 E24 C24 A24 E26 C26 E20 E6 E12 E22 A32 C32 E32 E30 C30 A30 E28 C28 A28 A26 Input 1 Input 2 Input 3 Input 4 Input 5 Input 6 Input 7 Input 8 Input Gnd 1-8 Input 9 Input 10 Input 11 Input 12 Input 13 Input 14 Input 15 Input 16 Input Gnd 9-16 Input 17 Input 18 Input 19 Input 20 Input 21 Input 22 Input 23 Input 24 Input 25 Input 26 Input 27 Input 28 Input 29 Input 30 Input 31 Input 32 Input Gnd CONNECTIONS TO PCB ADDRESS SELECT CIRCUITS Cardfile and Circuit Bard Installatin N NV.IN32 nn-vital islated Input PCB Figure Nn-Vital, Islated NV.IN32 PCB Basic Interface Wiring SM 6800B, Rev. 3, December

62 Cardfile and Circuit Bard Installatin SW1 SW2 SW3 SW4 SW5 SW6 Address Select PCB SEL+ GND 48-pin cnnectr Inputs E2 + E4 - C2 + C4 - A2 + A4 - E6 + E8 - C6 + C8 - A6 + A8 - E12 + E14 - C12 + C14 - A12 + A14 - E16 + E18 - C16 + C18 - A16 + A18 - E22 + E24 - C22 + C24 - A22 + A24 - E26 + C26 - E26 C26 E20 E6 E12 E22 A32 C32 E32 E30 C30 A30 E28 C28 A28 A26 Input 1 Input 2 Input 3 Input 4 Input 5 Input 6 Input 7 Input 8 Input 9 Input 10 Input 11 Input 12 Input 13 Input 14 Input 15 Input 16 N NV.IN32. OUT16 nn-vital islated I/O PCB CONNECTIONS TO PCB ADDRESS SELECT CIRCUITS Outputs Output 1 B32 Output 2 B31 Output 3 B30 Output 4 B29 Output 5 B28 Output 6 B27 Output 7 B26 Output 8 B25 Output 9 B24 Output 10 B23 Output 11 B22 Output 12 B21 Output 13 B20 Output 14 B19 Output 15 B18 Output 16 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 + 5V B6 + 5V B5 + 5V B4 GND B3 GND B2 GND B1 Input 17 A32 Input 18 A31 Input 19 A30 Input 20 A29 Input 21 A28 Input 22 A27 Input 23 A26 Input 24 A25 Input 25 A24 Input 26 A23 Input 27 A22 Input 28 A21 Input 29 A20 Input 30 A19 Input 31 A18 Input 32 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 + 5V A6 + 5V A5 + 5V A4 GND A3 GND A2 GND A1 IN 1 LED C32 IN 2 LED C31 IN 3 LED C30 IN 4 LED C29 IN 5 LED C28 IN 6 LED C27 IN 7 LED C26 IN 8 LED C25 IN 9 LED C24 IN 10 LED C23 IN 11 LED C22 IN 12 LED C21 IN 13 LED C20 IN 14 LED C19 IN 15 LED C18 IN 16 LED C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 + 5V C6 + 5V C5 + 5V C4 GND C3 GND C2 GND C1 96-pin cnnectr LCP PANEL N X Figure Cded Track Circuit PCBs Basic Interface Wiring Cde System Interface PCB The cde system interface PCB interfaces the Micrlk II system t varius types f nn-vital cde lines. Basic functins include cnversin f the particular cde line prtcl t a frmat cmpatible with the Micrlk II system (and vice-versa) and peratin as a nn-vital lgic cntrller. This bard is electrically identical t the 2-48 SM 6800B, Rev. 3, December 2005

63 Cardfile and Circuit Bard Installatin enhanced cntrller PCB used in the US&S GENISYS-2000 systems, and uses executive and applicatin sftware that is identical t that used n the enhanced cntrller bard. The GENISYS-2000 hardware is mdified t make the bard mechanically cmpatible with the Micrlk II cardfile. The basic interfacing rules fr the cde system interface PCB are as fllws: A. This bard must be used when interfacing the Micrlk II system t all types f nn-vital cde systems except GENISYS. Either the cde system interface PCB r the Micrlk II CPU bard (refer t sectin 2.4.1) can be used fr the GENISYS interface. B. When interfacing the Micrlk II system t a DC cde line, an external GENISYS unit must be included t prvide the electrical interface t the cde line. The Micrlk II system des nt include an equivalent t the GENISYS cde line interface PCB. C. Micrlk II serial link islatr units shuld be included in the interface t the cde line t prtect circuits n bth ends f the interface frm ptentially damaging vltage transients. These units are different frm the GENISYS surge suppressin/serial interface panels. The latter cannt be used as a substitute. Serial link islatr unit specificatins are as fllws: Unit Type Type A serial link islatr unit Type B serial link islatr unit US&S Part N. N (Cntact US&S) Unit Specificatins Interfaces the cde system PCB (cardfile) t a Glenaire mdem r MCP in ARES and serial line carrier cde systems. Input Pwer: 9.5 t 16.2 Vdc Mdem Pwer Outputs: +12 Vdc and 12 Vdc Interfaces the cde system interface bard t ATCS systems. Signal cmpatibility: Balanced RS-485 and unbalanced RS-423 prts Figure 2-20 shws the standard interface wiring pin-uts fr the cde system interface PCB. SM 6800B, Rev. 3, December

64 Cardfile and Circuit Bard Installatin T Serial r ATCS-cmpliant Cde System via Serial Link Islatr Unit See Sectin 3.5 fr Islatr Unit Installatin See Sectin 3.7 fr Typical Cde System Interface Diagrams 48-pin Cnnectr Pin N. C2 C4 C6 C8 C10 A10 C14 C16 C18 A2 A4 A6 A8 E2 E4 E6 E8 E10 E12 E14 E16 E18 E20 E22 E32 C12 C20 C22 C28 C32 Slave Receive Data - (S1RXD-) Slave Receive Data + (S1RXD+) Slave Receive Clck - (S1RXC-) Slave Receive Clck + (S1RXC+) Slave Transmit Clck - (S1TXC-) Slave Transmit Clck + (S1TXC+) Slave 2 Receive Clck (S2RXC) Slave Data Carrier Detect (S2DCD) Slave Receive Data - (S2RXD-) Slave Clear T Send - (S1CTS-) Slave Clear T Send + (S1CTS+) Slave Data Carrier Detect - (S1DCD-) Slave Data Carrier Detect + (S1DCD+) Slave Transmit Data (S1TXD) Slave Transmit Clck (S1TXC) (Output) Slave Request T Send (S1RTS) Slave Data Terminal Ready (S1DTR) 0 Vlts Slave 2 Cmmn (0 Vlts) Slave Transmit Data (S2TXD) (In / Out) Slave Transmit Clck (S2TXC) Slave Request T Send (S2RTS) Slave Data Terminal Ready (S2DTR) + 5 Vlts 0 Vlts 0 Vlts + 12 Vlts + 5 Vlts - 12 Vlts 0 Vlts A20 A22 A24 A28 A30 A32 A12 A14 A16 A Vlts Master Receive Data (MRXD) Master Data Carrier Detect (MDCD) - 12 Vlts 0 Vlts Master Cmmn - 0 Vlts Slave Cmmn - 0 Vlts (S1COM) Master Transmit Data (MTXD) Master Request T Send (MRTS) Master Data Terminal Ready (MDTR) T dc Cde Lines (US&S 500 Series r GRS K Series) Refer t SM-6700B fr Applicatin Data E24 C24 C26 A26 E26 E28 E30 C30 Parallel Output 1 (POUT1) Parallel Output 2 (POUT2) Parallel Output 3 (POUT3) Parallel Output 4 (POUT4) Parallel Input 1 (PIN1) Parallel Input 2 (PIN2) Parallel Input 3 (PIN3) Parallel Input 4 (PIN4) S1 Slave Prt: RS-423 (RS-422 Cmpatible) S2 Slave Prt: RS-232D Cmpatible Cde System Interface PCB N Figure Cde System Interface PCB - Basic Interface Wiring 2-50 SM 6800B, Rev. 3, December 2005

65 2.4.9 Cded Track Circuit PCBs Cardfile and Circuit Bard Installatin The cded track circuit PCBs interface the Micrlk II system t the mainline cded track circuits (with and withut cab signals). The specificatins fr these bards are as fllws: US&S Part N. Track Circuit Applicatin Track Circuit Operating Pwer N General nn-cab and 100 Hz cab 9.8 t 16.2 Vdc signal N Required fr 40 Hz cab signal 9.8 t 16.2 Vdc N Required fr 50 Hz cab signal 9.8 t 16.2 Vdc N Required fr 60 Hz cab signal 9.8 t 16.2 Vdc The Micrlk II system can accmmdate up t fur cded track circuit printed circuit bards in the same cardfile. Refer t Sectin fr cded track interface panel wiring t the rails. SM 6800B, Rev. 3, December

66 Cardfile and Circuit Bard Installatin 48-pin Cnnectr Pin N. L+ SW1 SW2 SW3 SW4 SW5 SW6 Address Select PCB SEL+ GND E32 E30 C30 A30 E28 C28 A28 A26 A2 White Brwn Red Orange Yellw Green Blue Black T Bard Addressing Circuits A OUT+ Master Side Cded Track Interface Panel (See Fig. 3-2 fr Track Wiring) L- A4 A OUT- L+ A8 B OUT+ Slave Side Cded Track Interface Panel (See Fig. 3-2 fr Track Wiring) L- A10 B OUT- B12 N12 C22 A24 Cded Track Circuit PCBs N N N N A12 Wake-up (Sleep Mde) Figure Cded Track Circuit PCBs - Basic Interface Wiring 2-52 SM 6800B, Rev. 3, December 2005

67 Cardfile and Circuit Bard Installatin OS Track Circuit PCB The OS track circuit PCB interfaces the Micrlk II system t the OS track circuit in interlcking applicatins requiring ne OS transmitter and tw OS receivers (end-f-siding). Specificatins fr this bard are as fllws: Transmitter/Receiver Frequency Receiver Output Vltage 400 Hz 12 Vdc t 20 Vdc 15 Vdc (nminal) Track Circuit Length Ω/1000 ft. Ballast Track Lead Resistance 0.5Ω (max.) It is nt necessary t cnnect bth receivers if it is nt required by the applicatin. In many cases the transmitter is cnnected at the heel blck and the tw receivers prvide independent train detectin n the interlcking thrugh and turnut tracks. Transmitter utput pwer is insufficient t drive a relay. Figure 2-22 shws the basic wiring f the OS track circuit PCB. Outputs OUT1 and OUT2 must be wired t ne f the inputs n the vital input PCB t prvide the train detectin input t the CPU bard. OUT1 and OUT2 shuld each be wired t a + input n the vital input PCB, with N12 cnnected t each negative input. See Figure 2-11 fr vital input PCB wiring pin-uts. Separate B12/N12 and +5V cnnectins are als required t pwer the OS track circuit PCB transmitters and bard circuitry. Als nte the installatin f primary surge prtectin n the wiring. CAUTION Lightning arrestrs (shwn in Figure 2-20) must be used in all Micrlk II OS track installatins, therwise the system culd be damaged frm lightning surges r perate imprperly as the result f transient signals. Refer t service manual SM-6800C fr prcedures t adjust the OS track circuit PCB pwer utput fr varius track circuit lengths. CAUTION The OS track circuit prvides a transmitter and 2 receivers. at an end f siding type lcatin this puts either a transmitter r receiver at each end f the OS circuit. All OS track circuits perate at the same frequency. If multiple OS circuits are used at a duble-crssver type lcatin, a defective jint ptentially culd cause a falsely energized track utput. SM 6800B, Rev. 3, December

68 Cardfile and Circuit Bard Installatin OS Maximum OS Track Lead Resistance = 0.5 Ohms OS OS 1 Line-t-Line Arrester USGA Blue N Line-t-Grund Arrester USGA Red N Pin N. 48-pin Cnnectr A2 Transmit A4 A8 Receive 1 A10 A18 Receive 2 A20 +OUT 1 +OUT 2 OS Track Circuit PCB N A14 A24 A28 A32 A30 DC + Lgic Output* B12 N12 +5V N12 N12 frm Pwer Supply PCB + INPUT X - + INPUT Y - Vital Input PCB N r N (See Fig. 2-7 fr Cmplete Wiring) *Track Occupancy Indicatin t Vital Input PCB Figure OS Track Circuit PCB - Basic Interface Wiring 2-54 SM 6800B, Rev. 3, December 2005

69 Cardfile and Circuit Bard Installatin Cab Signal Cder PCBs and Cab Amplifier PCBs The cder utput and cab amplifier printed circuit bards are used t generate cab signal carrier frequencies and cde rates, and utput these signals t the rails thrugh cab signal interface panels. Each Micrlk II cab signal applicatin requires ne cder utput bard and ne r tw cab amplifier bards installed in the fllwing cmbinatins: Amplifier PCB Cder PCB(s) Applicatin N N Fr 60 r 100 Hz carrier, 75/120/180 cde rates N N , Fr 40 r 50 Hz carrier, 50/75/120/180 cde rates N The cder utput PCB (75/120/180 CPM) is cntrlled by the Micrlk II CPU bard and requires an Address Select PCB with six tw-psitin jumpers in the cnnectr husing t set its cardfile bus address. When the additinal 50 CPM cde rate is required, it is prduced by the bard, which feeds the rate t the cab amplifier bard thrugh the cder utput bard. (A jumper must be set n the bard fr this cnfiguratin; refer t service manual SM-6800C). The cder utput PCB des nt cmmunicate ver the Micrlk II cardfile bus and is nly cnnected t the cder utput bard thrugh the upper wiring cnnectr. Cde rates prduced by the single bard r cmbinatin -5801/-7001 bards are delivered t the cab amplifier PCB thrugh the upper wiring cnnectrs, nt the cardfile bus. The cab amplifier PCB als perates separately frm the CPU bard (n cardfile bus cmmunicatins). The cab amplifier PCB utput is wired t the cab signal interface panel fr final cnnectin t the rails. Figure 2-23 shws the standard wiring ptins fr the fur Micrlk II cab signal bards. Cab amplifier utput cnnectins t cab panel transfrmer primary are dubled t carry the extra current lad. The East and West directin relays n the panel are energized thrugh three additinal wire cnnectins. A jumper is required between pin-uts E14 and E16 n cder utput PCB. This jumper prvides the east/west directin input frm utput #4 n the cder utput PCB. SM 6800B, Rev. 3, December

70 Cardfile and Circuit Bard Installatin Pin N. 48-pin Cnnectr Cab Amplifier PCB N (60/100 Hz) N (40/50 Hz) Cder Output PCB (75/120/180) N Cde Input Cde Output Output 3 Cde Input Output 4 T Bard Address Circuits A10 A8 C10 C8 E2 E4 A2 A4 A14 C14 E14 E10 A18 C18 E18 A16 A22 C22 E22 C20 A26 C26 E26 E24 E32 E20 C6 A6 E6 C24 E2 E12 C22 E14 E16 E32 E30 C30 A30 E28 C28 A28 A26 SEL+ GND SW1 SW2 SW3 SW4 SW5 SW6 Address Select PCB Directin Input +12 East, 0 West B12 N12 22-way Terminal Strip Directin Cntrl Relays East West N See Figure 3-4 fr Cab Signal Panel-t-Track Wiring VCOR Relay B12 AAR Terminals E E W W E1 E2 W1 W2 Cab Signal Interface Panels: Fr 100 Hz Cab: N Fr 60 Hz Cab: N Fr 50 Hz Cab: N Fr 40 Hz Cab: N East Track Feed West Track Feed Grup 1 Grup 2 Cde Turn-On Cde Output Cde Turn-On Cde Output E10 E22 A10 N12 Auxiliary Cder Output PCB (50/50) N Figure Cder Output and Cab Amplifier PCBs - Basic Interface Wiring 2-56 SM 6800B, Rev. 3, December 2005

71 Address Select Jumper Settings Cardfile and Circuit Bard Installatin On the PCBs that use them, the address select jumpers are used fr bard addressing. The jumper settings are autmatically determined by the cmpiler when the applicatin prgram is written. This infrmatin is clearly defined and available t the user in the list file (.mll), which is ne prduct f cmpiling an applicatin text file (.ml2). If this file is unavailable, the user can determine the jumper settings by fllwing the instructins belw. By far the best way t determine the jumper settings, hwever, is t use the list file. The jumper settings fr each bard are determined by the rder in which the bards are defined in the applicatin. The jumper settings d nt depend n the rder the bards happen t appear in the cardfile. If the applicatin prgram and list file are bth unavailable, then the rder can als be fund by lking at the cnfiguratin menu in the Micrlk II Maintenance Tl. (See Sectin 6.2 in the 6800C manual.) The buttns fr the bard listing in the cnfiguratin windw are in the same rder, frm left t right, as they are in the applicatin. There are tw types f bards: 8-bit and 16-bit. Lamp bards are 16-bit bards, and all ther bards are 8-bit bards. S, fr this purpse, there are lamp bards and nn-lamp bards. The fllwing table shws hw t set the jumpers fr each type f bard (lamp and nn-lamp). Each type must be cunted separately t determine the rder and, therefre, the prper jumper setting. Nte: Each jumper may be set t either a "0" r "1" psitin. SM 6800B, Rev. 3, December