Digital Electronics Electronics Technology

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1 Digital Electronics Electronics Technology Landon ohnson hift egisters

2 DIGITAL INTEGATED CICUIT MALL CALE INTEGATION LE THAN 12 GATE MEDIUM CALE INTEGATION 12 TO 99 GATE LAGE CALE INTEGATION 100 TO 9999 GATE GATE FLIP FLOP ENCODE DECODE HIFT EGITE MULTIPLEXE DEMULTIPLEXE ADDE MEMOY MALL MICOPOCEO

3 hift egister Competencies 39. Without references, the student will define the term erial Data Transmission with 100% accuracy. 40. Without references, the student will define the term Parallel Data Transmission with 100% accuracy. 41. Without references, the student will define the acronym IO with 100% accuracy. 42. Without references, the student will define the acronym IPO with 100% accuracy.

4 hift egister Competencies 43. Without references, the student will define the acronym PIO with 100% accuracy. 44. Without references, the student will define the acronym PIPO with 100% accuracy. 45. Given a specified register, the student will draw the register with 100% accuracy 46. Given a specified IO or IPO register, the student will state the number of pulses to completely load the register with 100% accuracy.

5 PAALLEL HIFT EGITE Lab 18. D D D D D D

6 EIAL HIFT EGITE Lab 18. data in clear clk

7 HIFT EGITE VOCABULAY EGITE- group of flip flops capable of storing data. EIAL DATA TANMIION- transfer of data from one place to another one bit at a time. PAALLEL DATA TANMIION- simultaneous transfer of all bits of a data word from one place to another. IO- EIAL IN/EIAL OUT- type of register that can be loaded with data serially and has only one serial output. IPO- EIAL IN/PAALLEL OUT- type of register that can be loaded with data serially and has parallel outputs available. PIO- PAALLEL IN/EIAL OUT- type of register that can be loaded with parallel data and has only one serial output. PIPO- PAALLEL IN/PAALLEL OUT- type of register that can be loaded with parallel data and has parallel outputs available.

8 Lab 27. INTEGATED CICUIT EGITE 74194A BIDIECTIONAL UNIVEAL HIFT EGITE LAB 27 b.eial OPEATION 74L194 D3 D2 1 D1 0 D0 D 3 DL 2 1 M 0 D C B A 1 0 MODE H H PAALLEL LOAD L H HIFT IGHT H L HIFT LEFT L L NO CHANGE

13 OVEVIEW OF HIFT EGITE A shift register is a sequential logic device made up of flip-flops that allows parallel or serial loading and serial or parallel outputs as well as shifting bit by bit. Common tasks of shift registers: erial/parallel data conversion UAT (an example) Time delay ing counter Twisted-ring counter or ohnson counter Memory device

14 CHAACTEITIC OF HIFT EGITE Number of bits (4-bit, 8-bit, etc.) Loading erial Parallel (asynchronous or synchronous) Common modes of operation. Parallel load hift right-serial load hift left-serial load Hold Clear ecirculating or non-recirculating

15 EIAL/PAALLEL DATA CONVEION hift registers can be used to convert from serialto-parallel or the reverse from parallel-to-serial. Parallel out Parallel out erial in erial out erial out Parallel in

16 EIAL LOAD HIFT EGITE Parallel outputs here. Order= A B C D Data = 10 Inputs here: Clock input: (1) Data Positive-edge (2) Clock Clear triggering input: (3) Clear Active = 0 Deactivated = 1 Clock Pulse Clear = bit serial-in parallel out shift right shift register Note the use of D FFs. Clock (CL) inputs wired in parallel. Clear (CL) inputs can be activated with LOW or disabled with HIGH. Preset (P) inputs deactivated.

17 TET UETION #2 #3 #4 #5 #6 #7 UETION #1 What is the 4-bit output (bit A on left, D on right) after pulse 1? 2? 3? 4? 5? 6? This is a type shift register. A. erial-in, parallel out B. Parallel-in, serial-out A: erial-in, A: parallel-out Data = 1 0 Clock Pulse Clear = 1 0

18 PAALLEL LOAD HIFT EGITE Outputs here. Order= A B C D Parallel data inputs (Active LOW) Clock input- H-to-L Clear input- Active LOW ecirculating lines: Pass Note data the from recirculating FFD to FFA on lines. each clock pulse. Note the use of - FFs. Clock (CL) inputs wired in parallel. Clear (CL) input activated with LOW. Parallel load inputs (A,B,C,D) are active LOW.

19 ECICULATING HIFT EGITE Parallel data inputs= only C & all D B inactive activated Clock pulse Clear input= 1 10

20 UNIVEAL HIFT EGITE IC Outputs here Clear input erial data ight active input LOW used during erial Load ight Parallel mode of data operation inputs Order: A, B, C, D during erial data Parallel Left loading input used during erial Load Left mode of operation Clock input Mode L-to-H Controls: triggering Hold Parallel load hift right hift left Universal 4-bit hift egister IC. Modes of operation: Hold, Parallel load, hift right & hift left. An active LOW Clear (CL) input overrides all others.

21 UING THE HIFT EGITE IC CL = erial = 0 X Parallel Load= erial L = X 10 Clock pulse (L-to-H) 0= 1 0 1= 0 1 X = Irrelevant

22 TET UETION #1 #3 #2 #5 #6 #7 UETION #4- What is the mode of operation during and the output of the The What is is the IC mode could of of be operation described during as a 4-bit and the (shift output right, of of universal) the shift register after pulse 3? shift register. after pulse 2? 1? 4? 5? 6? A: A: A: Parallel A: hift Clear, Hold, A: right, left, load, Universal CL = 0 1 erial = 0 X Parallel Load= erial L = X 1 Clock pulse (L-to-H) 0= 1 0 1= 0 1????

23 IMPLE TOUBLEHOOTING HINT Feel top of IC to determine if it is hot Look for broken connections, signs of excessive heat mell for overheating Check power source Trace path of logic through circuit now the normal operation of the circuit

Module-20 Shift Registers

1 Module-20 Shift Registers 1. Introduction 2. Types of shift registers 2.1 Serial In Serial Out (SISO) register 2.2 Serial In Parallel Out (SIPO) register 2.3 Parallel In Parallel Out (PIPO) register