Olivier Sentieys. IRISA/INRIA Cairn team. Power Consumption in Silicon Chips. Chips, logic gates and transistors.

Transcription

1 Olivier entieys II/INI Cairn team University of ennes ower Consumption in ilicon Chips Chips, logic gates and transistors Ci Intel s Xeon Chip i = i.fi.ci.vdd + Ileaki.Vdd = X i i.fi.ci.vdd + Ileaki.Vdd

2 Outline ower and energy consumption basics ower consumption in processors ulticore: power and utilization walls Energy advantages of hardware accelerators laying with accuracy for reducing energy Towards heterogeneous manycores 3D stacking Optical interconnect 3 The asic Element: Transistor Transistor as a switch C G G Vg > Vt: NO on esistance D Vg < Vt: NO off Leakage I off D I off Id Vg Vt: threshold Gate: capacitance C G witch: resistance D D / V dd V t 4

3 Transistors ulk CO ource W Gate channel L tox Drain FD-OI CO Oxyde N/ Diffusion Ticroelectronics Vt tuning gate Thin ilicon Channel Thin ilicon film 5 Transistors Intel FinFET: transistors go 3D 6 3

4 Gates Delay of a gate C i Delay / D.C i / elative FanOut V dd V t Dynamic power dyni = i.f clk.c i.vdd Leakage power stati = N.I o.vdd 7 ctivity ctivity α i is the probability to have a transitions at the output of a gate Example: ND gate = (=) = α i = (- ) ctivity propagation / C X /4 /8 / / /4 α=3/6 8 4

5 ropagating ctivity is not o imple Conditional probabilities / C X /4 /8 / X /4 /4 Glitches: gate delay ignificant in arithmetic Glitches 9 Dynamic ower vs. erformance Decreasing Vdd reduces power but increases delay dyni = i.f clk.c i.vdd elative Delay td elative dyn Delay / V dd V t upply voltage (VDD) 5

6 ower Dissipation and Circuit Delay ower (W) -4 x Delay (s) x Leakage vs. performance High performance Low leakage Id Id I off Vt (low) Vg I off Vt (high) Vg stati = N.I o.vdd Ioff: Delay / V dd V t Exponential in inverse of Vt Exponential in temperature Linear in device count 6

7 inimum Energy per Operation utting all together 3 On-Chip Interconnect? Gate delay decreases but wire delay increases Crossing chip in 5- clock cycles lso affected by noise etal layers to reduce wire delay epeaters [ource: Intel] Towards networkon-chip 4 7

8 Conclusion: ower in CO = X i i.f i.c i.vdd + I leaki.vdd Dynamic power 4-7% today Decreasing relatively DVF becomes more and more difficult Leakage power -5 % today Increasing rapidly number of transistors Vdd/Vt scaling Critical for memory energy = rate + static operation power 5 Outline ower and energy consumption basics ower consumption in processors ulticore: power and utilization walls Energy advantages of hardware accelerators laying with accuracy for reducing energy Towards heterogeneous manycores 3D stacking Optical interconnect 6 8

9 ower Consumption in rocessors typical (yet simple) processor pipeline IF/ID ID/EX EX/E E/W 4 DD u x Zero? ranch taken I 6.. C Instruction memory I I..5 E/W.I egisters u x u x LU Data memory u x 6 3 ign extend 7 Energy Cost in a rocessor D-cache 6% I-cache 3% Fetch/ Decode 9% eg. File 4% Datapath 38% I processor 9 pj/instr. 8 9

10 Energy Cost in a rocessor Fetching operands costs more than computing 64-bit D pj 6 pj 56 pj 6 nj D d/wr 56-bit buses 56-bit access 8 k 5 pj 5 pj Efficient off-chip link nj 8nm CO [Dally, ID ] 9 Energy Cost in a emory L Cache contains 4 illions cells aw/column of cells L-K it line K K+ L- ow decoder Word line torage Cell ense amplifiers-drivers. K K- Column decoder Input-Output ( bits)

11 The Energy Cost of Data ovement Future processor up to 3 Tera-op/sec t minimum requires 64b x 9 Tera-operands to be moved each second If on average mm (% of die size) then.pj/bit x 576 Tbits/s consumes 58 Watts! Delay (ps),, Wire Delay Wire Energy.5.5 pj/it 5 5 On-die interconnect length (mm) educing ower ower gating, multi-vt Clock gating Vdd scaling arallel, pipeline ctivity reduction sleep re-computation, correlation, encoding Glitch ower eduction Vdd witc h Cell Logic Cell Virtual Vdd

12 Dynamic ower anagement Dynamic Voltage and Frequency caling (DVF) educe speed (clock freq.) and Vdd depending on processor activity E=CV H +E idle rocessor peed efore IDLE E=CV L fter Time 3 Outline ower and energy consumption basics ower consumption in processors ulticore: power and utilization walls Energy advantages of hardware accelerators laying with accuracy for reducing energy Towards heterogeneous manycores Can 3D stacking help? Optical interconnect 4

13 The ower Wall ~5 W/cm a hard limit ource: C. atten, Cornell ource: C. atten, Cornell 5 and the ulticore Era Increasing performance by increasing # of cores ource: C. atten, Cornell 6 3

14 hared-emory ultiprocessor L L L L L L L L Interconnect hared L3 Off chip D banks rocessors communicate with shared address space by memory read/write Hardware-managed, implicitly-addressed, coherent caches andwidth depends on Cache size, associativity eplacement policy, coherence protocol pplication requirements 7 I ower 8 cores (T 8) 3 (5) nm, 6.5cm Caches 5 K L / core 96 ed shared L3 Up to 8 ed L4 (offchip) 8 4

15 I ower 8 cross core chip 4 T/sec L W 3 T/sec L3 W 3 G/s sustained external memory bandwidth Core L L G/sec shown assuming 4 GHz Distributed emory eparate address space for each processor rocessors communicate via message passing oftware-managed, explicitly-addressed, local memories ometimes also distributed shared memory 3 5

16 Intel s 8 Core Terascale rocessor 8 cores ( FCs).6 5GHz.V 3 G/s bisection router bandwidth outers write directly into memory: any core could write into the memory of any other core with low latency ( cycles).7mm I/O rea.64mm LL I/O rea single tile.5mm.mm T 3 oving to multicore core@ghz@.v@w core@ghz@.8v@.5w cores@ghz@.8v@.5w ut twice area (and not so simple) GHz W.V GHz.W.8V GHz GHz dvanced technology nodes? 3 6

17 Technology caling Thin ilicon Channel 8 nm nm 4 nm Classical (Dennard s) scaling Device count Device frequency Capacitance, Vdd / Device power / Utilization Core i W@f Core i 5W@.4.f 33 End of Dennard s caling Energy efficiency is not scaling along with integration capacity Leakage limited scaling Device count Device frequency Device power (cap) / Device power (V dd ) ~ Utilization / Core i W@f Core i W@.4.f (w/o) leakage 34 7