Outline. Technology Trends Moore's Law: Process, Feature Size, Scaling Power, Energy

Transcription

1 Technology Trends

2 Outline Technology Trends Moore's Law: Process, Feature Size, Scaling Power, Energy

3 Moore's Law (Technology Scaling) Parameter Value in Current Generation Value in the New Generation Area of the Transistor Supply Voltage (VDD) A A/S2 V V/S Frequency of operation Power consumption f f*s P P/S2 S: S:Scaling Scalingfactor factor(~ 2) (~ 2)

4 Power P total =P dynamic + P static + P leakage Dynamic Power while transistors are switching Static and Leakage Power while transistors are not switching (idle), or off

5 Dynamic Power P dyn =α C V f Activity Factor or Switching factor Number of times the circuit element transitions from 0 to 1 or 1 to 0 during operation. 0 <= α <= 1 Capacitance 2 Load capacitance wires, gate capacitance Supply Voltage (Vdd) Frequency of operation, f = 1 T clock cycle

6 Clock Cycle Clock is a special signal to hardware A well defined indication for event start and complete. Time (ns) Rising Edge Falling edge Clock Levels

7 Clock Cycle Clock is a special signal to hardware A well defined indication for event start and complete. Time (ns) Clock Addition Both operands are ready. ADDITION COMPLETES IN THIS DURATION ANOTHER BLOCK The result is ready. The result is consumed by another block.

8 Clock Cycle Clock is a special signal to hardware A well defined indication for event start and complete. Time (ns) Clock Memory Access Memory access happens here. Address is ready ANOTHER BLOCK Data is ready. The data is consumed

9 Power (Problem) 1.5μ 1.0μ 0.7μ 0.5μ 0.35μ 0.35μ 0.25μ 0.18μ 0.13μ 0.1μ 0.07μ

10 Power (Problem)

11 Reducing Dynamic Power Reduce capacitance (C) P dyn =α C V 2 f Smaller transistors Reduce voltage (Vdd) Quadratic reduction in energy consumption! But also slows transistors Reduce frequency (f) Slower clock frequency (reduces power but not energy) Why? Reduce switching Clock gating

12 Dynamic Frequency Scaling (DFS) Total TotalPower Power== W. W.Leakage Leakage==25%. 25%.Execution Executiontime time==100s. 100s. Original OriginalFrequency Frequency==11GHz. GHz. Scaled ScaledFrequency Frequency== GHz. GHz.Total TotalPower Power==??Execution Executiontime time==?? Energy Energy==?? CPU CPU T1GHz T0.5GHz Memory Memory Program Programis isnot notentirely entirelycpu CPUbound! bound! Decreases Decreasesmemory memorylatency latencyin incycles. cycles. Increases IncreasesIPC. IPC.Execution Executiontime timeis is<<200s. 200s.

13 DVFS Intel IntelXScale: XScale: 11GHz GHz MHz MHzreduces reducesenergy energyused usedby by30x. 30x.5x 5xslower. slower. 55xx MHz MHzin inparallel, parallel,use use1/6th 1/6ththe theenergy energy!! Power Powerhas hasdriven driventhe theindustry industrytowards towardsmulticore. multicore. Total TotalPower Power== W. W.Leakage Leakage==25%. 25%.Execution Executiontime time==100s. 100s.Voltage Voltage==11V. V. New NewVoltage Voltage==0.9V. 0.9V.New NewDelay Delay==??New NewFrequency? Frequency?Power Power==??Energy Energy==??

14 Power and Energy Energy = Power Time Power poses constraints System can only work fast enough to max out the power delivery or cooling solution Energy is the ultimate metric True cost of performing a fixed task Eg. Instructions per Joule, Bits per Joule Processor ProcessorAAconsumes consumes1.2x 1.2xthe thepower powerconsumed consumedby byprocessor ProcessorB. B. Processor ProcessorAAcompletes completesexecution executionin in30% 30%of ofthe thetime timetaken takenby byproc ProcB. B. Which Whichone onewould wouldyou youchoose choosefor foryour yourapplication? application?

15 Power and Energy Metrics Energy (Joules) Power (Watts, Joules per second) Measure of current delivery and voltage regulation on-chip. Power density (Power per Area Watts/cm 2) Measure of battery lifetime (mobile scenarios), operating costs (non-mobile environments) Thermal studies; 200 W/64 cm2 vs. 200 W/4 cm2 Energy-per-Instruction (EPI) Reducing energy at the expense of performance may not be acceptable Improves if one of the factors improve while holding the other constant

16 Metrics Energy-Delay Product (EDP) 1 EDP MIPS 2 /Watt Equal weight for energy and performance degradation Gochman, et. al., The Intel Pentium M Processor: Microarchitecture and Performance, Intel Tech. J., 2003.

17 Summary Effects of scaling Power, Energy, Energy Delay

18 References CS6810 Rajeev Balasubramonian. University of Utah. CIS 501 Milo Martin and Amir Roth. University of Pennsylvania. Kaxiras and Martonosi, Computer Architecture Techniques for Power Efficiency, Synthesis Lectures on Computer Architecture #4, Morgan and Claypool. Weste and Harris. CMOS Digital VLSI. 3e. Pearson-AW. Harris and Harris. Digital Design and Computer Architecture. MK. Hennessy and Patterson. Computer Architecture. 5e. MK.

19 Backup

20 Semiconductors Conductivity of Si changes over many orders of magnitude depending on the concentration of dopants

21 Metal Oxide Semiconductor gate, source, drain, body Gate oxide body stack looks like a capacitor Gate and body are conductors SiO2 (oxide) is a very good insulator

22 nmos and pmos Transistors Source Gate Drain Polysilicon Source Gate Drain SiO2 n+ n+ p p+ n bulk Si nmos nmostransistor Transistor bulk Si g g s p+ d s d pmos pmostransistor Transistor

23 FieldEffectTransistor MOSFET is a voltage-controlled switch Gate voltage creates an electric field that turns ON or OFF a connection between the source and drain.

24 I-V Characteristics of nmos α I ds (V DD V t ) 1<α <2 VDD: Supply Voltage Threshold Voltage (transistor turns ON at Vt) 1 Switching Speed (V DD V t )

25 Channel Length Characteristic of process generation Channel length reduces by a 'scaling factor' every generation Continued miniaturization Improves switching speed, power/transistor, area(cost)/transistor Reduces transistor reliability Transistor density (transistors/cm2) doubles every 18 months n+ 32nm p n+ n+ bulk Si n+ p bulk Si Channel Length (22nm)

26 Working of an nmos Transistor

27 Working of an nmos Transistor

28 Working of an nmos Transistor

29 Ideal I-V Characteristics

30 Ideal I-V Characteristics of nmos

31 Pipeline Stage

32 Wire resistivity Length R Height Width ϵ Length C Pitch Delay wire Length 2 Long wires are getting relatively slow to transistors And relatively longer time to cross relatively larger chips

33 Complementary MOS nmos transistors pass 0 s well but pass 1 s poorly. pmos transistors pass 1 s well but 0 s poorly. Manufacturing processes provide both flavors of transistors are called Complementary MOS or CMOS.

34 Complementary CMOS gates

35 Switching Speed of a Transistor Delay through an electrical component ~ RC L R= A Capacitance (C) ~ length * area / distance-to-other-plate Voltage (VDD) Threshold Voltage (Vt) delay V dd (V DD V t ) Voltage at which a transistor turns on Property of transistor based on fabrication technology Switching time ~ to R C V DD V t 2

36 Reducing Static Power Disable transistors Power gating disable power to unused parts (long latency to power up) Reduce voltage (V) Linear reduction in static energy consumption Slows transistors Dual Vt use a mixture of high and low Vt transistors Use slow, low-leak transistors in SRAM arrays Requires extra fabrication steps (cost) Low-leakage transistors P static V DD e V t T High-K/Metal-Gates in Intel s 45nm process, tri-gate in Intel s 22nm Reducing frequency can hurt energy efficiency due to leakage power

37 Static Power Transistors consume power when idle. Static and Leakage Subthreshold conduction, leakage, tunneling through gate oxide Leakage increases at high temperature Switching Speed vs. Leakage tradeoff Vt, Switching Speed Vt, Leakage exponentially P leakage =V DD I leakage P static=v DD I static

38 Single Processor Performance Move to multi-processor RISC Hennessy & Patterson, CA-QA, 5ed. MK, 2013