Energy Consumption Issues and Power Management Techniques

Transcription

1 Energy Consumption Issues and Power Management Techniques David Macii Embedded Electronics and Computing Systems group

2 The scenario 2

3 The Moore s Law The transistor count in IC doubles on average every 18 months Exponen(al improvement in performance Chip cost reduc(on Courtesy, Computer Measurement Group Exponen(al increment in power consump(on and power- related problems 3

4 Smartphone technology trend: clock rate From Xun Li et al., Smartphone Evolution and Reuse: Establishing a more Sustainable Model, Invited talk at the 39 th International Conference on Parallel Processing Workshops,

5 Smartphone technology trend: memory From Xun Li et al., Smartphone Evolution and Reuse: Establishing a more Sustainable Model, Invited talk at the 39 th International Conference on Parallel Processing Workshops,

6 Power consumption in electronic systems 6

7 Metal-Oxide-Semiconductor technology Structure of an integrated n-channel MOSFET Basic structure Detailed 3D structure CMOS digital circuits rely on complementary devices (i.e. NMOS and PMOS) 7

8 Reasons for power consumption In CMOS technology the power consump(on is due to both dynamic and sta9c contributors: Dynamic (or Ac(ve): currents related to: charging/discharging of logic gates during switching transient short- circuits during switching Sta9c: leakage (sub- threshold) currents in transistors Subthreshold currents Gate tunneling 8

9 Dynamic power consumption - 1 V in V out = Capacitance: Function of wire length, transistor size Supply Voltage: Has been dropping with successive fab generations Switching probability: depends on signal statistics Clock frequency: increases Reducing V DD has a quadra(c effect, but it has a nega(ve impact on performance the delay in switching increases 9

10 Dynamic power consumption - 2 Duration of the rising/falling time of the input signal I peak determined by the saturation current of the P and N transistors (which depend on their sizes, process technology, temperature, etc.) and the ratio between input and output slopes David Macii 10

11 Static power consumption I D sub I DS 0 e ( ) q VGS Vth αkt I gate Subthreshold currents grow about x5 per genera(on. An addi(onal parasi(c consump(on source is the (ny current tunneling the gate oxide. It also grows with temperature. 11

12 Example 12

13 Summary: energy and power equations Voltage scaling limited by threshold scaling increment in I leakage Leakage power, and therefore total power, can be substan(ally reduced by cooling essen(al to keep temperature under control 13

14 Power consumption reduction at the circuit level 14

15 Latency vs. voltage diagram For power reduc(on it is berer to operate at the lowest possible speed, since this allows the highest V dd scaling. When V dd approaches V th T d tends to infinity. Low- threshold MOS devices must be used for the design. 15

16 Voltage scaling vs. performance Operate at reduced voltage at lower speed Use architecture op(miza(on to compensate for slower opera(on e.g. concurrency, pipelining via compiler techniques Architecture borlenecks limit voltage reduc(on degrada(on of speed- up interconnect overheads Similar idea for memory: slower and parallel Trade AREA for lower POWER Courtesy : L. Benini-D. Brunelli 16

17 Example: reference datapath Cri(cal path delay: T adder + T comparator = 25 ns Frequency: f ref = 40 MHz Total switched capacitance = C ref V dd = V ref = 5V Power for reference datapath P ref = C ref V ref2 f ref Courtesy : L. Benini-D. Brunelli 17

18 Parallel architecture The clock rate can be reduced by a factor 2 with the same throughput: f par = f ref /2 = 20 MHz Total switched capacitance C par = 2.15C ref (due to some more rou(ng) V par = V ref /1.7 P par = (2.15C ref )(V ref /1.7) 2 (f ref /2) = 0.36P ref Courtesy : L. Benini-D. Brunelli 18

19 Pipelined architecture f pipe = f ref C pipe = 1.1C ref V pipe = V ref /1.7 Voltage can be reduced while maintaining the original throughput Pipe = C pipe V 2 pipe f pipe = (1.1C ref )(V ref /1.7)2 f ref = 0.37P ref Courtesy : L. Benini-D. Brunelli 19

20 Performance-power tradeoff: summary Datapath Architecture Voltage Area Power Original 5V 1 1 Pipelined 2.9V Parallel 2.9V Pipeline- Parallel 2.0V However, the addi(onal circuitry to compensate speed degrada(on may cause an increment in power consump(on around V th. Courtesy : L. Benini-D. Brunelli 20

21 Beyond voltage scaling Voltage scaling is not the only possible solu(on to reduce power consump(on. Considerable results can be obtained through minimiza(on of the average switching capacitance: Factors influencing C Eff: Circuit opera(on principle Signal transi(on probabili(es Data locality C Eff. = P 0 1 C L 21

22 Power consumption reduction at the system level 22

23 Dynamic Power Management (DPM) Workload System Power Performance Busy/Idle PM commands Power manager (controller) System responds to input (workload) with a performance level and a power consump(on Controller samples B/I and issues PM commands Objec&ve: minimize power for a desired performance Courtesy : L. Benini-D. Brunelli 23

24 Power manager components Monitoring U(liza(on, idle (mes, busy (mes Predic(on Averaging (e.g. EMA), filtering (e.g. LMS) Per- task based (e.g. Ver(go), global u(liza(on (e.g. Grunwald) Control Shutdown, Dynamic Voltage- Frequency Scaling Open- loop, closed loop (e.g. adap(ve control) Update Rule Establish decision points Courtesy : L. Benini-D. Brunelli 24

25 Traditional approach TASK 1 TASK 2 idle (me monitor global u(liza(on monitor per- task u(liza(on monitor update rule idle (me predictor shutdown controller workload predictor DVFS controller Courtesy : L. Benini-D. Brunelli 25

26 Shutdown When a component is idle it can be driven to a low- power state reac(vity power level - clock ga(ng (waked- up by (mer interrupt) - power ga(ng (waked- up by on- chip peripherals) no need for context restore need for context restore - chip power ga(ng (waked- up by external, on board int.) Courtesy : L. Benini-D. Brunelli 26

27 Not just switching off Reduce power according to workloads device states shut down wake up busy idle busy working T sd sleeping T wu working power states T bs T bw T sd : shutdown delay T bs : (me before shutdown T wu : wakeup delay T bw : (me before wakeup Courtesy : L. Benini- D. Brunelli 27

28 Shutdown for energy saving P tr T tr Blocked Off Ac(ve On P tr T tr If T tr =0, P tr =0 then DPM policy is trivial Stop a component when it is not needed If, as is usual, T tr!=0, P tr!=0 shutdown only when idleness is going to be long enough to make it worthwhile Sensible only for components with small duty factors Complex decision if the (me spent in state is not determinis(c Courtesy : L. Benini-D. Brunelli 28

29 Breakeven point Breakeven point: minimum idle (me that makes shutdown profitable. Shutdown worthwhile when T BE < Average T idle =T Off +T tr P Off P tr T tr P On T T BE BE = T = T tr tr + T tr P P tr On P P On Off if if P P tr tr > P P On ON P tr T tr Op&mal shutdown difficult to reach. When to shutdown? Op(mal vs. Idle Time Threshold vs. Predic(ve 29

30 Dynamic Frequency/Voltage Scaling Voltage limited by the most cri(cal (ming constraint Not a problem if latency is not important but, real systems have bursty behavior and latency cri(cal tasks Solu&on: change the supply voltage at run&me! DFVS: adap(ng frequency/voltage to the workload Frequency must be scaled down with voltage while assuring adequate performance and correct behavior Dynamic power grows with the square of V dd and linearly with f Scaling V dd and f by a factor a, power is reduced by a 3 30

31 Example Consider a task with 100 ms deadline, requires 50 ms CPU (me at full speed normal system requires 50 ms computa(on, and 50 ms idle (me half speed/voltage system require 100 ms computa(on, 0 ms idle same number of CPU cycles, but average power decrease by a factor 8 and energy by a factor 4 T1 T2 T1 T2 Speed Task Idle Same work, lower energy Task Time Time Courtesy : L. Benini-D. Brunelli 31

32 DFVS vs. shutdown Energy E min Region of scaling Region of shutdown Use scaling while it reduces the energy If more (me is allowed, scale down to the minimum energy point and subsequently use shutdown t* (me Power allowed (me Execu(on (me Power allowed (me Power allowed (me (me Execu(on (me = t* (me Execu(on (me = t* (me 32

33 Final considerations 33

34 Power consumption breakdown - I Suspended state Idle (fully awake but not ac(ve) From Carroll et al., An analysis of power consumption in a smartphone, Proc.USENIC conference,

35 Power consumption breakdown - Video playback II GSM phone call SMS sending E- mail benchmark From Carroll et al., An analysis of power consumption in a smartphone, Proc.USENIC conference,

36 Smartphone technology trend: batteries From Xun Li et al., Smartphone Evolution and Reuse: Establishing a more Sustainable Model, Invited talk at the 39 th International Conference on Parallel Processing Workshops, David Macii 36

37 Conclusions In spite of a constant improvement and op(miza(on over the years, the power/energy consump(on problem is s(ll cri(cal for Life(me (barery- operated, portable devices) Hea(ng and energy dissipa(on problems (servers) Essen(al to find more efficient barery technologies (micro- fuel cells) and/or to improve energy harves(ng techniques Essen(al to extend power management/reduc(on techniques further at the system level (e.g. for wireless communica(ons) 37

38 Questions? Universal Studios - No, no, no, no, no. This sucker's electrical. But I need a nuclear reaction to generate the 1.21 gigawatts of electricity I need. - Doc, but.what-what the hell is a gigawatt? Dr. Emmett Brown and Marty McFly in Back to the future 38