Lecture 110 Phase Frequency Detectors (6/9/03) Page Types of PLLs. PLL and PLL Measurements. PLL Components

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1 Lecture 110 Phase Frequency Detectors (6/9/03) Page 1101 LECTURE 110 PHASE FREQUENCY DETECTORS (READING: [2], [6]) Introduction The objective of this presentation is examine and characterize phase/frequency detectors at the circuits level. Most of the circuits presented will be compatible with CMOS technology. Organization: Systems Perspective ;;;;; ;;;;; Types of PLLs PLL ;;;;; and PLL Measurements ;;;;; Applications and Examples Circuits Perspective PLL Components Outline Analog Multipliers Digital Detectors Summary Fig Lecture 110 Phase Frequency Detectors (6/9/03) Page 1102 ANALOG MULTIPLIERS Linear Multipliers Modulators vs. Multipliers A modulator is a circuit with multiple inputs where one input can modify or control the signal flow from another input to the output. v 1 (t) v 2 (t) Modulator v out (t) = f A [v 1 (t)] f B [v 2 (t)] where f A and f B are two arbitrary functions of v 1 (t) and v 2 (t), respectively. A multiplier is a modulator where f A and f B are linear functions of v 1 (t) and v 2 (t). (111) v 1 (t) v 2 (t) Multiplier v out (t) = K 1 v 1 (t) v 2 (t) (112)

2 Lecture 110 Phase Frequency Detectors (6/9/03) Page 1103 Applications of Multipliers Nonlinear analog signal processing Mixing Phase difference detection Modulation and demodulation Frequency translation Symbol v α v ß v O Lecture 110 Phase Frequency Detectors (6/9/03) Page 1104 Types of Multiplication v O = v α v β v ß = 2.0 v ß = v ß = 0.5 v O = v α v β v ß = 2.0 v ß = v ß = 0.5 v α v O = v α v β v ß = 2.0 v ß = v ß = 0.5 v ß = 0 v α v α v ß = 0.5 v ß = 2.0 OneQuadrant Multiplier TwoQuadrant Multiplier FourQuadrant Multiplier Scaling: Let K m be a scaling constant such that v O = K m v α v ß. If V max = max v α or max v ß, then K m = 1 V max so that max v O = V max v ß =

3 Lecture 110 Phase Frequency Detectors (6/9/03) Page 1105 Simple BJT 2Quadrant Multiplier The differential amplifier makes a simple multiplier/modulator. Circuit: V CC R C I C1 R C I C2 v out v 1 v 2 Q1 I EE R EE Q2 I C = I C1 I C2 = α F I EE R C tanh If v 1 << 2V t and v 2 < V t, then I C α FI s R C R EE v 1 v 1 2V t 2V t [v 2 V BE (on)] FigMultApp02 v 2 V t and I EE = I s exp v 2 V BE (on) R EE Lecture 110 Phase Frequency Detectors (6/9/03) Page 1106 Basic Principle of Analog Bipolar Multiplier Gilbert Cell Circuit: i C1 i C2 i C3 i C4 Note that v BE1 v BE2 = v BE3 v BE4 Substituting for v BE by, Q1 ß>>1 Q4 v BE1 Q2 Q3 vbe2 vbe3 v BE4 (113) v BE = = V t ln i C Is Gives, i ln C1 I ln i C2 s1 I = ln i C3 s2 I ln i C4 s3 I ln i C1 i C2 s4 I s1 I = ln i C3 i C4 s2 I s3 I s4 If Q1 through Q4 are matched, then I s1 = I s2 = I s3 = I s4, and i C1i C2 I s1 I s2 = i C3i C4 I s3 I s4 i C1 i C2 = i C3 i C4

4 Lecture 110 Phase Frequency Detectors (6/9/03) Page 1107 Gilbert Multiplier Cell Problems with a simple modulator are: 2quadrant, v 2 > 0 Small signal, v 1 < 2V t 50mV Solution Gilbert Cell: i C1 i C1 i C3 = 1 exp(v 1 /V t ), i C4 = 1 exp(v 1 /V t ) i C2 i C5 = 1 exp v 1 /V, i C6 = t 1 exp v 1 /V, t I EE i C1 = 1 exp v 2 /V t and i C2 = 1 exp v 2 /V t Let i C = i L1 i L2 = (i C3 i C5 ) (i C4 i C6 ), therefore I EE i C2 I EE i C3 = [1exp(v 1 /V t )][1exp(v 2 /V t )], i C4 = [1exp(v 1 /V t )][1exp(v 2 /V t )] I EE i C5 = [1exp(v 1 /V t )][1exp(v 2 /V t )], i I EE C6 = [1exp(v 1 /V t )][1exp(v 2 /V t )] Writing i C as i C = (i C3 i C6 ) (i C5 i C4 ) gives 1 i C = I EE 1exp(v 1 /V t ) 1 1exp(v 1 /V t ) 1 1exp(v 2 /V t ) 1 1exp(v 2 /V t ) 1 1 e Note that: 1e x 1e x = x/2 e e x/2 e x/2 x/2 e x/2 e x/2 = ex/2 e x/2 e x/2 e x/2 = tanh(x/2) v 1 v 2 Q3 i L1 i C3 i C4 Q1 I EE Q4 i C1 Q5 i L2 i C5 i C6 i C2 I EE Q4 Q6 V EE (117) Lecture 110 Phase Frequency Detectors (6/9/03) Page 1108 Gilbert Multiplier Cell Continued i C = I EE tanh(v 1 /2V t ) tanh(v 2 /2V t ) which solves the twoquadrant problem. Assume that, v OUT = R(i L1 i L2 ) = R i C = RI EE tanh(v 1 /2V t )tanh(v 2 /2V t ) Synchronous Modulator: v 1 << 2V t and v 2 >> 2V t v OUT RI EE sgn[v 2 (t)]tanh(v 1 /2V t ) Waveforms: sgn[v 2 (t)] 0 v 1 (t)/2v t 0 t v o (t) Problem: v 1 < 2V t and v 2 < 2V t 0 t Fig. 118 t

5 Lecture 110 Phase Frequency Detectors (6/9/03) Page 1109 Using Voltages for the Gilbert Cell Voltage Equivalent: i Ci vin/r i Ci v in R R v out = i Ci R Input Circuit Output Circuit (114) Therefore the previous results can be converted to, v in v 2 = v 3 v 4 Let v 4 be an output, then v 4 = v out = v inv 2 v 3 Lecture 110 Phase Frequency Detectors (6/9/03) Page Four Quadrant Linear Multiplier Circuit: V CC Predistortion Circuit Currenttovoltage converter K o i L1 i L2 v OUT Q7 Q8 i 3 i 4 i i5 6 Q3 Q4 Q5 Q6 i 7 i 8 i 9 i 10 i 1 i 2 Q9 K1 K Q10 Q1 2 Q2 R EE R EE R EE R EE v 1 v 2 I XX I YY VEE The predistortion circuit forms tanh1 x type shaping prior to the tanh x shaping of the following stage. V EE

6 Lecture 110 Phase Frequency Detectors (6/9/03) Page Four Quadrant Linear Multiplier Continued Analysis Note that, v BE3 v BE4 v BE5 v BE6 = 0 V T ln I s3 V T ln I s4 V T ln I s5 V T ln I s6 = 0 Assuming matched transistors gives i 3 i 5 = i 4 i 6, i 9 i 3 = i 4 i 10 and i 9 i 6 = i 5 i 10 Also note that, i 1 = i 3 i 4, i 2 = i 5 i 6, i L1 = i 3 i 5, i L2 = i 4 i 6, and I XX = i 9 i 10 Assume that i 9 i 10 = v 1 K 1, i 1 i 2 = v 2 K 2, and v OUT = K o (i L1 i L2 ) where K 1 = K 2 2R EE Now, i 10 i 10 i 10 i 10 v OUT = K o (i 4 i 6 )(i 3 i 5 )=K o i 4 i 5 i 9 (i 4 i 9 i 5 )=K o i 4 i 4 i 9 i 5 i 5 i 9 =K o (i 4 i 5 ) 1 i 10 i 9 i 10 i 9 = K o i 9 (i 4 i 5 ) Next, find i 4 i 5 in terms of i 1 i 2 as follows. i 10 i 10 i 9 i 10 i 1 i 2 = (i 3 i 4 ) (i 5 i 6 ) = i 4 i 9 i 4 i 5 i 5 i 9 = i 9 (i 4 i 5 ) Therefore, i 4 i 5 = Substituting gives i 9 i 10 i 9 v OUT = K o i 9 i 9 i 3 i 4 i 9 i 10 (i 1 i 2 ) which is the desired result. i 9 i 10 (i 1 i 2 ) = K (i 9 i 10 )(i 1 i 2 ) o i 9 I 10 = K o I x (I 9 i 10 )(i 1 i 2 ) vout= Ko IXXK1K2 v 1 v2 = Km v1 v2 i 5 i 6 Lecture 110 Phase Frequency Detectors (6/9/03) Page Gilbert Cell CMOS Multiplier As we have seen, the classical Gilbert Cell mixer may be implemented in a singlebalanced or doublybalanced configuration. R L v out R L v 1 v 2 R L v out M1 M2 M3 R L v 1 v 2 M5 M3 M1 M4 M2 M6 SingleBalanced Multiplier DoubleBalanced Multiplier Fig As with the BJT multipliers, one input, v 1, is large enough that it cause the differential input transistor to act as a current steering switch. As a consequence, these mixers are really modulators. The gain of the multipliers is g m R L. A problem with the doublebalanced multiplier is that it uses three stacked transistors.

7 Lecture 110 Phase Frequency Detectors (6/9/03) Page V, HighFrequency CMOS Multiplier Based on the Gilbert cell with two sourcefollowers as current modulators. V 1 ML1 ML2 i L1 V out i L2 i 5 i 1 i 4 i 6 i 2 i 3 M5 M1 V 2 M2 M3 M4V 2 M6 V 2 I B I B Comparison with the Gilbert cell: Can operate at a lower supply voltage because the mixer does not use stacking Source followers give better linearity Has a smaller mixer gain because sharing the bias currents with the followers reduces g m KK Kan, D. Ma, KC Mak and H.C. Luong, Design Theory and Performance of a 1GHz CMOS Downconversion and Upconversion Mixers, Analog Integrated Circuit and Signal Processing, Vol. 24, No. 2, pp , July Lecture 110 Phase Frequency Detectors (6/9/03) Page How Does the Previous Multiplier Work? The oscillator input is sufficiently large that M1M4 are fully switched on or off. Therefore, the multiplier is redrawn as shown and consists of two pairs of unbalanced source coupled MOSFETs. v The differential drain current of an in unbalanced sourcecoupled pair is i D = i L1 i L2 = I DC i SQ i non where I DC = (W 1/L 1 )(W 5 /L 5 ) (W 1 /L 1 )(W 5 /L 5 ) I B which is the current due to the asymmetry of the unbalanced sourcecoupled pair. i SQ = (W 1/L 1 )(W 5 /L 5 )[(W 5 /L 5 )(W 1 /L 1 )]K n [(W 1 /L 1 )(W 5 /L 5 )] 2 V i 2 which is a current proportional to the square of the differential input voltage, V i =V G1 V G5 and where V G is the gate voltage from the inherent square law model i non = 2(W 1/L 1 )(W 5 /L 5 )K n V i [( W 1 /L 1 )( W 5 /L 5 )] 2 [(W 1 /L 1 ) (W 5 /L 5 )] 2I B K n (W 1/L 1 ) (W 5 /L 5 )V i 2 which is the portion of current that causes harmonic distortion. v out ML1 i L1 I B M5 M1 M4 M6 I B ML2 i L2 i 5 i 1 i 4 i 6 Fig

8 Lecture 110 Phase Frequency Detectors (6/9/03) Page Frequency Response of the Previous Multiplier There are four poles and one zero. Dominant pole: 1 p 1 = R o C o where R o is the output resistance at V IF (v out ). Second pole: p 2 = g m1g mbs1 g m5 g mbs5 g o5 g o7 C x C gs1 C gs5 where g o7 is the output conductance of I B and C x is the capacitance contributed by the biasing transistor as well as the cutoff transistor. The other two poles and zero are higher in magnitude and can be neglected. Frequency response: Output Signal (dbm) v in ML1 I B Frequency response at the commonsource nodes with LO frequency at zero v out M5 M1 M4 M6 X I B ML2 Y Conversion gain of the mixer Fig Frequency (MHz) Lecture 110 Phase Frequency Detectors (6/9/03) Page A QuarterSquare CMOS Multiplier QuarterSquare Principle: v O = k 4 [(v 1v 2 ) 2 (v 1 v 2 ) 2 ] = k 4 [v 1 2 2v 1 v 2 v 2 2 v 1 2 2v 1 v 2 v 2 2] = kv 1 v 2 Differential Summer Circuit: M7 M8 (W/L) 2 (W/L)2 M5 M6 (W/L) 2 (W/L) 2 v OS M1 M2 (W/L) 1 (W/L) 1 v 1 M3 M4 (W/L) 1 (W/L) 1 v 2 I B2 I B1 V SS MPLL06 v OS = v GS8 v GS6 v GS5 v GS7 v OS = v GS5 v GS7 v GS6 v GS8 But, v ON5 = v ON6 = (W/L) 1 (W/L) 2 v ON1, v ON7 = (W/L) 1 (W/L) 2 v ON2 and v ON8 = (W/L) 1 (W/L) 2 v ON3, (W/L) 1 (W/L) 2 v ON4 (W/L) 1 v OS = (W/L) 2 [(v GS1 v GS2 ) (v GS3 v GS4 )] (W/L) 1 v OS = (W/L) 2 (v 1 v 2 ) J.S. PeñaFinol and J.A. Connelly, A MOS FourQuadrant Analog Multiplier Using the QuarterSquare Technique, J. of SolidState Circuits, vol. SC22, No. 6, pp , Dec

9 Lecture 110 Phase Frequency Detectors (6/9/03) Page QuarterSquare Multiplier Continued Dual Differential Squaring Circuit: v OSq = R L i 2 R L i 1 = R L [(i 19 i 20 ) (i 9 i 10 )] i 9 i 10 = K p W 2 K p W 2 W L 3 [(V GS 0.5v OS1 V T ) 2 ] L 3 (V GS0.5v OS1 V T ) 2 ] = K p L 3 [(V GSV T ) v OS1 2] W Similarly, i 19 i 20 = K p L 3 [(V GSV T ) v OS2 2] W W v OSq = R L K p L 3 [(V GS V T ) v OS1 2 (V GS V T ) v OS2 2] = R L K p L 3 [0.25(v OS1 2 v OS2 2) which is valid as long as v i <<V ic where V ic is associated with the value of ±v i when one of the transistors leaves the saturation region. v OS1 V SS i 1 R L R L i 2 v OSq M9 M10 M19 M20 (W/L)3 R p (W/L)3 v OS2 MPLL07 Lecture 110 Phase Frequency Detectors (6/9/03) Page QuarterSquare Multiplier Continued Complete Circuit: v 1 M7 M8 (W/L) 2 (W/L)2 M5 M6 (W/L) 2 M9 (W/L) 3 M10 M1 M2 (W/L) 1 M17 M18 R L R (W/L) 2 L M15 M16 (W/L) 2 v O M19 (W/L) 3 M20 M11 M12 M31 M32 (W/L) 31 v 2 M3 (W/L) 1 (W/L) 1 M4 M13 M14 M29 M30 (W/L) 29 V Bias I B2 (W/L) 4 IB1 M24 M25 R p V SS M22 M21 M33 (W/L) 33 MPLL08 v O = K R L (W/L) 3 (W/L) 1 (W/L) 2 v 1 v 2 = K R L S 3 S 1 S 2 v 1 v 2 where S i = W i L i

10 Lecture 110 Phase Frequency Detectors (6/9/03) Page FourQuadrant CMOS Multiplier Small Signal Analysis: i out = i 7 i 8 = (i 3 i 5 )(i 4 i 6 ) = (i 3 i 4 )(i 6 i 5 ) where i 3 = g m34v x 2, i 4 = g m34v x 2, i 6 = g m56v x 2, and i 5 = g m56v x 2 i out = g m34 v x g m56 v x V = 2K N S N I 34 2K N S N I 56 v SS x However, I 34 = I SS (0.5I DD i 1 ) and I 56 = I SS (0.5I DD i 2 ) If I DD = I SS and i 1 < I SS and i 2 < I SS, then I 34 = 0.5I SS i 1 and I 56 = 0.5I SS i 2 i out = 2K N S N i out = = K N S N I SS K N S N I SS i 1 i 2 v x = I 34 I 56 v x = 2K N S N 0.5I SS i 1 0.5I SS i 2 v x 1 (2i 1 /I SS ) 1 (2i 2 /I SS ) v x K N S N I SS [(i 1 /I SS ) (i 2 /I SS )]v x g m12 v y K N S N I SS 2 g m12v y 2 v x = v Y M1 M2 M3 M4 M5 M6 v X i 1 i 2 FigMultApp08 I DD K N S N I SS i 7 I SS V SS I SS g m12 v y v x = 2K N S N K P S P v x v y i8 Babanezhad and Temes JSSC, Dec Lecture 110 Phase Frequency Detectors (6/9/03) Page CMOS FourQuadrant Multiplier Complete circuit: R 1 i 7 i 8 v OUT R 2 v Y M1 M2 M3 M4 M5 M6 M7 M8 M9 v X M10 v cx M11 M12 v CX is a voltage used to establish the common mode in the multiplier. FigMultApp09

11 Lecture 110 Phase Frequency Detectors (6/9/03) Page CMOS Four Quadrant Multiplier Uses FETs in the triode region to achieve a linear fourquadrant multiplier. Ideal Operation (Op Amp Gain = and v i = 0): i 1 = K V GS v y 2 V v x T 2 1 v 2 x 2 2 i 2 = K V GS v y v x 2 V T v x 2 2 i 3 = K V GS v y 2 V v x T v x 2 2 i 4 = K V GS v y 2 V v x T 2 1 v 2 x 2 2 v x v y v o = R(v o v o ) = RK (i 4 i 3 i 1 i 2 ) = RK 2 v xv y 2 = RK v xv y v x =V LO v x = V LO M4 M1 M2 v y vy =V RF = V RF M3 i 1 R f i 2 v i i 3 v i i 4 R f v o v o Fig v o = RK v LO v RF = G T v LO v RF where the gain, G T = RK Lecture 110 Phase Frequency Detectors (6/9/03) Page CMOS FourQuadrant Multiplier Performance 150uA 100uA 50uA I(VSENSE) 0 50uA 100uA 150uA VBC =5V V3 =0V VC1 =7V VC2 =6V 5V 4V 3V 2V V 1 V 2 SPICE Input File: Double MOSFET Differential Resistor Realization M MNMOS1 W=3U L=3U M MNMOS1 W=3U L=3U M MNMOS1 W=3U L=3U M MNMOS1 W=3U L=3U VSENSE 3 8 DC 0 VC1 2 0 DC 7V VC2 5 0 VSS 4 0 DC 5V V MODEL MNMOS1 NMOS VTO=0.75 KP=25U LAMBDA=0.01 GAMMA=0.8 PHI=0.6.DC V VC PRINT DC I(VSENSE)).PROBE.END Comments: Good linearity and tunability. Frequency range limited by the op amp

12 Lecture 110 Phase Frequency Detectors (6/9/03) Page CMOS Four Quadrant Multiplier Continued Previous circuit with a finite op amp gain (A): v o = v o v o = A (v i v i ) v i = v o 2A and v i = v o 2A i 1 = K V GS v y 2 v o 2A V v x T 2 v o 2A 1 v 2 x 2 v o 2A 2 i 2 = K V GS v y 2 v o 2A V T v x 2 v o 2A 1 v 2 x 2 v o 2A 2 i 3 = K V GS v y 2 v o 2A V v x T 2 v o 2A 1 v 2 x 2 v o 2A 2 i 4 = K V GS v y 2 v o 2A V T v x 2 v o 2A 1 2 v x 2 v o 2A 2 R v o = 1 1 (i 4 i 3 i 1 i 2 ) = RK v A 1 1 x v y A 2 V Tv o A V GSv o A v xv y 2 V GSv o A V Tv o A v o 1 1 2RK G T A A (V v GS V T ) = RK v x v o = y 1 1 A 2G v T x v y A (V GS V T ) Lecture 110 Phase Frequency Detectors (6/9/03) Page CMOS Four Quadrant Multiplier Continued Previous circuit with a finite op amp gain (A) and a threshold variation ( V T and V T ): i 1 = K V GS v y 2 v o 2A V v x T V T 2 v o 2A 1 2 v x 2 v o 2A 2 i 2 = K V GS v y 2 v o 2A V T V T v x 2 v o 2A 1 2 v x 2 v o 2A 2 i 3 = K V GS v y 2 v o 2A V v T V x T 2 v o 2A 1 2 v x 2 v o 2A 2 i 4 = K V GS v y 2 v o 2A V T V T v x 2 v o 2A 1 2 v x 2 v o 2A 2 R v o = 1 (1/A) (i 4 i 3 i 1 i 2 ) RK = 1 (1/A) v x v y 2 V T v o A V Tv o A v o 2 2A2 V GSv o A v xv y 2 V T v o A V Tv o A v o 2 2A2 V GSv o A G T v o = 1 (1/A) v x v y 2v o A (V GS V T ) v o A ( V T V T ) G T v o = 1 1 A 1 2G T 1 A (V GS V T ) G v T x v y 1 A ( V T V T )

13 Lecture 110 Phase Frequency Detectors (6/9/03) Page CMOS Multiplier 4 FET Switch Plus Inverter Circuit: VI converter based on CMOS inverter LO commutates fourfet switch to mix with the RF current LOI Linearity limited by VI converter RF Noise set by VI converter LOI Performance: Implemented for a 900 MHz RF, 100 MHz IF superheterodyne receiver Image noise suppression filter is required between the LNA and mixer to satisfy the matched input impedance requirement at the mixer. Specification Value Conversion Gain 9 db DSB Noise Figure 6.7 db IIP3 4 dbm LO level 0 dbm Current Drain 2.6 ma at 2.7V Technology 0.5 µm CMOS LOI LOI Fig Lecture 110 Phase Frequency Detectors (6/9/03) Page Passive Mixer Example A simple, doubly balanced passive CMOS downconversion mixer is shown along with the local oscillator waveform, v OL (t). Assume that v RF (t) = A RF cos(ω RF t) and is shown below. (a.) Find the conversion gain, G c, in db if the switches are ideal. (b.) Find the conversion gain in db if the switches have an ON resistance of R s /2. Solution Assume the switches have an ON resistance of R ON and work both parts (a) and (b) simultaneously. Also, The equation for v IF (t) can be written as, v IF (t) = R s v RF (t) R s2 R s2 v IF (t) 2R s 2R v ON RF (t) sgn[] R V IF (jω) = s 4 2R s 2R ON A RF cos(ω RF t) πcos(ω LO t) 4 3π cos (3ω LOt) R V IF (jω) s 4A RF R 2R s 2R ON π cos(ω RF t) cos(ω LO t) = s 2A RF 2R s 2R ON R s Switch ON Switch OFF 0 t 1 f LO F99E2P1 π cos[ω RF ω LO )t]

14 Lecture 110 Phase Frequency Detectors (6/9/03) Page Passive Mixer Example Continued The conversion gain in general is written as R s G c = V IF V RF = 2 2R s 2R ON π v RF (t) R s2 R s2 v IF (t) R s Switch ON Switch OFF 0 t 1 f LO F99E2P1 (a.) For R ON = 0, G c = 1 π G c = 1 π = 9.943dB (b.) For R ON = 0.5R s, G c = 2 3π G c = 2 3π = dB Lecture 110 Phase Frequency Detectors (6/9/03) Page A 1.8V, 1.9GHz CMOS Multiplier This mixer uses a stacked Gilbert cell as shown. Performance for RF = 1.9GHz and IF = 250MHz: R L1 R L2 Supply Voltage 1.8V LO Power 8dBm 8dBm 8dBm (1.65GHz) SSB NF (50Ω) 10.2dB 9.4dB 8.2dB Conversion Gain 0.5dB 2.4dB 6.5dB IIP3 6dBm 5.5dBm 3dBm Input 1dB Compression 15dBm 14.5dBm 12dBm Total Current 4.8mA 5.8mA 13.1mA V IF I B M7 i L1 il2 M8 i 1 i 4 i 2 i 3 M1 V LO M2 M3 M4V LO V RF M5 i 5 V LO i 6 M6 I B V RF I B V IF P.J. Sullivan, B.A. Xavier and W.H. Ku, Low Voltage Performance of a Microwave CMOS Gilbert Cell Mixer, IEEE J. of SolidState Circuits, Vol. 32, No. 7, July 1997, pp

15 Lecture 110 Phase Frequency Detectors (6/9/03) Page DIGITAL DETECTORS Conventional Phase Frequency Detector External Reference Down v d Dead Zone θ e VCO Up Fig The primary problem with the conventional PFD is the dead zone which causes phase jitter. N. H. E. Weste and K. Eshragrian, Principles of CMOS VLSI Design, 2 nd. ed., Reading, MA, Addison Wesley, Lecture 110 Phase Frequency Detectors (6/9/03) Page Delay in the Conventional PFD The PFD is an asynchronous state machine. The circuit speed depends on the delay time necessary to reset all internal nodes. The critical path is shown below in bold and consists of 6 gate delays. External Reference Down VCO 1 Fig Ending Point of Feedback Path Up 6 Starting Point of the Feedback Path

16 Lecture 110 Phase Frequency Detectors (6/9/03) Page Precharge PFD The critical path has a delay of only three gates reducing the dead zone and resulting phase jitter. Up External Reference Set 1 Starting point of feedback loop VDD Down VCO Output 2 3 Ending point of feedback loop Fig S. Kim, et. al., A 960Mb/s/pin Interface for SkewTolerant Bus Using Low Jitter PLL, IEEE J. of SolidState Circuits, Vol. 32, No. 5, may 1997, pp Lecture 110 Phase Frequency Detectors (6/9/03) Page Modified Precharge PFD Circuit: Up Up External Reference External Reference VCO Output Down VCO Output Down 0 Phase Offset 180 phase offset Fig The two delays inserted at the external reference and the VCO output remove the dead zone in the phase characteristic around the equilibrium point of the phase detector. H. O. Johansson, A Simple Precharged CMOS Phase Fequency Detector, IEEE J. of SolidState Circuits, Vol. 33, No. 2, Feb. 1998, pp

17 Lecture 110 Phase Frequency Detectors (6/9/03) Page Comparison of Various PFD s = 3V and f o = 50MHz Phase Sensitivity Precharge PFD Modified Precharge PFD Conventional PFD 1.5 2π π 0 π 2π Phase Phase Sensitivity Precharge PFD 0.5 Modified Precharge PFD Conventional PFD 0 Phase (ns) Fig A The duty cycle of the input will influence the deadzone of the PFD including the modified PFD. For example, a duty cycle of 5% at 50 MHz gives a phase offset of 0.063π or 630ps. Lecture 110 Phase Frequency Detectors (6/9/03) Page Frequency Response of Various PFDs The maximum operation frequency is defined as the frequency where the size of the dead zone starts to deviate significantly from the lowfrequency value. Deadzone width (ps) Conventional PFD Modified Precharge PFD 200 Precharge PFD Frequency (MHz) Maximum Frequency (MHz) Modified Precharge PFD Conventional PFD Precharge PFD Supply Voltage Fig

18 Lecture 110 Phase Frequency Detectors (6/9/03) Page SUMMARY Analog Multipliers: 1, 2, and 4quadrant Modulator output voltage is the product of arbitrary functions of the inputs Multiplier output voltage is a linear product of the inputs BJT multipliers Gilbert Cell MOS multipliers quartersquare principle, translinear principle The linearity of the multipliers can be increased by various methods. Digital Detectors: The EXOR and JK phase detectors are reasonably simple and straightforward The primary objective of the phase frequency detector is to eliminate the dead zone Techniques for reducing the dead zone Precharge PFD Modified Precharge PFD