Traveling the Wild Frontiers of Ultra-Low Voltage Design

Transcription

1 Traveling the Wild Frontiers of Ultra-Low Voltage Design Jan M. Rabaey Director Gigascale Silicon Research Center Co-Director Berkeley Wireless Research Center University of California at Berkeley PATMOS, September 05, Leuven

2 Why Ultra-Low Voltage? Power and Energy Limiting Integration and Scaling Exploring the Bounds and Frontiers of Computation The Brave New World of Ubiquitous Electronics Meso-scale low-cost wireless transceivers for ubiquitous wireless data acquisition that are fully integrated Size Size smaller than than 1 cm cm 3 3 are dirt cheap ( the Dutch treat ) At At or or below 1$ 1$ minimize power/energy dissipation Limiting power dissipation to to µw µw enables energy scavenging and form self-configuring, robust, ad-hoc networks containing 100 s to to 1000 s of of nodes 2

3 Why Worry about Ultra-Low Voltage? Maximum integration density ultimately limited by energy dissipated per unit volume. Technology scaling leads to linear increase in energy density (for same switching activity and voltage) Only options: Reduce computational density lowering frequency and/or activity 3 Reduce supply voltage

4 Power and Energy Limiting Integration The Picture of Old Power density : p [W/cm 2 ] κ 3 MPU DSP κ Scaling variable: κ p = p DYNAMIC + p LEAK Constant V scaling p DYNAMIC κ 3 V scaled as κ 1 I DS (V GS -V TH ) 1.3 p DYNAMIC κ Design rule [µm] 0.1 (Sakurai, 2003)

5 Power and Energy Limiting Integration The Roadmap Perspective 1000 Leakage power density: k Compute density: k 3 10 Active power density: k ITRS Low operating power scenario

6 The Reality May Be Worse! 1 st st Mega Trend: Slowing V CC / CC / Growing Power Technology Technology Voltage Voltage (V) (V) Technology Technology Supply Supply Voltage Voltage.7X Voltage.7X Voltage Scaling Scaling Voltage Voltage Scaling slowing Scaling slowing after P1262 after P Voltage Voltage scaling scaling is is slowing slowing // stopping ~1.0V ~1.0V Scott Thompson, TI Fellows meeting

7 Power and Energy Limiting Integration Better Option: Slow down or reverse compute density increase Use slack to control power (that is, voltage) and leakage 100 Compute density: k 2 Leakage power density: <k Active power density: <k

8 There is Room: Minimum Operational Voltage of Inverter Swanson, Meindl (April 1972) Further extended in Meindl (Oct 2000) Limitation: gain at midpoint > -1 Cfs: fast surface state capacitance Cox: gate capacitance Cd: diffusion capacitance For ideal MOSFET (60 mv/decade slope): 8

9 Gain is the Limiting Factor Voltages normalized to U T = kt/q 9 From E. Vittoz, Ch. 16, Low Power Electronics, Ed. C. Piguet, 2005.

10 Confirmed for Current Technologies Min Vdd (inverter) Degradation due to asymmetry mv Min Vdd (NOR) both inputs one input pn ratio For n =1.6, Vdd min = 1.9 kt/q = 48 mv mv pn ratio nm CMOS (simulation nominal process parameters) Source: M. Stan, L. Alarcon

11 Minimum Energy per Operation Predicted by von Neumann: ktln(2) Based on previous result moving one electron over Vddmin: Emin = QV DD /2 = q 2(ln2)kT/2q = ktln(2) Would be approximately three times larger for CMOS inverter with PMOS twice the size of NMOS At room temperature (300K): Emin = J Minimum sized CMOS inverter at 90 nm operating at 1V E = CVdd 2 = J, or 5 orders of magnitude larger! 11 How Close Can We Get?

12 Option 1: Subthreshold Operation Making Leakage Work You! Example: Energy-Aware FFT 12 A. Wang, A.P. Chandrakasan, "A 180mV FFT Processor Using Subthreshold Circuit Techniques," ISSCC 2004.

13 FFT Energy-Performance Curves Optimal (V dd, V th ) E E Switching Leakage = a C L V = I V 10 S DD V S 2 DD th T Supply Voltage (V DD ) Threshold Voltage (V th ) 13 Minimum Energy VDD = 0.35V and VT = 0.475V (estimated from switching and leakage models for a 0.18µm process) Courtesy: A. Wang, A. Chandrakasan, MIT

14 SubThreshold FFT 2.1 mm Data Memory Control logic Butterfly Twiddle Datapath ROMs Process Details 0.18µm CMOS process 6 layer metal 628k transistors 2.6 mm Operational down to 180 mv (fclock = 64 Hz) output clock DataOutput[1-0] DataReady 14

15 Confirmed by Measurements Clock frequency 10MHz 1MHz 100kHz 10kHz 1kHz Energy (nj) measured V DD (mv) estimated 100Hz V DD (mv) 15 The FFT operates between V DD =180mV-900mV and clock frequency of 164Hz-6MHz. The minimum energy dissipated is 155nJ/FFT at 350 mv for a 1024-point 16b FFT. The clock frequency is 10kHz and the FFT processor dissipates 0.6µW.

16 The Subliminal Processor (UMich) -14 Explores Minimum-Energy Processor subthreshold operation 3pJ per instruction at 350mV operation 10X less energy than previously reported 41 year operation on 1g Li-ion battery Research Areas Processor architectural trade-offs Low voltage memory design Process variation tolerance I-Mem 8-bit words ROM 8-bit words IF-STAGE 32 bits Prefetch Buffer ID-STAGE Reg File 8 x 16 bits 16 x 8 bits 32 x 4 bits bits Acc EX/MEM-STAGE 8-bit 16-bit 32-bit ALU Shifter x External Interrupts Event Scheduler D-Mem 8-bit words 16-bit words 32-bit words 16 CONTROL LOGIC Courtesy: D. Blaauw, T. Austin, UMICH

17 Is Sub-threshold The Way to Go? Achieves lowest possible energy dissipation But at a dramatic cost in performance tp (us) nm CMOS Power V dd (V) 17 Cycle time OPTIMAL POWER PERFORMANCE TRADEOFF CURVE

18 Option 2: Managing Leakage while Reducing Thresholds Stacked transistors enable aggressive threshold scaling Ion/Ioff increases with increasing stack height (leakage suppression) More robust to correlated (tune or adapt) and random variations (self-cancel) Decreased short channel effect 18 Courtesy: Mircea Stan, Louis Alarcon, UCB/Virginia

19 Impact of Stacking Devices 1 ns V DD 1 fj 19 V T Stack-depth 2

20 Impact of Stacking Devices 1 ns 1 fj V DD 20 V T Stack-depth 4

21 Impact of Stacking Devices 1 ns 1 fj V DD 21 V T Stack-depth 6

22 Impact of Stacking Devices 1 ns 1 fj V DD 22 V T Stack-depth 8

23 Optimal EDP, Energy, Delay vs. Stack 23

24 Complex Gates Reducing thresholds while containing leakage The return of PLAs? Regular Tunable NAND/NAND configuration A B B P 0 S In 2 In 1 In 0 Root Input A B to sense amp B S 24 F 0 F 1 Or pass-transistor logic Current-steering Regular Balanced delay Programmable

25 Some ULV Challenges: (1) Excessive Timing Variance 80 σ/µ (%) V dd (V) Timing variance increases dramatically with V dd reduction Design for large yield means huge overhead at low voltages: Worst case design at 300mV means over 200% overkill 25

26 Managing Systematic Variations Through Self-Adaptation Test inputs and responses T clock Test Module V dd Module V bb Energy-performance trade-off 26 Eswitching (fj) Adaptive Tuning Worst Case, w/o Vth tuning Nominal, w/ Vth tuning 10x 1.0E E E E E+07 Path Delay (ps) Move test onto the chip Dynamically adjust supply and threshold design parameters to center the design! Courtesy: K. Cao, Arizona

27 V 2 (V) Some ULV Challenges: (2) The Memory Data-Retention Voltage (DRV) DRV Condition: V DD 0 M 5 V 1 M 1 V DD M 3 V 2 0 M 6 V DD V V 2 Right inverter, when VDD 1 1 = 2 Left inverter V = V DRV Leakage current M 2 M 4 Leakage current 0.4 VTC of SRAM cell inverters 27 When V dd scales down to DRV, the Voltage Transfer Curves (VTC) of the internal inverters degrade to such a level that Static Noise Margin (SNM) of the SRAM cell reduces to zero. Source: Huifang Qin, QEDTI V DD =0.18V V DD =0.4V VTC 1 VTC V 1 (V)

28 The Impact of Process Variations DRV Spatial Distribution (256*128 Cells) Histogram of 32K SRAM cells DRV (mv) nm CMOS

29 Reducing the DRV Histogram of 32K SRAM cells Solution II: Error-tolerant SRAM design (with Redundancy and ECC) DRV (mv) SRAM Chip DRV 29 Option : ULV SRAM circuit optimization Combination of sizing and aggressive ECC reduces DRV to 150 mv

30 How about Mixed-Signal? 30 Reduced headroom challenges traditional mixed-signal design Process variation makes design centering tough Does further scaling help? Courtesy: R. Rutenbar, CMU

31 The Lure of the Sub-Threshold Region Greater transconductance (g (g m ) ) for for a given bias bias current Lower f t f, t, but but CMOS scaling helps g m / I D f T (Hz) Inversion Coefficient (IC)

32 Baseband Processor Technology 0.13um CMOS Synchronization is done! Power Supply < 1 V Data Input 30mV Chip Area 2.1mm x 2.1mm (pad limited) Reset 1 Integration 1 Total Power (Analog+Digital) 200 µw Data Output (from Analog) Data Output (from Digital) Synchronization Header Amplitude estimation: 10 bits Timing estimation: 25 bits (worst case) 32 Courtesy: Yan-Mei Li, UCB, CICC 2005

33 Example: Energy-Efficient Data Conversion Low-Voltage Low-Power Successive-Approximation A/D Simplest architecture wins! Fs Resolution 800KS/s 6 bits V dd.5v Pd ~2 uw 33 Source: S. Gambini, UCB

34 ULV(I) RF? Absolutely! Aggressive use of passives Unorthodox architectures to create gain (receiver) or increase efficiency (transmitter) at low voltage/current levels Stacking of components often helps (current re-use) Efficient oscillators are essential! 34

35 Extensive Use of (Innovative) Passives Si Electrodes Air AlN Air FBAR Si Drive Electrode 100µm Sense Electrode High Q-factor Small form factor MEMS/CMOS co-design Integration into IC process Impedance (Ω) Q > M 1G 10G Frequency (Hz) Ruby et. al. (Ultrasonics Symposium 2001) BAW Filter Mixer LNA Carpentier et. al. (ISSCC 2005)

36 Exploring the Limits: (Almost) Passive 1.9GHz Receiver P RX =200nW BW -3dB =4MHz Sensitivity=-38dBm (12dB SNR) S 11 : -9.3dB FBAR 1mm 36 Courtesy: B. Otis, N. Pletcher

37 Providing Gain: The Return of Super-Regenerative 1mm 2mm 37 Super-regenerative receiver creates gain at low-current level Sub-threshold operation No external components (inductors, crystals, capacitors) 0.13µm CMOS Otis, Chee, Rabaey, ISSCC 2005 Total Rx: 380µW

38 SuperRegenerative: Gain at Low Current 38 f q =100kHz -100dBm no -90dBm -70dBm -80dBm signal

39 SuperRegenerative: Gain at Low Current Detector oscillator transient: OOK modulation -80dBm, 5kbps Eye ST 0.13mm CMOS

40 Low-Voltage / Energy Oscillators Vdd R b M 2 M 1 Low power design techniques Complementary Gm stages to reduce I bias Large R b to reduce FBAR loading Sub-threshold MOSFET maximizes g m /I d Optimal choice of C 1 and C 2 FBAR C 1 C 2 FBAR Electrodes Bond wires L m C m R m CMOS Die R s L s 40 C o R o Y.H. Chee,, CICC 2005

41 Low-Energy FBAR Oscillator - Measurements Phase Noise (dbc/hz) k 100k 1M 10M Frequency offset (Hz) FBAR oscillator voltage swing (~140mV 90 µw) -98 dbc/hz -120 dbc/hz Instrument s noise floor Zero to peak voltage swing (mv) FBAR oscillator phase noise at 90µW power consumption Power Consumption (µw)

42 Dealing with Variations Calibrate LC oscillator with high accuracy reference (FBAR) Convert control voltage to digital signal and control oscillator frequency digitally Turn off FBAR oscillator and control loop after calibration To calibrate over 200MHz span better than 500kHz accuracy, 400 steps (9 bits) required Low-accuracy LC oscillator (<100µW) FBAR osc High-accuracy (500ppm) PD LPF ADC C LSB = 1 ff 9. FBAR oscillator (300µW) 42

43 Digitally Tuned VCO One bondwire and one integrated version implemented for comparison Bondwire oscillator performance Supply voltage Power consumption Nominal frequency Tuning Range Resolution Phase 1MHz offset 0.5V 100µW 1.9GHz 150MHz ~400kHz (9 bits) -115dBc/Hz 0.13µm ST CMOS, (2x2)mm 2 area Courtesy N. Pletcher, UCB, ESSCIRC 2005

44 Low Accuracy LC Oscillator - Results 0.5V supply Minimum startup conditions: Differential Vout (mv,p-p) Output Swing vs Bias Current Bondwire Integrated V dd = 0.3V I bias = 140µA (42µW) Core bias current (ua) Tuning range (10 bit code) 44

45 Innovative Architectures: Injection Locked Transmitter Use LC power oscillator instead of a power amplifier Self-drive reduces driver power Capacitive bank to tune oscillation within locked range Reference oscillator to lock the power oscillator to an accurate carrier frequency Output balun Bond wire inductor CMOS Die 45 Y.H. Chee et al, CICC 2005 Input balun

46 TX Performance Unlocked output spectrum Locked output spectrum TX consumes an average power of 1.5mW while delivering 1mW OOK signal (32% efficiency). Degradation of TX efficiency due to driver stage (FBAR oscillator) is only 1%. ST 0.13µm CMOS Transmitter Efficiency (%) Vdd = 280mV 22 Vdd = 260mV Vdd = 230mV Vdd = 210mV Radiated Power (µw)

47 Perspectives There is plenty of room at the bottom! Further scaling of energy/operation (or current per function) is essential for scaling to produce its maximum impact Current digital gates 5 orders of magnitude from minimum Exciting opportunities offered by new paradigms in computing Innovations at circuit, architecture and system level are essential Ample opportunity still to tame some wild horses The art of ingenuity H. De Man ISSCC 05 47