Implementation of a sub micron multifinger RF CMOS model in ADS cadence environment using spectre simulator
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1 Implementation of a sub micron multifinger RF CMOS model in ADS cadence environment using spectre simulator Stephane Beaussart AMI semiconductor Belgium BVBA 1
2 Outline Introduction Challenges and Issues RF model implementation Multi gate finger model vs. multi single gate model Complementary CMOS model Results Conclusions and perspectives 2
3 Introduction Higher Frequency / Higher speed systems Parasitic element become predominant and need to be account for Compensation is needed Reduce design cycle time First estimate prior realization at the schematic level Gain and Cost reduction 3
4 Multi finger MOS vs. Single finger model Single gate finger device Not really useful, lead to large chip area consumption Distributed effect due to large gate s width Multi gate finger device Less area Still limited in gate width. 4
5 Multi gate finger MOS: implementation Standard Software account for multi finger device: Multiplicity factor M Drain Drain Gate M=3 Gate Source Source 3 devices in Parallel 5
6 Multi gate finger MOS: implementation Using multiplicity factor lead to : Scale Electrical Parameters Cj, Cjsw, Cds, Cgs, Cgd, Rds, ect Scale Geometrical Parameters W, Ad, As, Pd, Ps By the Multiplicity factor M. 6
7 Multi gate finger MOS: implementation Simple scaling rule Widely used Geometrical scaling not longer hold true for multi finger structures. Limited effect on small devices Drawback for High speed and high frequency Improper determination of parasitic (output driver, ) 7
8 Multi gate finger MOS: implementation Multifinger device vs Multiple devices in Parallel M1:Multi finger device M2:Multiple device in Parallel S D S D S D S D S D Gate M1 mos M=1 nf=3 Gate M2 mos M=3 nf=1 8
9 Multi gate finger MOS: implementation How can we account correctly for multiplicity device S/D diffusion differs with the number of gate finger Selection on the first diffusion type : S or D based on designer needs Usually will minimize the drain capacitance Inner and outer diffusion may differs 9
10 Multi gate finger MOS: truth table Nbr Gate finger Nf 1 nums 1 numd 1 numis 0 numos 1 numid 0 numod 1» Define a truth table based Mos geometry and Process Bias parameters Nbr Gate finger Nf 3 nums 2 numd 2 numis 1 numos 1 numid 1 numod 1 Nbr Gate finger Nf 5 nums 3 numd 3 numis 2 numos 1 numid 2 numod 1 CAD / process Bias cawidth 0.3 catosti 0.14 catogate 0.22 Pcbias 0.05 Stibias 0 plidif 0.84 plodif 0.71 CAD / process Bias cawidth 0.3 catosti 0.14 catogate 0.22 Pcbias 0.05 Stibias 0 plidif 0.84 plodif 0.71 CAD / process Bias cawidth 0.3 catosti 0.14 catogate 0.22 Pcbias 0.05 Stibias 0 plidif 0.84 plodif
11 Multi gate finger MOS: truth table plodif plidif O S I D I S O D plidif=(cawidth+(2*(catogate+pcbias))) // Length of inner diffusion plodif=(catosti+stibias+cawidth+catogate+pcbias) // Length of outer diffusion 11
12 Multi gate finger MOS: truth table» Implementation of Source/ Drain area and perimeters // Drain Source area and perimeter calculation +ad=((numid*weff*plidif)+(numod*weff*plodif))/numd // Drain total area +as=((numis*weff*plidif)+(numos*weff*plodif))/nums // Source total area +pd=((numid*2*(weff+plidif))+(numod*2*(weff+plodif)))/numd // Drain perimeter +ps=((numis*2*(weff+plidif))+(numos*2*(weff+plodif)))/nums // Source perimeter 12
13 Multi gate finger MOS: circuit level implementation G Rds Cds Rpoly Rchannel Core BSIM3v3 S Rs S/B Rb D/B Rd D Rsb Rsbb Rdbb Rdb 13 stephane Beaussart B,MOS-AK meeting
14 Multi gate finger MOS: circuit level implementation Connection to the external world Sub circuit level 14
15 Multi gate finger MOS: circuit level implementation inline subckt enmrflbl25 (ed eg es eb) // SUB CIRCUIT LEVEL end Parameters W,L,NFG // truth table implementation accounting for even and odd gate finger number // Drain Source area and perimeter calculation +ad=((numid*weff*plidif)+(numod*weff*plodif))/numd // Drain total area +as=((numis*weff*plidif)+(numos*weff*plodif))/nums // Source total area +pd=((numid*2*(weff+plidif))+(numod*2*(weff+plodif)))/numd // Drain perimeter +ps=((numis*2*(weff+plidif))+(numos*2*(weff+plodif)))/nums // Source perimeter // CORE BSIM3 MODEL enmrflbl25 ( id ig es ib ) nch_rf w=weff l=leff M=NFG ad=0.0 as=0.0 pd =0.0 ps=0.0 // resistor definition rd ( ed id ) resistor r= function (numd, W) rs ( es is ) resistor r=function (nums, W) rg ( eg ig ) resistor r=functin (w, L, nfg) // rds ( ed n1) resistor r=function (W,Nfg) cds ( n1 es ) capacitor c=functin (w,nfg) // Diode definition ddb ( subn1 ed ) ndio_bare area=ad perim=pd m=numd dds ( subn2 es ) ndio_bare area=as perim=ps m=nums // // substrate network Rb ( ib eb ) resistor r=0 Rsbb ( subn2 mp ) resistor r=functin (w, nfg) Rdbb ( subn1 mp ) resistor r=functin (w, nfg) Rsb (subn2 eb ) resistor r=functin (w, nfg) Rdb (subn1 eb ) resistor r=functin (w, nfg) # S/D diffusion Consistent with the layout Top level user define parameters W, L, NFG 15
16 Multi gate finger MOS: device level comparison Standard 0.25 um CMOS technology RF model for Complementary MOS device DC and RF validation (beyond 20 GHz) Non linear validation Wide range of bias points Accuracy 10% in Y parameters Over temperature (up to 85 O C) 16
17 Multi gate finger MOS: device level comparison Layout view of a RF probable structure using GSG probes Ref. Plan 17
18 Multi gate finger MOS: device level comparison Standard Measurement Flow TRL calibration Extraction of the reference impedance De-embedding of DUT load, short, thru, open 18
19 Multi gate finger MOS: device level comparison Standard Parasitic extraction and modeling Flow Rg,Rd,Rs: Real Extrapolate linear fit R(Z) vs 1/(vgs upper Band. Pad capacitor Cpg, Cpd: Rg tune for S11 under strong inversion Imag(Y)@Vds=0 Inductance Lg, Ls, Ld: Z,Y matrix 19 Found to be negligible
20 Multi gate finger MOS: device level comparison Standard Parasitic extraction and modeling Flow Substrate network: Manly by tuning S22 No dedicated structures DC core BSIM3 parameters tuning Account for Rd and Rs shifted outside Mobility, transconductance, +/- 10 % accuracy 20
21 Multi gate finger MOS: device level comparison Typical DC results for N Mos transistor T=25,85 O C measured Ids Ids _RFMOS ids MOS meaured Gm Gm_RFMOS gm MOS id(vg) and Gm at T=25 O C and for transistor N01 (8x8x0.25) measured Ids Ids _RFMOS ids MOS meaured Gm Gm_RFMOS gm MOS id(vg) and Gm at T=85 O C and for transistor N01 (8x8x0.25) Vgs (V) Vgs (V) 21
22 Multi gate finger MOS: device level comparison Typical DC results for N Mos transistor O C. Measured RFMOS vgs=600e-3 RFMOS vgs=900e-3 RFMOS vgs=1.2 RFMOS vgs=1.5 RFMOS vgs= RFMOS vgs=2.1 RFMOS vgs=2.4 Idvd at T=25 O C for transistor N01 (8x8x0.25) Measured RFMOS vgs=600e-3 RFMOS vgs=900e-3 RFMOS vgs=1.2 RFMOS vgs=1.5 RFMOS vgs= RFMOS vgs=2.1 RFMOS vgs=2.4 Idvd at T=85 O C for transistor N01 (8x8x0.25) Vds (V) Vds (V)
23 Multi gate finger MOS: device level comparison Typical RF results for N&P Mos transistor (8x8x0.25): Cgs evolution in saturation region Cgs evolution measured datas RFMOS 8x8x0.25 vgs=1.0 v. MOS 8x8x0.25 vgs=1.0 v measured datas RFMOS 8x8x0.25 vgs=1.0 v. MOS 8x8x0.25 vgs=1.0 v Freq(GHz) Freq(GHz) 23
24 Multi gate finger MOS: device level comparison Typical RF results for N&P Mos transistor (8x8x0.25): 1600 Rout evolution in saturated region 8000 Rout evolution in saturation region measured datas RFMOS 8x8x0.25 vgs=1.0v MOS 8x8x0.25 vgs=1.0v measured datas RFMOS 8x8x0.25 vgs=1.0 v. MOS 8x8x0.25 vgs=1.0 v freq(ghz) freq(ghz) 24
25 Multi gate finger MOS: device level comparison Typical RF results for N&P Mos transistor (8x8x0.25): vds=2.5volts. Measured datas T=25 o C Gm evolution with the temperature Measured datas T=65 o C Measured datas T=85 o C RF T=25 o C Gm evolution with the temperature Measured datas T=25 o C Measured datas T=65 o C Measured datas T=85 o C RF T=65 o C RF T=25 o C 0.02 RF T=85 o C RF T=65 o C RF T=85 o C Freq(GHZ) Freq(GHZ)
26 Multi gate finger MOS: device level comparison HB N Mos transistor (8x8x0.25): vgs=1.0, vds=1.5volts. Vg(t) v1mts_de v1sts time, nsec v2mts_de v2sts time, nsec Vd(t) Ig(t) i1mts_de i1s ts i2mts_de i2s ts Id(t) time, nsec time, nsec 26
27 Output power 20 vs. input power 0 Pout Multi gate finger MOS: device level comparison HB N Mos transistor (8x8x0.25): vgs=1.0, vds=1.5volts Pouts-Pins Poutm-P inm Power gain vs. input power Pinm Pins Pouts1 Poutm Pinm Pins 27 Output Spectrum fre q, GHz
28 Multi gate finger MOS: device level comparison HB N Mos transistor (8x8x0.25): vgs=1.0, vds=1.5volts. Vg(t) Vd(t) v1mts_de v1sts v2mts_de v2sts time, psec time, psec Ig(t) i1mts_de i1 s ts i2mts_de i2 s ts Id(t) time, psec time, psec 28
29 Output power vs. input power Multi gate finger MOS: device level comparison HB 2.45GHz N Mos transistor (8x8x0.25): vgs=1.0, vds=1.5volts. Pout Pouts-Pins Poutm-Pinm Power gain vs. input power Pinm Pins Pinm Pins 10 0 Pouts1 Poutm Output Spectrum fre q, GHz 29
30 Multi gate finger MOS: device level comparison Statistical distribution of normalized RF parameters Cgd and Gm T=25 O C Cgd (ff) Mean Gm (ms) Cgd distribution for transistor N01 Wafer 06 - Lot C65031 Typical model 20.5 Counts Mean Median Std Deviation Variance Cgd (ff) Gm distribution for transistor N01 Wafer 06 Lot C Mean 10 Median Std Deviation Variance 8 Typical Model Gm (ms) Lot C Lot C Range Range
31 Conclusion & perspectives Proper implementation of mutifinger RF CMOS device demonstrate. Allow for first device parasitic estimation before physical circuit layout Account for the shared nature of S/D diffusion in multifinger structure Proper consideration of multiplicity and multifinger structure device. Better than simple used of inherent multiplicity feature (m) available in most common software. Use of inline sub circuit ( remove a level o hierarchy) 31
32 Conclusion & perspectives Validation of the implemented model DC validation within +/- 10% RF validation over wide frequency range +/- 10% Non linear validation at 900MHz and 2,45 GHz Temperature validation up to 85 O C Scalable model in W & Nfg for the 0.25 node technology. 32
33 Aknowlegments Dominique Schreurs, ESAT TELEMIC KUL Ahmed A.J. Alabadelah, ESAT TELEMIC KUL For performing the non linear validation 33
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