Four-Port Network Parameters Extraction Method for Partially Depleted SOI with Body-Contact Structure

Transcription

1 J Electron Test (216) 32: DOI 1.17/s x Four-Port Network Parameters Extraction Method for Partially Depleted SOI with Body-Contact Structure Jun Liu 1 & Yu Ping Huang 1 & Kai Lu 1 Received: 24 August 216 /Accepted: 31 October 216 /Published online: 11 November 216 # Springer Science+Business Media New York 216 Abstract This work presents a model parameter extraction method based on four-port network for RF SOI MOSFET modeling. The gate, drain, source and body terminals are served as four separate ports. Four-port measurement simplifies the determination of small-signal equivalent circuit model elements such as parameters related to the body terminal which become clear in the equivalent circuit analysis. The extraction method of the RF SOI MOSFET extrinsic parasitic elements was also presented. The accuracy of the model extraction was verified by measurement and simulation from 1 MHz to 2 GHz. Keywords SOI MOSFET. 4-port S-parameter. Modeling 1 Introduction Silicon-on-insulator (SOI) technology is considered as a good candidate for low-power microwave circuits for excellent RF performance such as gain, speed, and cut-off frequency (f T ) [6]. However, a reasonable methodology for accurately modeling RF SOI MOSFETs has not been proposed. Responsible Editor: T. Xia * Jun Liu ljun77@hdu.edu.cn Different from a bulk-silicon MOSFET, the isolate layer actually separates the substrate of a RF SOI MOSFET into three parts: bulk region, the isolator (BOX layer) and the original substrate under the BOX, which also form a back-gate MOSFET. Extraction of parameters related to the bulk terminal has become a significant challenge for modeling engineers. Conventional two-port network is used in most RF MOSFET equivalent circuits [2, 9], with the gate terminal served as the first port, the drain terminal defined as the second port and the source terminal was shorted to the substrate serving as the common terminal. For SOI MOSFET modeling, because of the source and substrate terminals are connected together, parameters related to the body terminal will not be able to separate according to the insufficient information provided by two-port measurement data. A possible method is to characterize the same device in multiple configurations (common source, common gate) using 2-port measurements, and transform these to obtain the full 4-terminal model. However these methods require more measurements and larger wafer space usage. In this work, the complete equivalent circuit of PD SOI nmosfet, including extrinsic parasitics, substrate network and intrinsic model, is proposed. All parameters of the small-signal equivalent circuit model were extracted in ICCAP, and the simulated and measured data were compared within the entire measurement frequency range. 1 Yu Ping Huang 14141@hdu.edu.cn Kai Lu lvkai@hdu.edu.cn Key Laboratory for RF Circuits and Systems of Ministry of Education, Hangzhou Dianzi University, Hangzhou, China 2 Four -Port Measurement and Extraction Method In four-port network S-parameter measurement, the gate, drain, source and body of the RF SOI MOSFET are connected individually to four signal pads. These four signal pads incorporated with a reference ground form a four-port ground-

2 764 J Electron Test (216) 32: D Cgs Cd Cs Fig. 2 The delta to star conversion for the drain-gate-source capacitance network signal-ground (GSG) test structure and the RF SOI MOSFET can be treated as a four-port device and characterized by fourport measurement [7]. In this work, the small-signal equivalent circuit for SOI nmosfet is given in Fig. 1.Theintrinsic elements of the model topology consists of the gate to source capacitance C gs, the gate to drain capacitance C gd, the drain to source capacitance C ds, the trans-conductance G m and drain conductance G ds. L g, L d, L s, L b,, R g, R d, R s and R b represent the parasitic inductances and resistances of gate (G), drain (D), source (S), and body (B), respectively. C gbe, C sbe and C dbe represent the shunt capacitance for gate to substrate, source to substrate and drain to substrate, respectively. C sb and C db represent the junction capacitance of source and drain to body, respectively. C gb is the capacitance between gate and body. R gb, R sb, and R db represent resistances from gate, source and drain to body, respectively. C box represents the capacitance of buried oxide. C sub and R sub represent the substrate capacitance and resistance. The elements in the dotted box are determined from 4-port network measurement. The following model parameters are extracted mainly based on Y parameters and Z parameters. Y parameters and Z parameters represent the admittance parameters and impedance parameters, respectively. The substrate resistances are unable to be extracted from a MOSFET biased in active region because of the more significant intrinsic components (G m, G ds ) and the substrate resistances have weak dependence on the bias condition [2]. While the substrate coupling effect is minor, G ds and G m are directly extracted from the real part of Y DD and the real part of Y DG at low frequency range, respectively, similar to the two-port network parameters extraction method [3]. While the bias voltage on each terminal is zero (cold device), the components inside the solid box of the equivalent circuit can be ignored. A delta-star transformation of the drain-gate-source capacitances can be shown in Fig. 2 [1] and the reduction techniques has been described in [8]. With the body terminal open circuited, the effect of the substrate network will be negligible in comparison with the draingate-source network. As shown in (1 4), R g, R d, R s can be directly extracted from real part of Z GG, Z GS and Z SS with considering common drain. R b can be determined by Z BG with the bulk as the common terminal. R d ¼ Real ðz GS Þ ¼ Real R d þ jωl d þ 1 jωc d R g ¼ Real ðz GG Þ Real ðz SG Þ ¼ Real R g þ jωl g þ 1 jωc g R s ¼ Real ðz SS Þ RealðZ SG Þ ¼ Real R s þ jωl s þ 1 jωc s R b ¼ Real ðz BG Þ R g ¼ Real jωl g þ 1 jωc g ð1þ ð2þ ð3þ ð4þ L d, L g, L d and L s can be found by applying a similar method to the one described in []. For example, to obtain L d, the imaginary part of Z GS can be expressed as: A ¼ ω ImagðZ GS Þ ¼ ω 2 L d 1 ðþ C d ω =2πf,andf is the operating frequency. L d can be extracted from the slope of the linear regression of the experimental A versus ω 2. L g, L s, L b can be extracted in a similar way. At low frequencies, the reactance of the inductances is very small compared to the capacitances and R d and R s are negligible. Figure 3 as an example, Y GG is the ratio between the gate- Cg Cgbe G Lg Ld Rd Cgs GmVg Cgb b Cdbe Cdb Rdb Gds Csb Rsb Csub Cbox E Rb Rsub i D R g C gb C gs C gd Rs Csbe Lb Ls S Vb Fig. 1 Proposed small-signal equivalent circuit for RF SOI MOSFETs Fig. 3 Y GG -equivalent circuit C gb R gb

3 J Electron Test (216) 32: current and gate-voltage with the drian, source and bulk terminals open circuited, and can be determined by (6). Y GG ¼ i G v G vd ¼v B ¼v S ¼ Y BD v D C dbe C db R db i B 1 1 ¼ R g þ jω C gs þ C gd þ C gbe þ B ð6þ Similar to the calculation of Y GG, Y SG and Y DG can be derived as follow: Y SG ¼ i S ¼ Y GG vd ¼v B ¼v S ¼ Y DG ¼ i D ¼ Y GG vd ¼v B ¼v S ¼ B ¼ jωc gb þ ω 2 C 2 gb R gb 1 þ ω 2 C 2 gb R2 gb jωc gs jωc gs þ jωc gd þ jωc gbe þ B jωc gd jωc gs þ jωc gd þ jωc gbe þ B ð7þ ð8þ ð9þ The higher order terms of (ω R X C X ) were neglected because they are much smaller than (ω R X C X ) within the measurement frequency range. And Y GG, Y SG and Y DG can be approximated as (1 12). According to Eqs. (1) (12), C gs, C gd, C ds can be directly extracted from Imag (Y SG )/ω, Imag (Y DG) /ω and Imag (Y SD )/ω, respectively. Y GG jωðcgs þ þ Cgb þ CgbeÞ þω 2 ðcgs þ þ Cgb þ CgbeÞ 2 ð1þ R g Y SG jωc gs þ ω 2 C gs þ C gd þ C gb þ C gbe Cgs R g ð11þ Y DG jωc gd þ ω 2 C gs þ C gd þ C gb þ C gbe R g ð12þ The simulation results show that the substrate parameters has little impact on Y BB, Y BD and Y BS.AsY BD for example, Y BD -equivalent circuit is given in Fig. 4 and the Y-parameters can be approximated as follow: Y BD ¼ jωc dbe þ jωc db þ ω 2 C 2 db R db 1 þ ω 2 C 2 ð13þ db R2 db Y BS ¼ jωc sbe þ jωc sb þ ω 2 C 2 sb R sb 1 þ ω 2 C 2 sb R2 sb ð14þ Y BS v S C sbe i B Y BB ¼ j w C box þ jwc sb þ w 2 C 2 sb R sb 1 þ w 2 C 2 sb R2 sb þ jwc gb þ w 2 C 2 gb R gb 1 þ w 2 C 2 gb R2 gb C sb Fig. 4 Y BD and Y BD equivalent circuits þ jwc db þ w 2 C 2 db R db 1 þ w 2 C 2 db R2 db ð1þ According to Eq. (13), through a simple conversion formula, Real (Y BD ) can be expressed as Eq. (16). w 2 Y ¼ RealðY BD Þ ¼ 1 C 2 db R þ w 2 R db db R sb ð16þ R db and C db can be determined from the slope and intercept of the linear regression of the experimental Y versus ω 2. C dbe is calculated from Imag(Y BD )/ω -C db. Similarly, C sb, C sbe, R sb, C gb, C gbe and R gb can be extracted from Y BS and Y SG in a similar way. Then, C box can be extracted from Y BB. Substrate parasitic resistance and capacitance are mainly affected by the coupling between source and drain. Therefore, the extraction of substrate resistance and capacitance can be made by using the properties of source and drain ports. The source side branch has little impact on the Y DD.Inorder to simplify the extraction algorithm, Y DD -equivalent circuit is given in Fig. and the Y DD can be approximated as follow: Vd Id Fig. Y DD -equivalent circuit Cdbe Cdb Cbox Csub Rdb Rsub Y1

4 766 J Electron Test (216) 32: C apacitance / ff Y DD ¼ jωc ds þ jωc gd þ ω 2 C 2 gd R g 1 þ ω 2 C 2 þ jωc db þ ω 2 C 2 db R db gd R2 gd 1 þ ω 2 C 2 db R2 db jωc dbe ðy1 þ jωc box Þ þ Y1 þ jωðc box þ C dbe Þ ð17þ Y1 ¼ jωc sub þ 1 R sub Frequency /GHz ð18þ C gd, R g, C ds, C dbe, C box, C db and R db have been obtained in the previous steps, Y1 can be calculated from Y DD.Then,R sub and C sub can be extracted from the real and imaginary part of Y1, respectively. 3 Results and Discussion Cgs Fig. 6 Cgs (red), (pink) and(blue) forthecolddevice The RF SOI nmosfet with 32 fingers,.13 μm lengthand 2 μm width was fabricated using HHGrace.13 μm RFSOI process. The frequency range of 4-port network measurement is extended from 2 MHz to 2 GHz. Four-port S-parameters were measured and de-embedded (Open - Short) [4]usingan Agilent PNA-X 244 Network Analyzer and a CASCADE Summit 12, probe station. Then, the de-embedded S-parameters were transformed to Y-parameters and Z-parameters for the parameters extraction. Figure 6 shows the extracted results of C gs, C gd and C ds for the cold device. The values of the capacitances are almost constant among the measuring /Ohm Resistance 1 1 Rd Rs Rb Frequency /GHz Fig. 7 Rd (red), (bule), Rs (pink) and Rb (green) for the cold device frequency. Figure 7 shows the extracted results of R d, R g, R s and R b for the cold device. The four port measurement data and the simulation data of the equivalent circuit of cold device up to 2 GHz are shown in the Fig. 8. The extracted parameters of.13 μm RF SOI nmosfet extracted from the device at zero bias (V g = V, V d = V, V s = Vand V b = V) are listed in Table 1. 1 real(y.11) imag(y.11) real(y.12) imag(y.12) real(y.13) real(y.14) imag(y.13) imag(y.14) (a) real(y.21) imag(y.21) real(y.22) imag(y.22) real(y.23) imag(y.23) -1 real(y.24) imag(y.24) (b) real(y.31) imag(y.31) real(y.32) imag(y.32) -1 real(y.33) imag(y.33) real(y.34) imag(y.34) -1 2 real(y.41) 2 imag(y.41) real(y.42) 1 imag(y.42) 1 real(y.43) (c) imag(y.43) -1 real(y.44) imag(y.44) (d) Fig. 8 Measured (Symbols) and model simulated (Lines) Y-parameters (a)y 11,Y 12,Y 13 and Y 14 (b)y 21,Y 22,Y 23 and Y 24 (c)y 31,Y 32,Y 33 and Y 34 (d) Y 41,Y 42,Y 43 and Y 44 at zero bias

5 J Electron Test (216) 32: Table 1 Values of the extracted model parameters of a RF SOI nmosfet at zero bias Element Value Element Value Element Value Element Value L g (ph) C gs (ff) 43.4 C dbe (ff) 1.97 R d (Ω) 29.9 L d (ph) 1.1 C gd (ff) C sb (ff) R db (Ω) L s (ph) C ds (ff) R sb (Ω) 3.66 C db (ff) 18.2 L b (ph) 14.6 C gb (ff) 24.7 C sbe (ff) 3.14 R gb (Ω) 34.9 C gbe (ff) R s (Ω) 9.3 R b (Ω) 17.4 C box (ff).26 R g (Ω) 1.4 R sub (Ω) C sub (ff) 46 4 Conclusion In this paper, the extraction method for the complete small signal equivalent circuit of PD RF SOI MOSFET based on 4-port measurement data has been presented. Good agreement between the measured and simulated output admittance of the device at zero bias, which verified and validated the accuracy of the model and model parameter extraction method proposed here. It suggests that 4-port measurement based extraction method is a very potential method to characterize and model the small-signal behavior of RF SOI MOSFET. Acknowledgments This work was supported by the National Natural Science Foundation of China under Grant References 1. Brinkhoff J, Rustagi SC, Shi J, Lin F (27) MOSFET model extraction using GHz four-port measurements. In: Proc. IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp Han J, Je M, Shin H (22) A simple and accurate method for extracting substrate resistance of RF MOSFETs. IEEE Electron Device Lett 23(7): Jen HM, Enz CC, Pehlke DR, Schroter M (1999) Accurate modeling and parameter extraction for mos transistors valid up to 1 GHz. IEEE Trans Electron Devices 46(11): Koolen MCAM, Geelen, JAM, Versleijen MPJG (1991) An improved DC-embedding technique for on-wafer high-frequency characterization. In: Proc. Bipolar circuits and technology meeting, pp Lee S (2) Accurate rf extraction method for resistances and inductances of sub-.1 μm CMOS transistors. Electron Lett 41(24): Lee BJ, Kim K, Yu CG et al (2) Effects of gate structures on the RF performance in PD SOI MOSFETs. IEEE Microwave Wireless Compon Lett 1(4): Wu SD, Huang GW, Chen KM, Chang CY, Tseng HC, Hsu TL (2) Extraction of substrate parameters for rf mosfets based on four-port measurement. IEEE Microwave Wireless Compon Lett 1(6): Wu SD, Huang GW, Cheng LP, Wen SY, Chang CY (23) Characterization of 2-port configuration MOSFETs amplifiers by 4-port measurement. In: Proc. Asia-Pacific Microwave Conf, vol. 3, pp Yang MT, Ho PPC, Wang YJ, Yeh TJ, Chia YT (23) Broadband small-signal model and parameter extraction for deep sub-micron MOSFETs valid up to 11 GHz. In: Proc. IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, pp Jun Liu received his M.S. degree from Hangzhou Dianzi University in 26 and PhD degrees from Dublin City University in 211. He is a research associate in Key Laboratory for RF Circuits and Systems of Ministry of Education, Hangzhou Dianzi University. His research interests include the semiconductor device modeling and characterizing technology and integrated circuit CAD technology. YuPing Huang is currently working towards her M. S. degree at Key Laboratory for RF Circuits and Systems of Ministry of Education, Hangzhou Dianzi University. Her main research interests include the micro nano semiconductor device modeling and integrated circuit CAD technology. Kai Lu received his PhD degree from University of Chinese Academy of Sciences. He is currently a lecturer in Key Laboratory for RF Circuits and Systems of Ministry of Education, Hangzhou Dianzi University. His research interests include the micro nano semiconductor device modeling and characterizing technology.