MC74LVX8051. Analog Multiplexer / Demultiplexer. High Performance Silicon Gate CMOS

Size: px

Start display at page:

Download "MC74LVX8051. Analog Multiplexer / Demultiplexer. High Performance Silicon Gate CMOS"

Edwin Austin
5 years ago
Views:

MC74X051 Analog Multiplexer / Demultiplexer igh Performance Silicon Gate CMOS The MC74X051 utilizes silicon gate CMOS technology to achieve fast propagation delays, low ON resistances, and low

1 MC74X051 Analog Multiplexer / Demultiplexer igh Performance Silicon Gate CMOS The MC74X051 utilizes silicon gate CMOS technology to achieve fast propagation delays, low ON resistances, and low leakage currents. This analog multiplexer/demultiplexer controls analog voltages that may vary across the complete power supply range (from to ). The X051 is similar in pinout to the high speed C4051A and the metal gate MC14051B. The Channel Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is IG, all analog switches are turned off. The Channel Select and Enable inputs are compatible with standard CMOS outputs; with pull up resistors they are compatible with STT outputs. This device has been designed so that the ON resistance (R on ) is more linear over input voltage than R on of metal gate CMOS analog switches. Features Fast Switching and Propagation Speeds ow Crosstalk Between Switches Diode Protection on All Inputs/Outputs Analog Power Supply Range ( ) = 2.5 to.0 Digital (Control) Power Supply Range ( ) = 2.5 to.0 Improved inearity and ower ON Resistance Than Metal Gate Counterparts ow Noise In Compliance With the Requirements of JEDEC Standard No. 7A Chip Complexity: X FETs or 4 Equivalent Gates Pb Free Packages are Available* SOIC D SUFFIX CASE 751B TSSOP DT SUFFIX CASE 94F SOEIAJ M SUFFIX CASE 9 MARKING DIAGRAMS A = Assembly ocation W or = Wafer ot Y = Year WW or W = Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. 1 1 X051 AWYWW 1 X 051 AYW X051 AYW *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SODERRM/D. Semiconductor Components Industries, C, 05 April, 05 Rev. 4 1 Publication Order Number: MC74X051/D

2 MC74X051 X2 X1 X0 X3 A B C X0 13 X1 14 X2 ANAOG INPUTS/ X3 12 OUTPUTS X4 1 X5 5 X 2 X7 4 A CANNE SEECT B INPUTS C 9 ENABE MUTIPEXER/ DEMUTIPEXER PIN = PIN = OGIC DIAGRAM MC74X051 Single Pole, Position Plus Common Off 3 X COMMON OUTPUT/ INPUT X4 X X X7 X5 Enable NC FUNCTION TABE MC74X051 Control Inputs Select Enable C B A X = Don t Care PIN CONNECTION AND MARKING DIAGRAM (Top iew) X X X ON Channels X0 X1 X2 X3 X4 X5 X X7 NONE ORDERING INFORMATION MC74X051DR2 MC74X051DR2G Device Package Shipping SOIC SOIC (Pb Free) 00 Tape & Reel MC74X051DT TSSOP * 9 Units / Rail MC74X051DTR2 TSSOP * 00 Tape & Reel MC74X051M MC74X051MG SOEIAJ SOEIAJ (Pb Free) 50 Units / Rail MC74X051ME MC74X051MEG SOEIAJ SOEIAJ (Pb Free) 00 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD0/D. *This package is inherently Pb Free. 2

3 MC74X051 ÎÎ MAXIMUM RATINGS SymbolÎÎÎÎÎÎÎÎÎÎÎÎÎ Parameter ÎÎÎÎÎÎ alue ÎÎÎ Unit ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ Positive DC Supply oltage (Referenced to ) ÎÎÎÎÎÎ 0.5 to ÎÎÎ ÎÎÎÎ IS ÎÎÎÎÎÎÎÎÎÎÎÎÎ Analog Input oltage ÎÎÎÎÎÎ 0.5 to ÎÎÎ ÎÎÎÎ in ÎÎÎÎÎÎÎÎÎÎÎÎÎ Digital Input oltage (Referenced to ) ÎÎÎÎÎÎ 0.5 to ÎÎÎ ÎÎÎÎ I ÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Current, Into or Out of Any Pin ÎÎÎÎÎÎ ± ÎÎÎ ma ÎÎÎÎ P D ÎÎÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation in Still Air, SOIC Package ÎÎÎÎÎÎ 500 ÎÎÎ mw TSSOP Package 450 ÎÎÎ T ÎÎÎÎ stg ÎÎÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature Range 5 to + 0 C ÎÎÎÎÎÎÎÎ T ÎÎÎÎ ead Temperature, 1 mm from Case for Seconds C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Derating SOIC Package: 7 mw/ C from 5 to 1 C TSSOP Package:.1 mw/ C from 5 to 1 C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. owever, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be constrained to the range ( in or out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit ÎÎÎ ÎÎÎÎ CC ÎÎÎÎÎÎÎÎÎÎÎÎÎ Positive DC Supply oltage (Referenced to ) ÎÎÎÎÎÎÎÎ ÎÎÎÎ IS ÎÎÎÎÎÎÎÎÎÎÎÎÎ Analog Input oltage 0.0 ÎÎÎÎÎÎ CC ÎÎÎ ÎÎÎÎ in Digital Input oltage (Referenced to ) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ CC ÎÎÎ ÎÎÎÎ IO* Static or Dynamic oltage Across Switch 1.2 T ÎÎÎÎ A Operating Temperature Range, All Package Types C t ÎÎÎÎ r, t f Input Rise/Fall Time ns/ (Channel Select or Enable Inputs) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ = 3.3 ± 0.3 ÎÎÎ 0 ÎÎÎÎ 0 ÎÎÎ = 5.0 ± 0.5 *For voltage drops across switch greater than 1.2 (switch on), excessive current may be drawn; i.e., the current out of the switch may contain both and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. 0 3

4 MC74X051 DC CARACTERISTICS Digital Section (oltages Referenced to ) Symbol Parameter Condition I I I in Minimum igh evel Input oltage, Channel Select or Enable Inputs Maximum ow evel Input oltage, Channel Select or Enable Inputs Maximum Input eakage Current, Channel Select or Enable Inputs R on = Per Spec 2.5 R on = Per Spec 2.5 Guaranteed imit 55 to C 5 C 1 C Unit in = or ± 0.1 ± 1.0 ± 1.0 A I CC Maximum Quiescent Supply Current (per Package) Channel Select, Enable and IS = or ; IO = A DC EECTRICA CARACTERISTICS Analog Section ÎÎÎÎÎÎÎÎÎÎ Guaranteed imit ÎÎÎ ÎÎ ÎÎÎÎ CC 55 to ÎÎÎÎ ÎÎÎ ÎÎÎ Symbol Parameter Test Conditions C 5 C 1 C Unit ÎÎÎÎÎÎÎÎÎÎÎÎ R ÎÎÎÎ on Maximum ON Resistance ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ in = I or I IS = to ÎÎÎ ÎÎÎÎ ÎÎÎÎ 32 ÎÎÎ 37 ÎÎÎ I S.0 ma (Figures 1, 2) 2 ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ in = I or I IS = ÎÎÎÎÎÎÎÎÎÎÎÎÎ or (Endpoints) 2 35 I S.0 ma (Figures 1, 2) ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ R ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ on Maximum Difference in ON ÎÎÎÎÎÎÎÎÎ in = I or I ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ Resistance Between Any Two ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ IS = 1/2 ( ).0 12 ÎÎÎÎÎÎÎÎÎÎÎÎÎ I off I on Channels in the Same Package Maximum Off Channel eakage Current, Any One Channel Maximum Off Channel eakage Current, Common Channel Maximum On Channel eakage Current, Channel to Channel I S.0 ma in = I or I ; IO = or ; Switch Off (Figure 3) in = I or I ; IO = or ; Switch Off (Figure 4) in = I or I ; Switch to Switch = or ; (Figure 5) A A 4

5 MC74X051 AC CARACTERISTICS (C = 50 pf, Input t r = t f = 3 ns) Symbol t P, t P t P, t P t PZ, t PZ t PZ, t PZ Parameter Maximum Propagation Delay, Channel Select to Analog Output (Figure 9) Maximum Propagation Delay, Analog Input to Analog Output (Figure ) Maximum Propagation Delay, Enable to Analog Output (Figure ) Maximum Propagation Delay, Enable to Analog Output (Figure ) Guaranteed imit 55 to C 5 C 1 C Unit C in Maximum Input Capacitance, Channel Select or Enable Inputs pf C I/O Maximum Capacitance Analog I/O pf (All Switches Off) Common O/I Feedthrough C, = 5.0 C PD Power Dissipation Capacitance (Figure 13)* 45 pf * Used to determine the no load dynamic power consumption: P D = C PD 2 f + I CC. ns ns ns ns ADDITIONA APPICATION CARACTERISTICS ( = 0 ) Symbol Parameter Condition BW Maximum On Channel Bandwidth or Minimum i Frequency Response (Figure ) Off Channel Feedthrough Isolation (Figure 7) Feedthrough Noise. Channel Select Input to Common I/O (Figure ) TD Total armonic Distortion (Figure 14) *imits not tested. Determined by design and verified by qualification. f in = 1Mz Sine Wave; Adjust f in oltage to Obtain 0dBm at OS ; Increase f in Frequency Until db Meter Reads 3dB; R = 50, C = pf f in = Sine Wave; Adjust f in oltage to Obtain 0dBm at IS f in = kz, R = 00, C = 50pF f in = 1.0Mz, R = 50, C = pf in 1Mz Square Wave (t r = t f = ns); Adjust R at Setup so that I S = 0A; Enable = R = 00, C = 50pF R = k, C = pf f in = 1kz, R = k, C = 50pF TD = TD measured TD source IS = 2.0 PP sine wave IS = 4.0 PP sine wave IS = 5.0 PP sine wave imit* C Unit Mz db m PP % 5

6 MC74X051 Ron, ON RESISTANCE (OMS) C 5 C C 55 C IN, INPUT OTAGE (OTS) Figure 1a. Typical On Resistance, = R on, ON RESISTANCE (OMS) 5 1 C 5 C C 55 C R on, ON RESISTANCE (OMS) 5 1 C 5 C C 55 C IN, INPUT OTAGE (OTS) Figure 1b. Typical On Resistance, = IN, INPUT OTAGE (OTS) Figure 1c. Typical On Resistance, = POTTER PROGRAMMABE POWER SUPPY MINI COMPUTER DC ANAYZER + DEICE UNDER TEST ANAOG IN COMMON OUT Figure 2. On Resistance Test Set Up

7 MC74X051 A NC ANAOG I/O I I Figure 3. Maximum Off Channel eakage Current, Any One Channel, Test Set Up Figure 4. Maximum Off Channel eakage Current, Common Channel, Test Set Up A ON N/C f in 0.1 F ON OS C * R db METER ANAOG I/O I Figure 5. Maximum On Channel eakage Current, Channel to Channel, Test Set Up Figure. Maximum On Channel Bandwidth, Test Set Up f in 0.1 F IS R OS C * R db METER R ANAOG I/O R ON/ /ON R C * TEST POINT I or I CANNE SEECT in 1 Mz t r = t f = 3 ns CANNE SEECT Figure 7. Off Channel Feedthrough Isolation, Test Set Up Figure. Feedthrough Noise, Channel Select to Common Out, Test Set Up 7

8 MC74X051 CANNE SEECT 50% ANAOG I/O ON/ /ON C * TEST POINT t P t P ANAOG OUT 50% CANNE SEECT Figure 9a. Propagation Delays, Channel Select to Analog Out Figure 9b. Propagation Delay, Test Set Up Channel Select to Analog Out ANAOG IN 50% ANAOG I/O ON C * TEST POINT t P t P ANAOG OUT 50% Figure a. Propagation Delays, Analog In to Analog Out Figure b. Propagation Delay, Test Set Up Analog In to Analog Out t f t r 90% CC ENABE 50% % t PZ t PZ ANAOG OUT ANAOG OUT 50% 50% t PZ t PZ % 90% Figure a. Propagation Delays, Enable to Analog Out IG IMPEDANCE O O IG IMPEDANCE POSITION 1 WEN TESTING t PZ AND t PZ POSITION 2 WEN TESTING t PZ AND t PZ ANAOG I/O ENABE ON/ C * Figure b. Propagation Delay, Test Set Up Enable to Analog Out 1k TEST POINT

9 MC74X051 f in 0.1 F R IS ON OS ANAOG I/O ON/ /ON A NC R R C * R C * CANNE SEECT Figure 12. Crosstalk Between Any Two Switches, Test Set Up Figure 13. Power Dissipation Capacitance, Test Set Up IS OS 0.1 F TO f in ON DISTORTION R METER C * Figure 14a. Total armonic Distortion, Test Set Up db FUNDAMENTA FREQUENCY DEICE SOURCE FREQUENCY (kz) Figure 14b. Plot, armonic Distortion APPICATIONS INFORMATION The Channel Select and Enable control pins should be at or logic levels. being recognized as a logic high and being recognized as a logic low. In this example: = = logic high = 0 = logic low The maximum analog voltage swing is determined by the supply voltage. The positive peak analog voltage should not exceed. Similarly, the negative peak analog voltage should not go below. In this example, the difference between and is five volts. Therefore, using the configuration of Figure, a maximum analog signal of five volts peak to peak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not connected). owever, tying unused analog inputs and outputs to or through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch. Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that: = 2 to volts When voltage transients above and/or below are anticipated on the analog channels, external Germanium or Schottky diodes (D x ) are recommended as shown in Figure. These diodes should be able to absorb the maximum anticipated current surges during clipping. 9

10 MC74X051 0 ANAOG SIGNA ON ANAOG SIGNA 0 D x D x ON/ D x D x 9 TO EXTERNA CMOS CIRCUITRY 0 to 5 DIGITA SIGNAS Figure. Application Example Figure. External Germanium or Schottky Clipping Diodes ANAOG SIGNA ON/ ANAOG SIGNA * R R R ANAOG SIGNA ON/ ANAOG SIGNA 9 STT/NMOS CIRCUITRY 9 STT/NMOS CIRCUITRY * 2K R K CT1GT50 BUFFERS a. Using Pull Up Resistors b. Using CT Interface Figure 17. Interfacing STT/NMOS to CMOS Inputs A EE SIFTER 13 X0 14 X1 B EE SIFTER X2 12 X3 C 9 EE SIFTER 1 X4 5 X5 ENABE EE SIFTER 2 X 4 X7 Figure 1. Function Diagram, X051 3 X

11 MC74X051 PACKAGE DIMENSIONS SOIC D SUFFIX CASE 751B 05 ISSUE J A 9 1 B P P 0. (0.0) M B S NOTES: 1. DIMENSIONING AND TOERANCING PER ANSI Y1M, CONTROING DIMENSION: MIIMETER. 3. DIMENSIONS A AND B DO NOT INCUDE MOD PROTRUSION. 4. MAXIMUM MOD PROTRUSION 0. (0.00) PER SIDE. 5. DIMENSION D DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE (0.005) TOTA IN EXCESS OF TE D DIMENSION AT MAXIMUM MATERIA CONDITION. T SEATING PANE G K C D P 0. (0.0) M T B S A S M R X 45 J F MIIMETERS INCES DIM MIN MAX MIN MAX A B C D F G 1.27 BSC BSC J K M P R TSSOP DT SUFFIX CASE 94F 01 ISSUE A 0. (0.00) T 0. (0.00) T 0. (0.004) T SEATING PANE U PIN 1 IDENT. U D S S 2X /2 C X K REF 0. (0.004) M T U S S 9 1 A G B U N N J J1 F DETAI E DETAI E K K1 ÇÇÇ ÉÉÉ SECTION N N 0. (0.0) M W NOTES: 1. DIMENSIONING AND TOERANCING PER ANSI Y1M, CONTROING DIMENSION: MIIMETER. 3. DIMENSION A DOES NOT INCUDE MOD FAS. PROTRUSIONS OR GATE BURRS. MOD FAS OR GATE BURRS SA NOT EXCEED 0. (0.00) PER SIDE. 4. DIMENSION B DOES NOT INCUDE INTEREAD FAS OR PROTRUSION. INTEREAD FAS OR PROTRUSION SA NOT EXCEED 0. (0.0) PER SIDE. 5. DIMENSION K DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 0.0 (0.003) TOTA IN EXCESS OF TE K DIMENSION AT MAXIMUM MATERIA CONDITION.. TERMINA NUMBERS ARE SOWN FOR REFERENCE ONY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PANE W. MIIMETERS INCES DIM MIN MAX MIN MAX A B C D F G 0.5 BSC 0.02 BSC J J K K BSC 0.2 BSC M 0 0

12 MC74X051 SOEIAJ M SUFFIX CASE 9 01 ISSUE O e 9 1 Z b D A E A (0.005) M 0. (0.004) E IEW P M E Q 1 DETAI P c NOTES: 1. DIMENSIONING AND TOERANCING PER ANSI Y1M, CONTROING DIMENSION: MIIMETER. 3. DIMENSIONS D AND E DO NOT INCUDE MOD FAS OR PROTRUSIONS AND ARE MEASURED AT TE PARTING INE. MOD FAS OR PROTRUSIONS SA NOT EXCEED 0. (0.00) PER SIDE. 4. TERMINA NUMBERS ARE SOWN FOR REFERENCE ONY. 5. TE EAD WIDT DIMENSION (b) DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 0.0 (0.003) TOTA IN EXCESS OF TE EAD WIDT DIMENSION AT MAXIMUM MATERIA CONDITION. DAMBAR CANNOT BE OCATED ON TE OWER RADIUS OR TE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT EAD TO BE 0.4 ( 0.01). MIIMETERS INCES DIM MIN MAX MIN MAX A A b c D E e 1.27 BSC BSC E E M 0 0 Q Z ON Semiconductor and are registered trademarks of Semiconductor Components Industries, C (SCIC). SCIC reserves the right to make changes without further notice to any products herein. SCIC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCIC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCIC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCIC does not convey any license under its patent rights nor the rights of others. SCIC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCIC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCIC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCIC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCIC was negligent regarding the design or manufacture of the part. SCIC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBICATION ORDERING INFORMATION ITERATURE FUFIMENT: iterature Distribution Center for ON Semiconductor P.O. Box 1312, Phoenix, Arizona USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center Kamimeguro, Meguro ku, Tokyo, Japan Phone: ON Semiconductor Website: Order iterature: For additional information, please contact your local Sales Representative. MC74X051/D

MC74LVX8051. Analog Multiplexer/ Demultiplexer High Performance Silicon Gate CMOS

MC74LVX8051. Analog Multiplexer/ Demultiplexer High Performance Silicon Gate CMOS MC74X051 Analog Multiplexer/ Demultiplexer igh Performance Silicon Gate CMOS The MC74X051 utilizes silicon gate CMOS technology to achieve fast propagation delays, low ON resistances, and low leakage currents.