MC74LVXT8053. Analog Multiplexer / Demultiplexer. High Performance Silicon Gate CMOS
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1 MC74VXT053 Analog Multiplexer / Demultiplexer igh Performance Silicon Gate CMOS The MC74VXT053 utilizes silicon gate CMOS technology to achieve fast propagation delays, low ON resistances, and low leakage currents. This analog multiplexer/demultiplexer controls analog voltages that may vary across the complete power supply range (from to ). The VXT053 is similar in pinout to the high speed C4053A, and the metal gate MC14053B. The Channel Select inputs determine which one of the Analog Inputs/Outputs is to be connected by means of an analog switch to the Common Output/Input. When the Enable pin is IG, all analog switches are turned off. The Channel Select and Enable inputs are compatible with TT type input thresholds. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic level translator from V CMOS logic to 5.0 V CMOS ogic or from 1. V CMOS logic to V CMOS ogic while operating at the higher voltage power supply. The MC74VXT053 input structure provides protection when voltages up to 7.0 V are applied, regardless of the supply voltage. This allows the MC74VXT053 to be used to interface 5.0 V circuits to V circuits. This device has been designed so that the ON resistance (R on ) is more linear over input voltage than R on of metal gate CMOS analog switches. Features Fast Switching and Propagation Speeds ow Crosstalk Between Switches Diode Protection on All Inputs/Outputs Analog Power Supply Range ( ) = V to.0 V Digital (Control) Power Supply Range ( ) = V to.0 V Improved inearity and ower ON Resistance Than Metal Gate Counterparts ow Noise In Compliance With the Requirements of JEDEC Standard No. 7A Pb Free Packages are Available* SOIC D SUFFIX CASE 751B TSSOP DT SUFFIX CASE 94F SOEIAJ M SUFFIX CASE 9 MARKING DIAGRAMS A = Assembly ocation W or = Wafer ot Y = Year WW or W = Work Week ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. 1 1 VXT053 AWYWW 1 VXT 053 AYW VXT053 AYW *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SODERRM/D. Semiconductor Components Industries, C, 05 March, 05 Rev. 4 1 Publication Order Number: MC74VXT053/D
2 MC74VXT053 FUNCTION TABE MC74VXT053 Y X X1 X0 A B C Y1 Y0 Z1 Z Z0 Enable NC PIN CONNECTION AND MARKING DIAGRAM (Top View) Enable Control Inputs X = Don t Care Select C B A X X X Z0 Z0 Z0 Z0 Z1 Z1 Z1 Z1 ON Channels Y0 Y0 Y1 Y1 Y0 Y0 Y1 Y1 NONE X0 X1 X0 X1 X0 X1 X0 X1 X0 12 X1 13 X SWITC 14 X ANAOG INPUTS/OUTPUTS Y0 2 Y1 1 Y SWITC Y COMMON OUTPUTS/INPUTS Z0 5 Z1 3 A CANNE-SEECT B INPUTS C 9 ENABE Z SWITC 4 Z PIN = PIN = NOTE: This device allows independent control of each switch. Channel Select Input A controls the X Switch, Input B controls the Y Switch and Input C controls the Z Switch Figure 1. OGIC DIAGRAM Triple Single Pole, Double Position Plus Common Off ORDERING INFORMATION Device Package Shipping MC74VXT053DR2 SOIC 00 Tape & Reel MC74VXT053DR2G SOIC (Pb Free) 00 Tape & Reel MC74VXT053DTR2 TSSOP * 00 Tape & Reel MC74VXT053M SOEIAJ 50 Units / Rail MC74VXT0531MG SOEIAJ (Pb Free) 50 Units / Rail MC74VXT053ME SOEIAJ 00 Tape & Reel MC74VXT053MEG SOEIAJ (Pb Free) 00 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD0/D. *This package is inherently Pb Free. 2
3 MC74VXT053 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS SymbolÎÎÎÎÎÎÎÎÎÎÎÎÎ Parameter ÎÎÎÎÎÎ Value ÎÎÎ Unit ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ Positive DC Supply Voltage (Referenced to )ÎÎÎÎÎÎ 0.5 to ÎÎÎ V ÎÎÎÎ V IS ÎÎÎÎÎÎÎÎÎÎÎÎÎ Analog Input Voltage ÎÎÎÎÎÎ 0.5 to + 0.5ÎÎÎ V ÎÎÎÎ V in ÎÎÎÎÎÎÎÎÎÎÎÎÎ Digital Input Voltage (Referenced to ) ÎÎÎÎÎÎ 0.5 to + 0.5ÎÎÎ V ÎÎÎÎ I ÎÎÎÎÎÎÎÎÎÎÎÎÎ DC Current, Into or Out of Any Pin ÎÎÎÎÎÎ ÎÎÎ ma ÎÎÎÎ P D ÎÎÎÎÎÎÎÎÎÎÎÎÎ Power Dissipation in Still Air, SOIC Package ÎÎÎÎÎÎ 500 ÎÎÎ mw TSSOP Package 450 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ T ÎÎÎÎ stg ÎÎÎÎÎÎÎÎÎÎÎÎÎ Storage Temperature Range 5 to + 0 ÎÎÎÎÎÎÎÎ C T ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ead Temperature, 1 mm from Case for Seconds ÎÎÎÎÎÎÎÎ C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Derating SOIC Package: 7 mw/ C from 5 C to 1 C TSSOP Package:.1 mw/ C from 5 C to 1 C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. owever, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, V in and V out should be constrained to the range (V in or V out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. RECOMMENDED OPERATING CONDITIONS SymbolÎÎÎÎÎÎÎÎÎÎÎÎÎ Parameter ÎÎÎÎ Min MaxÎÎÎ Unit ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ Positive DC Supply Voltage (Referenced to )ÎÎÎÎ ÎÎÎ.0ÎÎÎ V ÎÎÎÎ V IS ÎÎÎÎÎÎÎÎÎÎÎÎÎ Analog Input Voltage ÎÎÎÎ 0.0 ÎÎÎ ÎÎÎ V ÎÎÎÎ V in ÎÎÎÎÎÎÎÎÎÎÎÎÎ Digital Input Voltage (Referenced to ) ÎÎÎÎ ÎÎÎ ÎÎÎ V ÎÎÎÎ V IO * ÎÎÎÎÎÎÎÎÎÎÎÎÎ Static or Dynamic Voltage Across Switch ÎÎÎÎÎÎ 1.2ÎÎÎ V ÎÎÎÎ T A ÎÎÎÎÎÎÎÎÎÎÎÎÎ Operating Temperature Range, All Package TypesÎÎÎÎ 55 ÎÎÎ + 5ÎÎÎ C ÎÎÎÎ t r, t f ÎÎÎÎÎÎÎÎÎÎÎÎÎ Input Rise/Fall Time ÎÎÎÎÎÎÎÎ ns/v (Channel Select or Enable Inputs) ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ = 3.3 V ± 0.3 V 0 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ = 5.0 V ± 0.5 ÎÎÎÎ V 0 ÎÎÎ 0 ÎÎÎ *For voltage drops across switch greater than 1.2 V (switch on), excessive current may be drawn; i.e., the current out of the switch may contain both and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. DC CARACTERISTICS Digital Section (Voltages Referenced to ) Symbol Parameter Condition V I V I I in Minimum igh evel Input Voltage, Channel Select or Enable Inputs Maximum ow evel Input Voltage, Channel Select or Enable Inputs Maximum Input eakage Current, Channel Select or Enable Inputs R on = Per Spec R on = Per Spec Guaranteed imit V 55 to C 5 C 1 C Unit V in = or, ± 0.1 ± 1.0 ± 1.0 A V V I CC Maximum Quiescent Supply Current (per Package) Channel Select, Enable and V IS = or ; V IO = 0 V A 3
4 MC74VXT053 DC EECTRICA CARACTERISTICS Analog Section ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Guaranteed imit ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ V ÎÎÎÎ ÎÎÎÎ CC ÎÎÎ ÎÎÎ Symbol Parameter Test Conditions V 55 to C 5 C 1 C Unit ÎÎÎÎ R on ÎÎÎÎÎÎÎÎÎÎ Maximum ON Resistance ÎÎÎÎÎÎÎÎÎ V in = V I or V I ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ V IS = to ÎÎÎ ÎÎÎÎ ÎÎÎÎ 32 ÎÎÎ ÎÎÎ I S.0 ma (Figures 1, 2) 2 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ V ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ in = V I or V I V IS = or (Endpoints) ÎÎÎ ÎÎÎÎ ÎÎÎÎ 2 ÎÎÎ 35 ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ I S.0 ma (Figures 1, 2) ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ R on ÎÎÎÎÎÎÎÎÎÎ Maximum Difference in ON V ÎÎÎÎÎÎÎÎÎ in = V I or V I Resistance Between Any Two V IS = 1/2 ( ÎÎÎÎÎÎÎÎÎÎÎÎÎ ).0 12 ÎÎÎÎÎÎÎÎÎÎÎÎÎ Channels in the Same Package ÎÎÎÎÎÎÎÎÎ I S.0 ma ÎÎÎ ÎÎÎÎ.0 ÎÎÎÎ 12 ÎÎÎ ÎÎÎ I off I on Maximum Off Channel eakage Current, Any One Channel Maximum Off Channel eakage Current, Common Channel Maximum On Channel eakage Current, Channel to Channel V in = V I or V I ; V IO = or ; Switch Off (Figure 3) V in = V I or V I ; V IO = or ; Switch Off (Figure 4) V in = V I or V I ; Switch to Switch = or ; (Figure 5) A A AC CARACTERISTICS (C = 50 pf, Input t r = t f = 3 ns) Symbol t P, t P t P, t P t PZ, t PZ t PZ, t PZ Parameter Maximum Propagation Delay, Channel Select to Analog Output (Figure 9) Maximum Propagation Delay, Analog Input to Analog Output (Figure ) Maximum Propagation Delay, Enable to Analog Output (Figure ) Maximum Propagation Delay, Enable to Analog Output (Figure ) Guaranteed imit V 55 to C 5 C 1 C Unit C in Maximum Input Capacitance, Channel Select or Enable Inputs pf C I/O Maximum Capacitance Analog I/O pf (All Switches Off) Common O/I Feedthrough ns ns ns ns C, = 5.0 V C PD Power Dissipation Capacitance (Figure 13)* 45 pf * Used to determine the no load dynamic power consumption: P D = C PD 2 f + I CC. 4
5 MC74VXT053 ADDITIONA APPICATION CARACTERISTICS ( = 0 V) Symbol Parameter Condition BW TD Maximum On Channel Bandwidth or Minimum i Frequency Response (Figure ) Off Channel Feedthrough Isolation (Figure 7) Feedthrough Noise. Channel Select Input to Common I/O (Figure ) Crosstalk Between Any Two Switches (Figure 12) Total armonic Distortion (Figure 14) *imits not tested. Determined by design and verified by qualification. f in = 1Mz Sine Wave; Adjust f in Voltage to Obtain 0dBm at V OS ; Increase f in Frequency Until db Meter Reads 3 db; R = 50, C = pf f in = Sine Wave; Adjust f in Voltage to Obtain 0 dbm at V IS f in = kz, R = 00, C = 50 pf f in = 1.0Mz, R = 50, C = pf V in 1Mz Square Wave (t r = t f = 3 ns); Adjust R at Setup so that I S = 0A; Enable = R = 00, C = 50pF R = k, C = pf f in = Sine Wave; Adjust f in Voltage to Obtain 0dBm at V IS f in = kz, R = 00, C = 50pF f in = 1.0Mz, R = 50, C = pf f in = 1kz, R = k, C = 50pF TD = TD measured TD source V IS = V PP sine wave V IS = 4.0V PP sine wave V IS = 5.0V PP sine wave imit* V C Unit Mz db mv PP db % 5
6 MC74VXT053 R on, ON RESISTANCE (OMS) C 5 C C 55 C V IN, INPUT VOTAGE (VOTS) Figure 1a. Typical On Resistance, = V 35 Ron, ON RESISTANCE (OMS) 5 1 C 5 C C 55 C Ron, ON RESISTANCE (OMS) 5 1 C 5 C C 55 C V IN, INPUT VOTAGE (VOTS) Figure 1b. Typical On Resistance, = V V IN, INPUT VOTAGE (VOTS) Figure 1c. Typical On Resistance, = V POTTER PROGRAMMABE POWER SUPPY MINI COMPUTER DC ANAYZER + DEVICE UNDER TEST ANAOG IN COMMON OUT Figure 1. On Resistance Test Set Up
7 MC74VXT053 A NC ANAOG I/O V I V I Figure 2. Maximum Off Channel eakage Current, Any One Channel, Test Set Up Figure 3. Maximum Off Channel eakage Current, Common Channel, Test Set Up A ON N/C f in 0.1 F ON V OS C * R db METER ANAOG I/O V I Figure 4. Maximum On Channel eakage Current, Channel to Channel, Test Set Up Figure 5. Maximum On Channel Bandwidth, Test Set Up f in 0.1 F V IS R V OS C * R db METER R ANAOG I/O R /ON R C * TEST POINT V I or V I CANNE SEECT V I V I V in 1 Mz t r = t f = 3 ns CANNE SEECT Figure. Off Channel Feedthrough Isolation, Test Set Up Figure 7. Feedthrough Noise, Channel Select to Common Out, Test Set Up 7
8 MC74VXT053 CANNE SEECT 50% ANAOG I/O /ON C * TEST POINT t P t P ANAOG OUT 50% CANNE SEECT Figure 9a. Propagation Delays, Channel Select to Analog Out Figure 9b. Propagation Delay, Test Set Up Channel Select to Analog Out ANAOG IN 50% ANAOG I/O ON C * TEST POINT t P t P ANAOG OUT 50% Figure a. Propagation Delays, Analog In to Analog Out Figure b. Propagation Delay, Test Set Up Analog In to Analog Out t f t r V 90% CC ENABE 50% % t PZ t PZ ANAOG OUT ANAOG OUT 50% 50% t PZ t PZ % 90% Figure a. Propagation Delays, Enable to Analog Out IG IMPEDANCE V O V O IG IMPEDANCE V I V I POSITION 1 WEN TESTING t PZ AND t PZ POSITION 2 WEN TESTING t PZ AND t PZ ANAOG I/O ENABE C * Figure b. Propagation Delay, Test Set Up Enable to Analog Out 1k TEST POINT
9 MC74VXT053 f in 0.1 F R V IS ON V OS ANAOG I/O /ON A NC R R C * R C * CANNE SEECT Figure 12. Crosstalk Between Any Two Switches, Test Set Up Figure 13. Power Dissipation Capacitance, Test Set Up V IS V OS 0.1 F TO f in ON DISTORTION R METER C * Figure 14a. Total armonic Distortion, Test Set Up db FUNDAMENTA FREQUENCY DEVICE SOURCE FREQUENCY (kz) Figure 14b. Plot, armonic Distortion APPICATIONS INFORMATION The Channel Select and Enable control pins should be at or logic levels. being recognized as a logic high and being recognized as a logic low. In this example: = +5V = logic high = 0V = logic low The maximum analog voltage swing is determined by the supply voltages. The positive peak analog voltage should not exceed. Similarly, the negative peak analog voltage should not go below. In this example, the difference between and is five volts. Therefore, using the configuration of Figure, a maximum analog signal of five volts peak to peak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not connected). owever, tying unused analog inputs and outputs to or through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch. Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that: = 2 to volts When voltage transients above and/or below are anticipated on the analog channels, external Germanium or Schottky diodes (D x ) are recommended as shown in Figure. These diodes should be able to absorb the maximum anticipated current surges during clipping. 9
10 MC74VXT053 +5V +5V 0V ANAOG SIGNA ON ANAOG SIGNA +5V 0V D x D x D x D x 9 TO EXTERNA STT COMPATIBE CIRCUITRY 0 to V I DIGITA SIGNAS Figure. Application Example Figure. External Germanium or Schottky Clipping Diodes +3V +5V +3V ANAOG SIGNA ANAOG SIGNA +3V +5V ANAOG SIGNA ANAOG SIGNA +5V V V CIRCUITRY V CIRCUITRY MC74VC1GT50 BUFFERS = V a. ow Voltage ogic evel Shifting Control b. 2 Stage ogic evel Shifting Control Figure 17. Interfacing ow Voltage CMOS Inputs A EVE SIFTER 13 X1 12 X0 14 X B EVE SIFTER 1 Y1 2 Y0 Y C 9 EVE SIFTER 3 Z1 5 Z0 4 Z ENABE EVE SIFTER Figure 1. Function Diagram, VXT053
11 MC74VXT053 PACKAGE DIMENSIONS SOIC D SUFFIX CASE 751B 05 ISSUE J A 9 1 B P P 0. (0.0) M B S NOTES: 1. DIMENSIONING AND TOERANCING PER ANSI Y1M, CONTROING DIMENSION: MIIMETER. 3. DIMENSIONS A AND B DO NOT INCUDE MOD PROTRUSION. 4. MAXIMUM MOD PROTRUSION 0. (0.00) PER SIDE. 5. DIMENSION D DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE (0.005) TOTA IN EXCESS OF TE D DIMENSION AT MAXIMUM MATERIA CONDITION. T SEATING PANE G K C D P 0. (0.0) M T B S A S M R X 45 J F MIIMETERS INCES DIM MIN MAX MIN MAX A B C D F G 1.27 BSC BSC J K M P R TSSOP DT SUFFIX CASE 94F 01 ISSUE A 0. (0.00) T 0. (0.00) T 0. (0.004) T SEATING PANE U PIN 1 IDENT. U D S S 2X /2 C X K REF 0. (0.004) M T U S V S 9 1 A V G B U N N J J1 F DETAI E DETAI E K K1 ÇÇÇ ÉÉÉ SECTION N N 0. (0.0) M W NOTES: 1. DIMENSIONING AND TOERANCING PER ANSI Y1M, CONTROING DIMENSION: MIIMETER. 3. DIMENSION A DOES NOT INCUDE MOD FAS. PROTRUSIONS OR GATE BURRS. MOD FAS OR GATE BURRS SA NOT EXCEED 0. (0.00) PER SIDE. 4. DIMENSION B DOES NOT INCUDE INTEREAD FAS OR PROTRUSION. INTEREAD FAS OR PROTRUSION SA NOT EXCEED 0. (0.0) PER SIDE. 5. DIMENSION K DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 0.0 (0.003) TOTA IN EXCESS OF TE K DIMENSION AT MAXIMUM MATERIA CONDITION.. TERMINA NUMBERS ARE SOWN FOR REFERENCE ONY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PANE W. MIIMETERS INCES DIM MIN MAX MIN MAX A B C D F G 0.5 BSC 0.02 BSC J J K K BSC 0.2 BSC M 0 0
12 MC74VXT053 SOEIAJ M SUFFIX CASE 9 01 ISSUE O e 9 1 Z b D A E A (0.005) M 0. (0.004) E VIEW P M E Q 1 DETAI P c NOTES: 1. DIMENSIONING AND TOERANCING PER ANSI Y1M, CONTROING DIMENSION: MIIMETER. 3. DIMENSIONS D AND E DO NOT INCUDE MOD FAS OR PROTRUSIONS AND ARE MEASURED AT TE PARTING INE. MOD FAS OR PROTRUSIONS SA NOT EXCEED 0. (0.00) PER SIDE. 4. TERMINA NUMBERS ARE SOWN FOR REFERENCE ONY. 5. TE EAD WIDT DIMENSION (b) DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 0.0 (0.003) TOTA IN EXCESS OF TE EAD WIDT DIMENSION AT MAXIMUM MATERIA CONDITION. DAMBAR CANNOT BE OCATED ON TE OWER RADIUS OR TE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT EAD TO BE 0.4 ( 0.01). MIIMETERS INCES DIM MIN MAX MIN MAX A A b c D E e 1.27 BSC BSC E E M 0 0 Q Z ON Semiconductor and are registered trademarks of Semiconductor Components Industries, C (SCIC). SCIC reserves the right to make changes without further notice to any products herein. SCIC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCIC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCIC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCIC does not convey any license under its patent rights nor the rights of others. SCIC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCIC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCIC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCIC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCIC was negligent regarding the design or manufacture of the part. SCIC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBICATION ORDERING INFORMATION ITERATURE FUFIMENT: iterature Distribution Center for ON Semiconductor P.O. Box 1312, Phoenix, Arizona USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center Kamimeguro, Meguro ku, Tokyo, Japan Phone: ON Semiconductor Website: Order iterature: For additional information, please contact your local Sales Representative. MC74VXT053/D
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