Electronics Revolution. ECE 410: VLSI Design Course Lecture Notes (Uyemura textbook) Figure 1.2 (p.4) General overview of the design heirarchy.

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1 ECE 410: VLSI Design Course Lecture Notes (Uemur tetook) Professor Fthi Slem Michign Stte Universit Spring 2010 Acknowledgement: These re sed on notes of Prof. Mson from previous semesters. This semseter, we will e updting them, s the need rises. ECE 410, Prof. F. Slem Lecture Notes Pge 2.1 Age of electronics microcontrollers, DSPs, nd other VLSI chips re everwhere Electronics of tod nd tomorrow higher performnce (speed) circuits low power circuits for portle pplictions more mied signl emphsis wireless hrdwre high performnce signl processing Sensors, ctutors, nd microsstems Electronics Revolution Digitl Cmer PDAs Cmcorder MP3/CD Pler Lptop Cell phone Nintendo Gmeo ECE 410, Prof. F. Slem Lecture Notes Pge 2.2 Figure 1.1 (p. 2) The VLSI design funnel. Figure 1.2 (p.4) Generl overview of the design heirrch. ECE 410, Prof. F. Slem Lecture Notes Pge 2.3 ECE 410, Prof. F. Slem Lecture Notes Pge 2.4 1

2 VLSI ver lrge scle integrtion lots of trnsistors integrted on single chip Top Down Design digitl minl coded design ECE 411 Bottom Up Design cell performnce Anlog/mied signl ECE 410 VLSI Design Procedure VLSI Design Flow Top Down Design Bottom Up Design Sstem Specifictions Astrct Highlevel Model VHDL, Verilog HDL Functionl Simultion Digitl Cell Lirr PostLout Simultion Prsitic Etrction LVS (lout vs. schemtic) DRC (design rule check) Phsicl Design Simultion Schemtic Design Functionl/Timing/ Performnce Specifictions Logic Snthesis Miedsignl Anlog Blocks Process Design Rules Process Models SPICE Chip Floorplnning Chiplevel Integrtion Mnufcturing Finished VLSI Chip Process Chrcteriztion Process Design Process Cpilities nd Requirements Integrted Circuit Technologies Wh does CMOS dominte? other technologies pssive circuits IIIV devices Silicon BJT CMOS domintes ecuse: Silicon is cheper preferred over other mterils phsics of CMOS is esier to understnd CMOS is esier to implement/fricte CMOS provides lower powerdel product CMOS is lowest power cn get more CMOS trnsistors/functions in sme chip re BUT! CMOS is not the fstest technolog! BJT nd IIIV devices re fster ECE 410, Prof. F. Slem Lecture Notes Pge 2.5 ECE 410, Prof. F. Slem Lecture Notes Pge 2.6 MOSFET Phsicl View Phsicl Structure of MOSFET Device Schemtic Smol for 4terminl MOSFET gte criticl dimension = feture size Vritions over time CMOS Technolog Trends # trnsistors / chip: incresing with time power / trnsistor: decresing with time (constnt power densit) device chnnel length: decresing with time power suppl voltge: decresing with time trnsistors / chip chnnel length Sustrte, ulk, well, or ck gte drin power / trnsistor suppl voltge Simplified Smols ref: Kuo nd Lou, LowVoltge CMOS VLSI Circuits, Fig. 1.3, p. 3 low power/voltge is criticl for future ICs ECE 410, Prof. F. Slem Lecture Notes Pge 2.7 ECE 410, Prof. F. Slem Lecture Notes Pge 2.8 2

3 In 1965, Gordon Moore relized there ws striking trend; ech new genertion of memor chip contined roughl twice s much cpcit s its predecessor, nd ech chip ws relesed within 1824 months of the previous chip. He resoned, computing power would rise eponentill over reltivel rief periods of time. Moore's oservtion, now known s Moore's Lw, descried trend tht hs continued nd is still remrkl ccurte. In 26 ers the numer of trnsistors on chip hs incresed more thn 3,200 times, from 2,300 on the 4004 in 1971 to 7.5 million on the Pentium II processor. Moore s Lw 2 Billion 10μm 1μm 0.35μm 45 nm Feture Size (ref: Power Suppl Tends Digitl Core Voltge Projections 1.8 V from the 2000 ITRS * 1.5 V 1.2 V 0.9 V 0.6 V 0.6 V Electronics Building lock(s) MOSFET Device 1950 to 2020 New elements in nno technologies re emerging include: Memristor: memor resistor see Dec IEEE Spectrum Nnotues Moleculr devices Quntum dots Etc. Yer Feture Size (nm) * ECE 410, Prof. F. Slem Lecture Notes Pge 2.9 ECE 410, Prof. F. Slem Lecture Notes Pge 2.10 VLSI ver lrge scle integrtion lots of trnsistors integrted on single chip Top Down Design digitl minl coded design ECE 411 Bottom Up Design cell performnce Anlog/mied signl ECE 410 VLSI Design Procedure VLSI Design Flow Top Down Design Bottom Up Design Sstem Specifictions Astrct Highlevel Model VHDL, Verilog HDL Functionl Simultion Digitl Cell Lirr PostLout Simultion Prsitic Etrction LVS (lout vs. schemtic) DRC (design rule check) Phsicl Design Simultion Schemtic Design Functionl/Timing/ Performnce Specifictions Logic Snthesis Miedsignl Anlog Blocks Process Design Rules Process Models SPICE Chip Floorplnning Chiplevel Integrtion Mnufcturing Finished VLSI Chip Process Chrcteriztion Process Design Process Cpilities nd Requirements ECE 410, Prof. F. Slem Lecture Notes Pge 2.11 Wht is MOSFET? Digitl integrted circuits rel on trnsistor switches most common device for digitl nd mied signl: MOSFET Definitions MOS = Metl Oide Semiconductor phsicl lers of the device Pol Oide E V gte insultor FET = Field Effect Trnsistor chnnel Wht field? Wht does the field do? Are other fields importnt? Semiconductor silicon sustrte CMOS = Complementr MOS use of oth nd to form circuit with lowest power consumption. Primr Fetures gte; gte oide (insultor) ver thin nd drin chnnel ulk/sustrte ECE 410, Prof. F. Slem Lecture Notes Pge 2.12 drin NOTE: Pol stnds for polsilicon in modern MOSFETs 3

4 Fundmentl Reltions in MOSFET Electric Fields V Q gte fundmentl eqution E insultor electric field: E = V/d verticl field through gte oide Q chnnel drin determines chrge induced in chnnel silicon sustrte horizontl field cross chnnel determines todrin current flow Cpcitnce fundmentl equtions cpcitor chrge: Q = CV W Topview cpcitnce: C = ε A/d L chrge lnce on cpcitor, Q = Q chrge on gte is lnced chrge in chnnel wht is the of chnnel chrge? where does it come from? CMOS Cross Section View Cross section of 2 metl, 1 pol CMOS process Tpicl MOSFET Device () Lout (top view) of the devices ove (prtil, simplified) ECE 410, Prof. F. Slem Lecture Notes Pge 2.13 ECE 410, Prof. F. Slem Lecture Notes Pge 2.14 CMOS = complementr MOS uses 2 tpes of MOSFETs to crete functions CMOS Power Suppl tpicll single power suppl, with Ground reference CMOS Circuit Bsics tpicll uses single power suppl rnges from (0.6V) 1V to 5V Logic Levels (voltgesed) ll voltges etween 0V nd Logic 1 = Logic 0 = ground = 0V gte drin V gte CMOS circuit drin ECE 410, Prof. F. Slem Lecture Notes Pge 2.15 = undefined 1 voltges 0 voltges CMOS circuit Trnsistor Switching Chrcteristics switching ehvior on = closed, when Vin > Vtn off = open, when Vin < Vtn switching ehvior on = closed, when Vin < Vtp off = open, when Vin > Vtp Digitl Behvior Vin Vout (drin) 1 Vs=0 device is ON 0? device is OFF Vin Vout (drin) 1? device is OFF 0 Vs==1 device is ON drin Vin gte Vgs Vsg Vin gte Vout Vin Vgs > Vtn = on Vtp off on on Vtn off Vsg > Vtp = on Vsg = Vin drin Vout Rule to Rememer is t lowest potentil for highest potentil for ECE 410, Prof. F. Slem Lecture Notes Pge

5 on when gte is high on when gte is low MOSFET Pss Chrcteristics Ech tpe of trnsistor is etter t pssing (to output) one digitl voltge thn the other psses good low (0) ut not good high (1) psses good high (1) ut not good low (0) Vgs=Vtn 0 V V = 0 V V = Vtn 0 V 0 V V = 0 V Vsg= Vtp V = Vtp Rule to Rememer is t lowest potentil () nd highest potentil () Psses good low M high is Vtn Psses good high Min low is Vtp ECE 410, Prof. F. Slem Lecture Notes Pge 2.17 MOSFET Terminl Voltges How do ou find one terminl voltge if other 2 re known? cse 1) if Vg > Vi Vtn, then Vo = Vi (VgVi > Vtn) Vo here Vi is the so the will pss Vi to Vo cse 2) if Vg < Vi Vtn, then Vo = VgVtn (VgVi < Vtn) Vg here Vo is the so the output is limited Vi Emple (Vtn=0.5V): Vg=5V, Vi=2V Vo = 2V Vg=2V, Vi=2V Vo = 1.5V For, m(vo) = VgVtn Vg cse 1) if Vg < Vi Vtp, then Vo = Vi (ViVg < Vtp ) Vi here Vi is the so the will pss Vi to Vo cse 2) if Vg > Vi Vtp, then Vo = Vg Vtp (ViVg > Vtp ) here Vo is the so the output is limited Emple (Vtp=0.5V): Vg=2V, Vi=5V Vo = 5V Vo Vg=2V, Vi=2V Vo = 2.5V For, min(vo) = Vg Vtp ECE 410, Prof. F. Slem Lecture Notes Pge 2.18 SwitchLevel Boolen Logic Logic gtes re creted using sets of controlled switches Chrcteristics of n sserthigh switch =? cts like n sserthigh switch SwitchLevel Boolen Logic Chrcteristics of n ssertlow switch = = A, i.e. = if A = 0 =? error in figure 2.5 cts like n ssertlow switch = A, i.e. = iff A = 1 (iff=if nd onl if) Series ssertlow switches? NOT function, comining sserthigh nd ssertlow switches Series switches AND function Prllel switches OR function NOR Rememer This?? =, = DeMorgn reltions =1 SW1 closed, SW2 open =0 = =0 SW1 open, SW2 closed =1 = ECE 410, Prof. F. Slem Lecture Notes Pge 2.19 ECE 410, Prof. F. Slem Lecture Notes Pge

6 CMOS PushPull Logic CMOS PushPull Networks on when input is low pushes output high on when input is high pulls output low onl one network (p or n) is required to produce the function ut the complementr set llows the lod to e turned off for zero sttic power dissiption inputs ssertlow sserthigh output VSS = ground ECE 410, Prof. F. Slem Lecture Notes Pge 2.21 Review: Bsic Trnsistor Opertion CMOS Circuit Bsics inputs ssertlow sserthigh Vsg Vin gte output drin drin Vin gte Vgs Vsg > Vtp = on Vsg = Vin Vgs > Vtn = on CMOS Pss Chrcteristics is t lowest potentil () nd highest potentil () Vgs=Vtn 0 V = V = 0 V V Vtn 0 V 0 V 0 V Vsg= Vtp V = V = Vtp Vg= Vin Vout 0 1 on = closed 1? off = open Vg= Vin Vout 0? off = open 1 0 on = closed Vin Vtp Vtn 0 in = 0 out in = Vtn out strong 0, wek 1 in = out 0 in = Vtp out strong 1, wek 0 ECE 410, Prof. F. Slem Lecture Notes Pge 2.22 on off off on Review: SwitchLevel Boolen Logic sserthigh switch = A, i.e. = iff A = 1 series = AND prllel = OR ssertlow switch = A, i.e. = if A = 0 = series = NOR prllel = NAND ECE 410, Prof. F. Slem Lecture Notes Pge 2.23 Creting Logic Gtes in CMOS All stndrd Boolen functions (INV, NAND, OR, etc.) cn e produced in CMOS pushpull circuits. Rules for constructing gtes using CMOS use complementr / pir for ech input connect the output to through ts connect the output to ground through ts insure the output is lws either high or low inputs CMOS produces inverting CMOS gtes re sed on the inverter outputs re lws inverted functions e.g., NOR, NAND rther thn OR, AND Logic Properties DeMorgn s Rules ( ) = ( ) = ssertlow sserthigh output Useful Logic Properties 1 = 1 0 = 1 = 0 = 0 Properties which cn e proven = 1 = 0 ()(c) = c = = ' = c = (c) ECE 410, Prof. F. Slem Lecture Notes Pge

7 CMOS Inverter Inverter Function toggle inr of signl Inverter Switch Opertion = input low output high off/open on/closed on output high (1) Vin= input high output low on/closed off/open on output low (0) Inverter Smol Inverter Truth Tle Vin Vsg Vgs Vout = Vin ECE 410, Prof. F. Slem Lecture Notes Pge = 1 0 CMOS Inverter Schemtic Logic Gtes Stud first, more simple thn CMOS Logic ssume resistive lod to switches pull output low sed on inputs Inverter NOR c = prllel switches = OR function pulls low (NOTs the output) () is off output is high (1) () is on output is low (0) NAND c = series switches = AND function pulls low (NOTs the output) ECE 410, Prof. F. Slem Lecture Notes Pge 2.26 NOR Smol Krnugh mp CMOS NOR Gte NOR Truth Tle g(,) = construct Sum of Products eqution with ll terms ech term represents MOSFET pth to the output 1 terms re connected to vi 0 terms re connected to ground vi CMOS NOR Schemtic CMOS NOR Gte g(,) = g(,) = output is LOW if OR is true prllel output is HIGH when AND re flse series Importnt Points seriesprllel rrngement when in series, in prllel, nd vis vers true for ll CMOS gtes llows us to construct more comple functions ECE 410, Prof. F. Slem Lecture Notes Pge 2.27 ECE 410, Prof. F. Slem Lecture Notes Pge

8 CMOS NAND Gte Truth Tle NAND Smol CMOS Schemtic g(,) = Kmp g(,) = ( 1) ( 1) ( 1) ( 0) = output is LOW if AND re true series output is HIGH when OR is flse prllel z NOR3 z NAND3 z z z g(,) = z 3Input Gtes Alternte Schemtic wht function? z g(,) = z z note shred gte inputs is input order importnt? in series, prllel, oth? schemtic resemles how the circuit will look in phsicl lout ECE 410, Prof. F. Slem Lecture Notes Pge 2.29 ECE 410, Prof. F. Slem Lecture Notes Pge 2.30 Review: CMOS NAND/NOR Gtes NOR Schemtic NAND Schemtic Comple Comintionl Logic Generl functions for emple f = ( c), f = (d e) ( c) g(,) = g(,) = How do we construct the CMOS gte? use DeMorgn principles to modif epression construct nd networks = = output is LOW if OR is true prllel output is HIGH when AND re flse series output is LOW if AND re true series output is HIGH when OR is flse prllel use Structured Logic AOI (AND OR INV) OAI (OR AND INV) ECE 410, Prof. F. Slem Lecture Notes Pge 2.31 ECE 410, Prof. F. Slem Lecture Notes Pge

9 Using DeMorgn DeMorgn Reltions NANDOR rule = ule pushing illustrtion equivlent to ules = inversions NORAND rule = equivlent to to implement this w, must push ll ules to the inputs nd remove ll NAND/NOR output ules nd ule pushing Prllelconnected g(,) = = ssertlow OR cretes NAND function Seriesconnected g(,) = = ssertlow AND cretes NOR function ECE 410, Prof. F. Slem Lecture Notes Pge 2.33 Rules for Constructing CMOS Gtes The Mthemticl Method Given function F = f(,, c) Reduce (using DeMorgn) to eliminte inverted opertions inverted vriles re OK, ut not opertions (NAND, NOR) Form network complementing the inputs Fp = f(,, c) Form the network complementing the output Fn = f(,, c) = F Construct Fn nd Fp using AND/OR series/prllel MOSFET structures series = AND, prllel = OR EXAMPLE: F = Fp = = ; Fn = = ; OR/prllel AND/series ECE 410, Prof. F. Slem Lecture Notes Pge 2.34 g(,) = CMOS Comintionl Logic Emple Construct CMOS gte to implement the function: F = ( c) Appl DeMorgn epnsions F = ( c) F = ( c ) Invert inputs for Fp = ( c) Resulting Schemtic c F=(c) c 6 trnsistors (CMOS) c c F=(c) F 14 trnsistors (cscded gtes) Invert output for Fn = ( c) Appl DeMorgn none needed Resulting Schemtic F=(c) c ECE 410, Prof. F. Slem Lecture Notes Pge 2.35 Structured Logic Recll CMOS is inherentl Inverting Cn use structured circuits to implement generl functions AOI: implements function in the order AND, OR, NOT (Invert) Emple: F = c d opertion order: i) AND, c AND d, ii) () OR (cd), iii) NOT Inverted SumofProducts (SOP) form OAI: implements function in the order OR, AND, NOT (Invert) Emple: G = () (zw) opertion order: i) OR, z OR w, ii) () AND (zw), iii) NOT Inverted ProductofSums (POS) form Use structured CMOS rr to relize such functions ECE 410, Prof. F. Slem Lecture Notes Pge

10 AOI/OAI Circuits AOI structure F = c d series ts in prllel AOI structure AOI/OAI Circuits series of prllel ts opposite of (series/prllel) OAI structure series ts in prllel opposite of (series/prllel) OAI structure series of prllel ts F = ( e) ( f) e X X Complete CMOS AOI/OAI circuits error in tetook Figure 2.45 ECE 410, Prof. F. Slem Lecture Notes Pge 2.37 ECE 410, Prof. F. Slem Lecture Notes Pge 2.38 Implementing Logic in CMOS Reducing Logic Functions fewest opertions fewest ts minimized function to eliminte ts Emple: z v = ( z v) 5 opertions: 3 AND, 2 OR 3 opertions: 1 AND, 2 OR # ts = # ts = Suggested pproch to implement CMOS function crete network invert output reduce function, use DeMorgn to eliminte NANDs/NORs implement using series for AND nd prllel for OR crete network complement ech opertion in network i.e. mke prllel into series nd vis vers ECE 410, Prof. F. Slem Lecture Notes Pge 2.39 CMOS Logic Emple Construct the function elow in CMOS F = (c d); rememer AND opertions occur efore OR Group 2: c & d in prllel Group 1: in series with G1 Group 3: prllel to G2 Group 2: c & d in series Group 1: prllel to G1 Group 3: in series with G2 Circuit hs n OAOI orgniztion (AOI with etr OR) ECE 410, Prof. F. Slem Lecture Notes Pge

11 Another Comintionl Logic Emple Construct CMOS gte which implements the function: F = ( c) Appl DeMorgn epnsions none needed Invert inputs for Fp = ( c) Resulting Schemtic? Invert output for Fn = ( c) Appl DeMorgn Fn = (c ) Fn = ( c) Resulting Schemtic? Yet Another Comintionl Logic Emple Implement the function elow constructing the network nd complementing opertions for the : F = ( c) Invert Output c Fn = ( c) = ( c) Eliminte NANDs nd NORs F= (c) Fn = ( c) Reduce Function Fn = ( c) Resulting Schemtic? Complement opertions for Fp = ( c) c ECE 410, Prof. F. Slem Lecture Notes Pge 2.41 ECE 410, Prof. F. Slem Lecture Notes Pge 2.42 EclusiveOR (XOR) = not AOI form XOR nd XNOR XOR nd XNOR AOI Schemtic EclusiveNOR = inverse of XOR XOR/XNOR in AOI form XOR: =, formed complementing XNOR ove XNOR: =,formed complementing XOR thus, interchnging nd (or nd ) converts from XOR to XNOR ECE 410, Prof. F. Slem Lecture Notes Pge 2.43 note: see tetook, figure 2.57 XOR: = XNOR: = ECE 410, Prof. F. Slem Lecture Notes Pge

12 Function CMOS Trnsmission Gtes recll: psses good 1 nd psses good 0 gted switch, cple of pssing oth 1 nd 0 Formed prllel nd t Trnsmission Gte Logic Functions TG circuits used etensivel in CMOS good switch, cn pss full rnge of voltge (ground) 2to1 MUX using TGs F = Po s P1 s schemtic smol Controlled gte select signls, s nd s if s = 1, =, switch is closed, ts re on if s = 0, = unknown (high impednce), switch open, ts off = s, for s=1 ECE 410, Prof. F. Slem Lecture Notes Pge 2.45 ECE 410, Prof. F. Slem Lecture Notes Pge 2.46 More TG Functions TG XOR nd XNOR Gtes =, = 1 = =, = 1 = =, = 1 =, = 1 Using TGs insted of sttic CMOS TG OR gte =, = 1 =, = 1 f = f = ECE 410, Prof. F. Slem Lecture Notes Pge