Computing Logic-Stage Delays Using Circuit Simulation and Symbolic Elmore Analysis

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1 Computing Logic-Stge Delys Using Circuit Simultion nd Symolic Elmore Anlysis Clyton B. McDonld Rndl E. Brynt Deprtment of Electricl nd Computer Engineering Crnegie Mellon University, Pittsurgh, PA ABSTRACT The computtion of logic-stge delys is fundmentl su-prolem for mny EDA tsks. Although ccurte delys cn e otined vi circuit simultion, we must estimte the input ssignments tht will mximize the dely. With conventionl methods, it is not fesile to estimte the dely for ll input ssignments on lrge su-networks, so previous pproches hve relied on heuristics. We present symolic lgorithm tht enles efficient computtion of the Elmore dely under ll input ssignments nd dely refinement using circuit-simultion. We nlyze the Elmore estimte with three metrics using dt extrcted from symolic timing simultions of industril circuits. 1. INTRODUCTION The computtion of logic-stge delys in trnsistor networks is fundmentl su-prolem for numer of electronic design utomtion tsks. Exmples include sttic timing nlysis, timing simultion, trnsistor-sizing optimiztion, nd lirry cell chrcteriztion. Determintion of the sensitizing conditions for the mximum nd minimum stge delys is extremely difficult in generl, nd exct solutions my e impossile for lrge networks. Typiclly, stge delys re computed on chnnel-connected regions (CCRs), consisting of ll nodes nd trnsistors rechle from ech other through trnsistor drin-source (chnnel) connections. Given prticulr input trnsition or simultneous set of trnsitions, we wish to determine the dely to the resulting trnsition on designted output node. This dely vlue is generlly dependent on the sttes of other inputs to the stge, s well s the initil conditions of the internl nodes. For exmple, Figure 1 shows dynmic stge where the dely from rising to pc flling is dependent on the vlues of, c, nd x1. Inputs nd c control the conductnce of the dischrge pth, while the initil stte of x1 ffects the mount of chrge tht must e removed. Determining the sensitizing conditions for the minimum or mximum dely is further complicted y potentil logicl reltionships etween the inputs. This reserch ws supported y the SRC (contrct DC-068) Permission to mke digitl or hrd copies of ll or prt of this work for personl or clssroom use is grnted without fee provided tht copies re not mde or distriuted for profit or commercil dvntge nd tht copies er this notice nd the full cittion on the first pge. To copy otherwise, to repulish, to post on servers or to redistriute to lists, requires prior specific permission nd/or fee. DAC 2001, June 18-22, 2001, Ls Vegs, Nevd, USA. Copyright 2001 ACM /01/ $5.00. CK / c 0 pc \ x1 Figure 1: Effects of Side-Conditions on Dely Previously pulished pproches hve used comintion of forml methods nd heuristics. Desi nd Yen [8] implemented lgorithms for sensitizing the mximum dely on specified pth through multi-ccr trnsistor-level network, which they decomposed into sensitizing series of mximum delys through single CCRs. Their method utilizes Boolen functions (stored s Binry Decision Digrms, or BDDs) to compute the set of input ssignments tht enle the desired input to output trnsition. For smll CCRs, they dvocte explicit enumertion of these input ssignments to determine which sensitizes the lrgest dely. For lrge CCRs, they first determine the mximum-resistnce driving pth, nd then use greedy lgorithm tht ttempts to select the ssignment which mximizes the cpcitnce connected to the output node. This pproch ssumes tht the ssignment tht mximizes the Elmore dely will mximize the true dely, n ssumption tht is chllenged y our dt (Section 3). Furthermore, mximizing the resistnce efore considering cpcitnces my not even led to mximl Elmore dely, s there might e n ssignment which sensitizes low-resistnce, high-cpcitnce driving pth with lrger RC product. Burks nd Min s pproch [5] is quite similr, though they primrily focused on incorporting logicl dependencies etween inputs. To select the worst-cse input ssignment, they sy only tht they use heuristic method. Our pproch lso uses the Elmore dely s n estimte of the true dely. However, using symolic techniques, we cn exploit the regulrity of lrge CCRs nd compute the Elmore dely exctly for ll input ssignments while voiding exponentil lowup for ll ut the most pthologicl cses. The primry enler for our methodology is the Multi-Terminl Binry Decision Digrm (MTBDD) dt structure [2]. Using MTBDDs, we compute the Elmore dely for ll possile input ssignments. We cn then select one ssignment for ech possile dely cse, nd use it s stimulus for SPICE-like simultion. Section 2 discusses the computtion of the symolic Elmore dely nd its refinement to high-ccurcy dely vlues with SPICE-

2 =1 x2 F / c=0 x2 out x1 τ out x1 Figure 2: Elmore Approximtion for Logic Stge + - F Figure 3: Exmple MTBDD + G H like simultor. We then present error-chrcteriztion dt in Section 3, drwn from test-runs of our symolic timing simultor on industril circuit designs STAGE-DELAY CALCULATION 2.1 Elmore Estimte Since our pproch is sed on the Elmore estimte of logicstge s dely, we will first present quick review. The Elmore dely is n estimte of the dominnt time constnt of the step-response of n RC tree. As result, it hs een hevily utilized for estimting delys in interconnect networks. However, numer of reserchers hve dpted it to otin dely estimtes of single stges of MOSFET circuits [11, 6]. This is ccomplished y removing non-conducting (OFF) trnsistors nd replcing conducting (ON) trnsistors with simple liner resistors. At ech internl node we compute single grounded cpcitnce vlue, nd then heuristiclly rek loops of conducting trnsistors to complete the RC tree. This conversion process is depicted in Figure 2. Besides the oviously risky pproximtion of trnsistors y liner resistnces, the Elmore estimte hs severl deficiencies when used for logic stges. First, it ssumes tht the inputs switch instntneously t time zero. To incorporte the effects of non-zero rise/fll times, we cn effectively modify the resistnce representing the turning-on trnsistor to reflect its reduced drive-cpcity or clculte n empiricl penlty to e dded onto the finl dely estimte. The second mjor ssumption is tht of single driving voltge source. This cn e significnt difficulty in nlyzing stges where multiple pulldown pths cn e ctivted simultneously, or for rtioed circuits where pullup nd pulldown pths re fighting ech other. Agin, empiricl pproximtions cn e mde to incorporte these effects, s ws done y Chu[6]. Since our symolic Elmore nlysis procedure is sed on Chu s, it implements these enhncements. 2.2 MTBDDs Previously pulished pproches to stge-dely computtion hve utilized symolic techniques to hndle logicl restrictions on input ptterns with considerle success. However, they hve hd to resort to heuristic methods for representing rel-vlued functions, such s resistnce, cpcitnce nd dely. The primry enler for our pproch, nd the key to extending symolic techniques to this rel-vlued domin, is the Multi-Terminl Binry Decision Digrm (MTBDD) [2]. MTBDDs re generliztions of BDDs tht llow n ritrry numer of rel-vlued terminls. For exmple, the MTBDD in Figure 3 represents the function F hving two inputs nd. To de- Figure 4: Exmple MTBDD Opertion termine the return vlue for ny given input ssignment, we work downwrds from the root, following the solid rc from nodes ssigned 1 nd the dshed rcs from nodes ssigned 0. We cn see tht F 2:5 when either or is 1, nd F 1:2 otherwise. Computtion on MTBDDs cn e ccomplished using the function MtddApply, which is virtully identicl to the well-known BDD Apply function[3]. It tkes s rguments n opertor nd two opernds, nd returns n MTBDD representing the result for ll input ssignments. For exmple, Figure 4 shows two input MTB- DDs F nd G, nd the MTBDD tht would result from computing MtddApply(+,F,G). MtddApply hs worst-cse complexity O(jFj jgj), where jfj represents the numer of terminls in MTBDD F. Using MtddApply, we cn perform ny lgeric opertions necessry to compute series nd prllel resistnces, RC products, nd other quntities needed for our nlysis. For exmple, since Elmore delys in digitl networks re computed y replcing trnsistors with switched resistors, we cn represent its symolic resistnce y n MTBDD which returns infinity where the trnsistor is off, nd its equivlent conducting resistnce when it is on (Figure 5). Then, using MtddApply clls, we cn compute ritrry prllel nd series comintions of these symolic resistors s shown in Figure 6. Throughout this pper, we will denote BDDs nd MTBDDs in oldfce (i.e. F), while sclr vlues will pper in norml type. We will lso often utilize infix nottion rther thn explicit clls to MtddApply, such tht F + G MtddApply(+; F; G). In some cses it will e convenient to specify trivil MTBDDs, consisting only of single terminl node, in rckets (i.e. [1:5]). 5/1 3.2K Figure 5: Representing FETs inf R 3.2

3 ck 5/1 5/1 c d inf Figure 6: Symolic FET Anlysis 1ns Inf. ck R c c c d d d d.8ns.4ns.27ns Figure 7: Exmple T dely for dynmic NOR.2ns 2.3 Symolic Elmore Anlysis The core of our symolic Elmore nlysis procedure is the pir of functions SymolicComputeDC nd SymolicComputeDely, which re descried in detil in [9]. Given chnnel-connected trnsistor network (CCR) whose input nd internl node-vlues hve een set to pproprite Boolen functions, SymolicComputeDC(z) returns BDD representing the function to which node z will settle. SymolicComputeDely(z,f) returns n MTBDD representing the time required for node z to settle to function f. Both functions strt from the output node nd recur through chnnel connections until they rech power or ground. They then perform series nd prllel computtions s they return from the recursion, using symolic lger s outlined ove. SymolicComputeDC uses voltge-divider or chrge-shring eqution to compute n MTBDD representing the stedy-stte voltge t the output node under ny input ssignment. This voltge vlue is thresholded to otin Boolen function for the output node. In similr fshion, SymolicComputeDely computes symolic resistnce nd cpcitnce MTBDDs tht re comined to otin the symolic Elmore dely MTBDD, T dely. Our procedure for computing the DC vlue of CCR is more generl thn tht presented y Desi [8], since it hndles the intermedite voltge levels generted y rtioed logic, nd differentites utomticlly etween the drive strengths of logic trnsistors nd wek holders. If this generlity is not required, purely BDDsed pproch such s Desi s my e sustituted. Alterntively, the multi-strength pproch used y COSMOS [4] hs lso een shown to work well for most digitl circuits. Since ll computtions re performed symoliclly using MTB- DDs nd symolic lger, the finl dely MTBDD T dely encodes the correct Elmore dely under ll input ssignments. In generl, T dely cn e of exponentil size with respect to the numer of inputs to the CCR. Typiclly, the CCRs eing nlyzed re quite smll nd this exponentil possiility is not concern. Fortuntely, lrger CCRs tend to contin regulrities tht cn e cptured y sugrph shring in the MTBDD dt structure. Figure 7 shows 1 Refine( Network N, T dely ) 2 T rened [1] 3 while (T dely 6= [1]) 4 d min MtddMinTerminl(T dely ) 5 Equl MtddEqul(T dely ; d min) 6 cue GetRndomCue(Equl) 7 8 nodes n 2 N 8 n:v Evlute(n:vlue; cue) 9 d refined TETA(N ) 10 T rened MtddITE(Equl; [d refined ] ; T rened ) 11 T dely MtddITE(Equl; [1] ; T dely ) 12 return T rened Figure 8: Dely Refinement the T dely tht results from computing the symolic Elmore dely of wide dynmic NOR gte. We see tht we only need one terminl for ech numer of pulldowns tht cn e on simultneously, nd tht there re lrge numer of reconverging pths in the MTBDD. Thus for circuits of this type, the dely MTBDD will only e of qudrtic size, rther thn exponentil. In our experience, pthologicl cses re extremely rre. In fct, we firly esily constructed the dely MTBDD for 64-it rrel-shifter contining more thn 8000 trnsistors in single CCR. 2.4 Refining the Dely Vlues As the results in Section 3 will demonstrte, the Elmore dely is firly poor estimte of the stge dely. However, we hve found it to e quite effective t seprting input ptterns into equivlent dely clsses. Bsed on this oservtion, we hve implemented methodology tht refines the symolic Elmore dely y selecting sensitizing input ssignment from ech dely clss nd recomputing the dely using SPICE-like circuit simultor. In this wy, the symolic Elmore dely ecomes heuristic pre-processing routine for selecting input ssignments. The circuit simultor we hve een working with is TETA [1, 7], from Crnegie Mellon. It is essentilly fst, cllle circuit simultor with ccurcy comprle to SPICE. By using successive chord integrtion method nd tle-lookup model for I ds currents, TETA cn re-use expensive LU fctoriztion results cross multiple timesteps nd input stimuli. Thus, it is idelly suited to quickly evluting sets of delys on single network under multiple input ssignments. The lgorithm for refining the symolic Elmore dely MTBDD is shown in Figure 8. For ech terminl of the dely MTBDD, we select sensitizing ssignment, evlute the node vlues under tht ssignment, nd compute the dely using TETA. The refined dely MTBDD is constructed with series of MtddITE opertions, nd we terminte once we hve refined ech terminl of the Elmore MTBDD. This lgorithm is perhps deceptively simple, nd we discovered numer of difficulties in implementing it in prctice. We re effectively performing mixed-mode logic nd circuit simultion, where the conversion etween the two modes is performed t ech CCR oundry. Since logic nd circuit simultion operte t such widely seprted levels of strction, there re ound to e sustntil mismtches in results. While we found tht the vst mjority of CCR nlyses completed flwlessly, significnt specil csing code ws required to hndle conflicts. Among other things, we were forced to hndle mismtching DC vlues, especilly those due to ggressively rtioed logic or chrge-shring glitches. In d-

4 1 MinMxTrnsitionDely( Network N, hin; out; in 0; out 0; Ri ) 2 out:vlue out inputs i 2 N 4 i:vlue oolen vrile x i 5 in:vlue in 0 6 f 0 ComputeDC(out) 7 in:vlue in 0 8 f 1 ComputeDC(out) 9 S f 0 f 1 10 T R ^ S inputs i 2 N 13 i:vlue i:vlue T internl nodes n 2 N 16 n:vlue out 0 17 M SymolicComputeDely(out; out 0) 18 MinDely MtddMinT erminl(m ) internl nodes n 6= out 2 N 21 n:vlue out 0 22 M SymolicComputeDely(out; out 0) 23 MxDely MtddMxT erminl(m ) returnhmindely; MxDelyi Figure 9: Min/Mx Stge Dely Computtion dition, circuit ehvior ignored y the Elmore pproximtion (Section 3.4) lso resulted in refined dely vlues tht were negtive, or trnsitions tht occur outside the expected simultion time-window. Since our initil ppliction is in symolic simultion environment, we chose to e conservtive y utilizing X s wherever necessry to cover the uncertinties. However, this specil-csing code will e highly dependent on the needs of the ppliction in which this dely-clcultion scheme is emedded. 2.5 Applictions Armed with these tools, we cn perform stge-dely clcultion for numer of pplictions. Ech ppliction will primrily differ in the mnner of initilizing the input nd internl nodes. In this section we discuss how to pply these routines to symolic timing simultion nd to sttic timing nlysis Sttic Timing Anlysis For sttic timing nlysis, pth trcing will identify trnsition for which we need to clculte the minimum nd mximum dely. We will ssume tht trnsition is specified s the following tuple: T = hin; out; in 0; out 0; Ri in = input node out = output node in 0 = initil vlue of input node 2 0; 1 out 0 = initil vlue of output node 2 0; 1 R = logicl restriction function For exmple, T = h; z; 0; 1; ci would represent the trnsition from rising input node to flling output node z, ssuming tht side inputs nd c re mutully exclusive. The sttic timing nlysis stge-dely lgorithm is shown in Figure 9. To determine the setup conditions which enle trnsition of this form, we first compute the DC vlues tht result from the initil nd finl input stimuli. These re comined to determine the conditions S under which the output node will switch s desired. The switching constrint S is ANDed with the logicl restriction function R to otin the finl trnsition condition T. Lstly, the inverse of T is XORed with ll input node vlues to constrin the cceptle input ptterns. For mx dely clcultion, we initilize ll internl nodes to the output initil vlue, nd cll SymolicComputeDely. The resultnt MTBDD contins the dely under ech input ssignment, so we need only select the mximum terminl vlue. For min dely clcultion, we initilize ll internl nodes to the output finl vlue, cll SymolicComputeDely gin, nd select the minimum terminl Symolic Timing Simultion For symolic timing simultion (STS), we require the full generlity of these two routines. This is not surprising, since STS ws the originl motivtion ehind the development of our pproch. Since symolic timing simultion is event-driven, we repetedly select n event from the event queue, updte node stte ccordingly nd compute the resultnt effects. In this wy, input nd internl node stte initiliztion is tken cre of y the event-driven simultion engine. After ech event, we merely cll SymolicComputeDC to determine output nd internl node DC vlues, nd SymolicComputeDely to otin the symolic delys. These delys re then scheduled s new events ccording to the lgorithms in [10]. 3. RESULTS We hve implemented this methodology in the symolic timing simultor STEED [10], nd run it on numer of sustntil testcses. As result, we hve collected lrge numer of dt points over wide rnge of circuit types, including sttic, domino, DCVSL, pss-gte logic, nd some izrre custom topologies. We generted some of the test cses ourselves, ut the mjority were supplied y the Compq Alph microprocessor design tem. The TETA device models re for 0.18um ST-Microelectronics process. In ccordnce with the potentil pplictions of this methodology, we hve collected dt with respect to three performnce metrics. These metrics mesure the Elmore dely s solute ccurcy, its ility to detect the min/mx dely cses, nd its clssifiction of delys into equivlence clsses. In ll three cses, the TETA dely vlues re ssumed to give the true delys, while the Elmore dely is considered to e n pproximtion. 3.1 Asolute Accurcy In terms of solute ccurcy, the Elmore dely does not perform prticulrly well. Figure 10 shows the percentge errors in Elmore delys vs TETA-sed delys, over pproximtely simultion cses. Only 50% of ll Elmore dely vlues were within 50% of the TETA-sed vlue. These inccurcies re wht we would otin y simply utilizing the Elmore estimte s our dely vlue, without pplying refinement scheme sed on more ccurte model. 3.2 Differentition The second performnce metric we mesured is differentition. Here we re ttempting to determine how well the Elmore dely groups different input ssignments into equivlence clsses. We mesured this y generting two dditionl rndom input ssignments within ech equivlence clss, nd simulting them in TETA.

5 1 Error in Elmore Prediction for Mx Dely Cse Cumultive Percentge of Cses Error in Elmore Dely vs. Tet Dely Cumultive Percentge of Cses Percent Error Figure 12: Errors From Mximizing Elmore Dely Cumultive Percentge of Cses Percent Error Figure 10: Elmore Dely Accurcy Error Within Elmore Equivlence Clsses Percent Error Figure 11: Spred Within Elmore Equivlence Clsses The dditionl dt points were compred with the one selected y our lgorithm, nd the percentge error ws computed. Figure 11 shows cumultive plot of these errors. Approximtely 97% of the the dditionl dt points otined the sme dely vlue s the originl representtives of their equivlence clsses, nd 99% were within 20%. This metric demonstrtes the errors tht cn e expected when pplying our pproch. For the vst mjority of cses, the Elmore estimte ppers to correctly prtition the input ssignments into equivlence clsses. While there remin circuit effects tht re not ccounted for y the Elmore estimte (see Section 3.4), they re reltively rre nd the frequency of their ssocited errors tend to drop off quickly s their mgnitudes increse. 3.3 Min/Mx Selection The finl metric is min/mx selection, which we mesured y compring the true mximum dely over ll input ssignments with the refined vlue of the mximum Elmore dely. This reflects the wy in which the Elmore dely is used to identify the mximum dely cse in previously pulished techniques. Figure 12 shows the reltive error due to ssuming the mximum Elmore dely cse will yield the mximum true dely. Only in out 74% of the cses did the mximum Elmore dely cse give the true mximum. Furthermore, in nerly 10% of the cses, the mximum Elmore dely cse produced dely with more thn 50% error reltive to the true mximum. This metric highlights the errors ssocited with previously pulished pproches, which ttempt to mximize the Elmore estimte nd then refine tht cse lone. Since the solute ccurcy of the Elmore estimte is so poor, it is not surprising tht we would incur errors y ssuming the mximum Elmore dely will led to the mximum true dely. 3.4 Limittions of the Elmore Estimte The previous section gives some quntittive informtion on the potentil inccurcies ssocited with using the Elmore estimte. Since lrge mounts of informtion re lost in constructing the Elmore equivlent circuit, we should expect some circuit-effects to e ignored which could led to significnt errors. In generl, the circuit ehvior on nodes tht re rechle through conducting trnsistors from the output node is modeled sufficiently to llow the Elmore dely to identify equivlent ssignments. From nlysis of lrge numer of error cses from our experiments, we

6 out \ in / c=0 Figure 13: Elmore Dely with S-D Coupling c 4. CONCLUSION We hve presented new technique for computing logic-stge delys in CMOS trnsistor networks. Our technique leverges MTB- DDs to enle the computtion of n Elmore dely estimte for ll possile input ssignments, which effectively groups these ssignments in Elmore-equivlent clsses. We cn extrct representtive from ech of the clsses for refinement of the dely vlue using circuit simultion. This pproch is pplicle to wide rnge of EDA prolems, nd demonstrtes the power of symolic methods even in deling with lrgely rel-vlued domins such s timing. Our pproch represents n improvement in ccurcy over previously pulished methods of dely clcultion for sttic timing nlysis in tht enles direct computtion of the Elmore estimte for ll input ssignments. Given this cpility, we cn void mjor source of errors y mximizing the refined dely vlues directly, rther thn ssuming the mximl-elmore cse will mximize the true dely. / c out \ 5. ACKNOWLEDGEMENTS We would like to thnk Emrh Acr for his help in integrting the TETA circuit simultor, nd the Compq Alph development tem nd ST Microelectronics for llowing us ccess to sensitive informtion for our experiments. Figure 14: Elmore Dely with Cross-Over Current hve determined tht the lrgest sources of errors re due to circuit ehvior on the fr side of off or turning-off trnsistors. By fr the lrgest source of errors re cpcitive coupling effects through nonconducting source-drin connections nd cross-over current flowing through turning-off trnsistors. Both effects re inherently excluded y the nture of the Elmore estimte. Figure 13 shows n exmple of the error induced y sourcedrin cpcitive coupling. While somewht contrived, it serves to demonstrte the circuit issues involved. Here we re ttempting to determine the dely from in rising to out flling, given tht node c is low. Since c is low nd its ssocited trnsistor is nonconducting, the vlues of nd will hve no effect on the Elmore dely estimte. However, using circuit simultor such s SPICE or TETA, we might see considerle difference etween the cses h = 1; = 1i nd h = 0; =0i. In the former, node will e flling, nd through source-drin coupling, will ccelerte the fll of out. In the ltter, node will e stle nd out will ehve s the Elmore dely predicts. In generl, the effects of source-drin coupling cn e unounded, nd re hevily dependent on process nd trnsistor-sizing. Figure 14 shows cse in which cross-over current through the turning-off pfet connected to will ffect the stge dely. In computing the Elmore dely, we set ll inputs to their finl vlues ( 0 in this cse), replce conducting trnsistors with resistors, nd determine the settling time of the resulting RC network. Therefore, ny circuit ehvior occurring in the top portion of the pfet chin cnnot ffect the Elmore computtion. However, under circuit simultion, we will see dely difference etween the cses h = 0; c = 0i nd h = 0; c=1i. The two cses differ only in the resistnce of the top portion of the pfet pullup chin, nd thus in the mount of cross-over current tht will flow into node out while is rising. If is rising slowly enough, nd the difference in crossover current is lrge, we could see sustntil vritions in the true dely of these su-cses despite hving the sme Elmore estimte. 6. REFERENCES [1] E. Acr nd L. T. Pileggi. TETA: Trnsistor-Level Engine for Timing Anlysis. CMU Internl Report, [2] R. I. Bhr, E. A. Frohm, C. M. Gon, G. Hchtel, E. Mcii, A. Prdo, nd F. Somenzi. Algeric Decision Digrms nd Their Applictions. ACM/IEEE Interntionl Conference on Computer Aided Design, pges , Novemer [3] R. E. Brynt. Grph-Bsed Algorithms for Boolen Function Mnipultion. IEEE Trnsctions on Computers, C-35(8):79 85, August [4] R. E. Brynt. Boolen Anlysis of MOS Circuits. IEEE Trnsctions on Computer Aided Design of Integrted Circuits nd Systems, CAD-6(4): , July [5] T. M. Burks nd R. E. Mins. Incorporting Signl Dependencies into Sttic Trnsistor-Level Dely Clcultion. TAU: ACM/IEEE Interntionl Workshop on Timing Issues in the Specifiction nd Synthesis of Digitl Systems, pges , [6] C. Y. Chu. Improved Models for Switch-Level Simultion. PhD thesis, Stnford University, Octoer [7] F. Drtu nd L. T. Pileggi. TETA: Trnsistor-Level Engine for Timing Anlysis. Proceedings of the Design Automtion Conference, pges , June [8] M. P. Desi nd Y. T. Yen. A Systemtic Technique for Verifying Criticl Pth Delys in 300MHz Alph CPU Design Using Circuit Simultion. Proceedings of the Design Automtion Conference, pges , June [9] C. B. McDonld nd R. E. Brynt. Symolic Functionl nd Timing Verifiction of Trnsistor Level Circuits. ACM/IEEE Interntionl Conference on Computer Aided Design, pges , Novemer [10] C. B. McDonld nd R. E. Brynt. Symolic Timing Simultion Using Cluster Scheduling. Proceedings of the Design Automtion Conference, June [11] C. J. Termn. RSIM - A Logic-Level Timing Simultor. Interntionl Conference on Computer Design, pges , Octoer 1983.