Digital Design. Sequential Logic Design -- Controllers. Copyright 2007 Frank Vahid

Transcription

1 Digitl Design Sequentil Logic Design -- Controllers Slides to ccompny the tetook Digitl Design, First Edition, y, John Wiley nd Sons Pulishers, Copyright 27 Instructors of courses requiring Vhid's Digitl Design tetook (pulished y John Wiley nd Sons) hve permission to modify nd use these slides for customry course-relted ctivities, suject to keeping Digitl this copyright Design notice in plce nd unmodified. These slides my e posted s unnimted pdf versions on pulicly-ccessile course wesites.. PowerPoint source (or pdf with nimtions) my not e posted to pulicly-ccessile wesites, ut my e posted for students on internl protected sites or distriuted directly to students y other electronic mens. Copyright 26 Instructors my mke printouts of the slides ville to students for resonle photocopying chrge, without incurring roylties. Any other use requires eplicit permission. Instructors my otin PowerPoint Frnk source Vhidor otin specil use permissions from Wiley see for informtion.

2 Introduction 3. Sequentil circuit Output depends not just on present inputs (s in comintionl circuit), ut on pst sequence of inputs Stores its, lso known s hving stte Comintionl digitl circuit F Simple emple: circuit tht counts up in inry In this chpter, we will: Design new uilding lock, flip-flop, tht stores one it Sequentil digitl circuit? F Comine tht lock to uild multi-it storge register Descrie the sequentil ehvior using finite stte mchine Must know sequence of pst inputs to know output Convert finite stte mchine to controller sequentil circuit hving register nd comintionl logic Digitl Design Copyright 26 Note: Slides with nimtion re denoted with smll red "" ner the nimted items 2

3 Emple Needing Bit Storge 3.2 Flight ttendnt cll utton Press cll: light turns on Stys on fter utton relesed Cll utton Cncel utton Bit Storge Blue light Press cncel: light turns off. Cll utton pressed light turns on Blue light Logic gte circuit to implement this? utton Bit Cll Cncel Q Cll Cncel utton Storge 2. Cll utton relesed light stys on Doesn t work. Q= when Cll=, ut doesn t sty when Cll returns to Need some form of feedck in the circuit Digitl Design Copyright 26 Cll utton Cncel utton Bit Storge Blue light 3. Cncel utton pressed light turns off 3

4 Clocks Clock period: time intervl etween pulses Freq Period Aove signl: period = 2 ns Clock cycle: one such time intervl Aove signl shows 3.5 clock cycles Clock frequency: /period Aove signl: frequency = / 2 ns = 5 MHz Hz = /s GHz GHz GHz MHz MHz. ns. ns ns ns ns Digitl Design Copyright 26 4

5 Finite-Stte Mchines (FSMs) nd Controllers 3.3 Wnt sequentil circuit with prticulr ehvior over time Controller lser Emple: Lser timer Push utton: = for 3 clock cycles ptient How? Let s try three flip-flops = gets stored in first D flip-flop Then 2nd flip-flop on net cycle, then 3rd flipflop on net OR the three flip-flop outputs, so should e for three cycles D Q D Q D Q Digitl Design Copyright 26 5

6 Need Better Wy to Design Sequentil Circuits Tril nd error is not good design method Will we e le to guess circuit tht works for other desired ehvior? How out counting up from to 9? Pulsing n output for cycle every cycles? Detecting the sequence 3 5 in inry on 3-it input? And, circuit uilt y guessing my hve undesired ehvior Lser timer: Wht if press utton gin while =? then stys one nother 3 cycles. Is tht wht we wnt? Comintionl circuit design process hd two importnt things. A forml wy to descrie desired circuit ehvior Boolen eqution, or truth tle 2. A well-defined process to convert tht ehvior to circuit We need those things for sequence circuit design Digitl Design Copyright 26 6

7 Descriing Behvior of Sequentil Circuit: FSM Finite-Stte Mchine (FSM) A wy to descrie desired ehvior of sequentil circuit Akin to Boolen equtions for comintionl ehvior List sttes, nd trnsitions mong sttes Emple: Mke chnge toggle ( to, or to ) every clock cycle Outputs: = ^ = Off On ^ Off On Off On Off On Off On Two sttes: Off (=), nd On (=) cycle cycle 2 cycle 3 cycle 4 Trnsition from Off to On, or On to Off, on rising clock edge stte Off On Off On Arrow with no strting stte points to initil stte (when circuit first strts) Outputs: Digitl Design Copyright 26 7

8 FSM Emple:,,,,repet Wnt,,,,,,,,... Ech vlue for one clock cycle Cn descrie s FSM Four sttes Outputs: = ^ = ^ = ^ = Off On On2 On3 ^ Trnsition on rising clock edge to net stte Stte Off OnOn2On3 Off OnOn2On3 Off Outputs: Digitl Design Copyright 26 8

9 Etend FSM to Three-Cycles High Lser Timer Four sttes Wit in Off stte while is ( ) Inputs: ; Outputs: = Off *^ ^ When is (nd rising clock edge), trnsition to On Sets = *^ = On ^ = On2 ^ = On3 On net two clock edges, trnsition to On2, then On3, which lso set = So = for three cycles fter utton pressed Inputs: Stte Off Off Off Off Off On On2 On3 Off Outputs: Digitl Design Copyright 26 9

10 FSM Simplifiction: Rising Clock Edges Implicit Showing rising clock on every trnsition: cluttered nd unnecessry Mke implicit -- ssume every edge hs rising clock, even if not shown. Eg., it is understood tht trnsition out of stte is on clock edge. Inputs: ; Outputs: = Off *^ *^ = ^ = On On2 ^ ^ = On3 Wht if we wnted trnsition without rising edge We don t consider such synchronous FSMs -- less common, nd dvnced topic Inputs: ; Outputs: = Off Only consider synchronous FSMs -- rising edge on every trnsition = = = On On2 On3 Digitl Design Copyright 26 Note: Trnsition with no ssocited condition thus trnsistions to net stte on net clock cycle

11 FSM Definition FSM consists of Set of sttes E: {Off, On, On2, On3} Set of inputs, set of outputs E: Inputs: {}, Outputs: {} Initil stte E: Off Inputs: ; Outputs: = Off = = On On2 = On3 Set of trnsitions Descries net sttes Eg: Hs 5 trnsitions Set of ctions Sets outputs while in sttes Eg: =, =, =, nd = We often drw FSM grphiclly, known s stte digrm Cn lso use tle (stte tle), or tetul lnguges Digitl Design Copyright 26

12 FSM Emple: Secure Cr Key Mny new cr keys include tiny computer chip When cr strts, cr s computer (under engine hood) requests identifier from key Key trnsmits identifier If not, computer shuts off cr FSM Wit until computer requests ID (=) Trnsmit ID (in this cse, ) Digitl Design Copyright 26 Inputs: ; Outputs: r Wit r= K K2 K3 K4 r= r= r= r=.k.., A Sequencer 2

13 FSM Emple: Secure Cr Key (cont.) Nice feture of FSM Cn evlute output ehvior for different input sequence r= Inputs: ; Outputs: r Wit K K2 K3 K4 Timing digrms show sttes nd output vlues for different input wveforms Inputs r= r= r= r= Q: Determine sttes nd r vlue for given input wveform: Inputs Stte Wit Wit K K2 K3 K4 Wit Wit Stte Wit Wit K K2 K3 K4 Wit Outputs r Output r Digitl Design Copyright 26 3

14 FSM Emple: Code Detector Unlock door (u=) only when uttons pressed in sequence: strt, then red, lue, green, red Input from ech utton: s, r, g, Also, output indictes tht some colored utton pressed Strt Red Green Blue s r g Code detector u Door lock FSM Wit for strt (s=) in Wit Once strted ( Strt ) If see red, go to Red Then, if see lue, go to Blue Then, if see green, go to Green Then, if see red, go to Red2 In tht stte, open the door (u=) Wrong utton t ny step, return to Wit, without opening door Digitl Design Copyright 26 u= s u= r Wit Inputs: s,r,g,,; Outputs: u Q: Cn you trick this FSM to open the door, without knowing the code? Strt Red u= s r g r Blue g Green r Red2 u= u= u= A: Yes, hold ll uttons simultneously 4

15 Improve FSM for Code Detector Inputs: s,r,g,,; Outputs: u Wit u= s r g r s Strt u= r Red u= Blue g Green r Red2 u= u= u= Note: smll prolem still remins; we ll discuss lter New trnsition conditions detect if wrong utton pressed, returns to Wit FSM provides forml, concrete mens to ccurtely define desired ehvior Digitl Design Copyright 26 5

16 Stndrd Controller Architecture How implement FSM s sequentil circuit? Use stndrd rchitecture Stte register -- to store the present stte Comintionl logic -- to compute outputs, nd net stte For lser timer FSM 2-it stte register, cn represent four sttes Inputs: ; Outputs: = Off = = On On2 = On3 Input, output Known s controller FSM inputs I Comintionl logic S m m O FSM outputs FSM inputs Comintionl logic s s Stte register n n FSM outputs m-it stte register Digitl Design Copyright 26 N Generl version 6

17 Stte Digrm Emple Modify the lser pulse genertor stte digrm (elow left), so tht the new FSM will only produce one pulse (3 cycles wide) for ech ctution of... or stted nother wy, one pulse out for one pulse in. Inputs: ; Outputs: = Off Inputs: ; Outputs: Off = On = On2 = On3 On On2 On3 Digitl Design Copyright 26 7

18 Controller Design 3.4 Five step controller design process Digitl Design Copyright 26 8

19 Controller Design: Lser Timer Emple Step : Cpture the FSM Alredy done Step 2: Crete rchitecture 2-it stte register (for 4 sttes) Input, output Inputs: ; Outputs: = Off = = = On On2 On3 Net stte signls n, n Step 3: Encode the sttes Any encoding with ech stte unique will work (in lue) FSM inputs Comintionl logic s s Stte register n n FSM outputs Digitl Design Copyright 26 9

20 Controller Design: Lser Timer Emple (cont) Step 4: Crete stte tle Inputs: ; Outputs: = Off = = = On On2 On3 FSM inputs Comintionl logic s s n n FSM outputs Stte register Digitl Design Copyright 26 2

21 Controller Design: Lser Timer Emple (cont) Step 5: Implement comintionl logic FSM inputs Comintionl logic s s n n FSM outputs Stte register = s + s (note from the tle tht = if s = or s = ) n = s s + s s + ss + ss n = s s + ss n = s s + ss + ss n = s s + ss Digitl Design Copyright 26 2

22 Controller Design: Lser Timer Emple (cont) Step 5: Implement comintionl logic (cont) FSM inputs Comintionl Logic Comintionl logic s s n n FSM outputs n Stte register n s s Stte register = s + s n = s s + ss n = s s + ss Digitl Design Copyright 26 22

23 Understnding the Controller s Behvior = Off = = = On On2 On3 = Off = = = On On2 On3 = Off = = = On On2 On3 s s n n s s n n s s n n stte= stte= stte= Inputs: Outputs: Digitl Design Copyright 26 23

24 Controller Emple: Button Press Synchronizer cycle cycle2 cycle3 cycle4 i Button press synchronizer controller o Inputs: i Outputs: o Wnt simple sequentil circuit tht converts utton press to single cycle durtion, regrdless of length of time tht utton ctully pressed We ssumed such n idel utton press signl in erlier emple, like the utton in the lser timer controller Digitl Design Copyright 26 24

25 Controller Emple: Button Press Synchronizer (cont) FSM inputs: i; FSM outputs: o i i i A B i C i i o= o= o= FSM inputs i Comintionl logic s s Stte register o n n FSM outputs Step 2: Crete rchitecture n = s si + ssi n = s s i o = s si + s si = ss Step : FSM Comintionl logic o FSM inputs: i; FSM outputs: o i i i i i i o= o= o= Step 3: Encode sttes A B C unused Comintionl logic Inputs Outputs s s i n n o i s s Stte register n n Digitl Design Copyright 26 Step 4: Stte tle Step 5: Crete comintionl circuit 25

26 Controller Emple: Sequence Genertor Wnt generte sequence,,,, (repet) Ech vlue for one clock cycle Common, e.g., to crete pttern in 4 lights, or control mgnets of stepper motor Inputs: none; Outputs: w,,y,z wyz= wyz= A D B C wyz= wyz= Step : Crete FSM Comintionl logic s s Stte register n n Step 2: Crete rchitecture w y z Inputs: none; Outputs: w,,y,z wyz= wyz= A B D C wyz= wyz= Step 3: Encode sttes Digitl Design Copyright 26 Step 4: Crete stte tle w = s = ss y = s s z = s n = s or s n = s s s Stte register n w y z n Step 5: Crete comintionl circuit 26

27 Controller Emple: Secure Cr Key (from erlier emple) Inputs: ; Outputs: r Step Wit r= K K2 K3 K4 r= r= r= r= r Step 2 Comintionl logic n2 n n s2 s s Stte register Step 3 r= r= r= r= r= Digitl Design Copyright 26 Inputs: ; Outputs: r Step 4 We ll omit Step 5 circuits from equtions is old ht y now. 27

28 Emple: Seq. Circuit to FSM (Reverse Engineering).k.. Circuit Anlysis Wht does this circuit do? y z y=s z = ss n=(s or s) n=(s *s ) A D Outputs: y, z B C sttes n n A yz= D yz= B yz= C yz= sttes with outputs s s Stte register Work ckwrds Inputs: ; Outputs:y, z A D yz= B C yz= yz= Digitl Design Copyright 26 Pick ny stte nmes you wnt yz= sttes with outputs nd trnsitions 28

29 Common Pitflls Regrding Trnsition Properties Only one condition should e true For ll trnsitions leving stte = net stte? Else, which one? One condition must e true For ll trnsitions leving stte wht if =? Else, where go? Digitl Design Copyright 26 29

30 Defining the FSM using VHDL Using the model put forth y the uthor there will e two process sttements Comintionl logic (net stte logic nd output logic comined) Stte register Modeling the stte register Assume cs (current stte) nd ns (net stte) re it vectors process () egin if ( event nd = ) then cs <= ns; end if; end process; This register is uilt with rising edge triggered D-FF s. Digitl Design Copyright 26 3

31 FSM w/ VHDL (cont.) For flling-edge triggered register process () egin if ( event nd = ) then cs <= ns; end if; end process; For rising-edge triggered register, with sync. reset process (, reset) egin if (reset = ) then cs <= ; elsif ( event nd = ) then cs <= ns; end if; end process; For flling-edge triggered register, with sync. ctive-low reset Digitl Design Copyright 26 process (, reset) egin if ( event nd = ) then if (reset = ) then cs <= ; else cs <= ns; end if; end if; end process; 3

32 FSM w/ VHDL (cont.) If you define enumerte new type, life will e esier Emple: rchitecture Behviorl of duledgedetect is type sttetype is (init, rising, wit4flling, flling); signl ns, cs: sttetype; egin Note the stte nmes in Modelsim very hndy no decoding required. Another enefit for using enumerted types for nming sttes is when designing the comintoril logic lock Digitl Design Copyright 26 32

33 FSM w/ VHDL (cont.) Setup comintoril logic lock in process sttement nd cse sttement: Inputs: i; Outputs: z = zr,zf i z = init i z= i i' z= z= rising Digitl Design Copyright 26 wit4flling i i' flling process(i, cs) egin cse cs is when init => if i='' then ns <= init; else ns <= rising; end if; zr <= ; zf <= ; when rising => if i='' then ns <=flling; else ns <= wit4flling; end if; zr <= ; zf <= ; when wit4flling => if i='' then ns <= flling; else ns <= wit4flling; end if; zr <= ; zf <= ; when flling => ns <= init; zr <= ; zf <= ; when others => ns <= init; zr <= ; zf <= ; end cse; end process; 33