Engineer-to-Engineer Note

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1 Engineer-to-Engineer Note EE-247 Technicl notes on using Anlog Devices DSPs, processors nd development tools Contct our technicl support t nd t Or visit our on-line resources nd Interfcing AD7676 ADCs to ADSP-21065L SHARC Processors Contributed by Aseem Vsudev Prbhugonkr nd Jgdeesh Ryl Rev 1 October 5, 2004 Introduction This ppliction note explins how to interfce n AD7676 nlog-to-digitl (ADC) converter in mster seril mode (internl discontinuous clock) with SHARC ADSP-21065L processors. This ppliction note lso provides exmple code to demonstrte how to progrm the ADSP-21065L processor's seril port to receive dt from the AD7676 converter when the AD7676 is configured in mster seril mode, supplying discontinuous seril dt clock to the processor's seril port. About AD7676 ADCs AD7676 ADCs re 16-bit, 500 ksps, chrgeredistribution SAR, fully differentil nlog-todigitl converters (ADCs) tht opertes from single 5-V power supply. In ddition to the highspeed 16-bit smpling ADC, these prts lso contin n internl conversion clock, error correction circuits, nd seril nd prllel system interfce ports. AD7676 ADCs re fctory-clibrted nd re comprehensively tested, ensuring tht they meet or exceed their AC prmeters such s signl-tonoise rtio (SNR) nd totl hrmonic distortion (THD), in ddition to the more trditionl DC prmeters of gin, offset, nd linerity. AD7676 pplictions include: CT Scnners Dt Acquisition Instrumenttion Spectrum Anlysis Medicl Instruments Bttery-Powered Systems Process Control AD7676 ADCs cn operte in seril mode s well s prllel mode. In seril dt mode, they cn be configured to supply seril dt clock (mster seril interfce internl clock) or they cn tke seril dt clock externlly (slve seril interfce). In mster seril mode, AD7676 converters provide discontinuous bit clock. This gurntees tht the conversion performnce is not degrded becuse there re no voltge trnsients on the digitl interfce during the conversion process. AD7676 Product Highlights The AD7676 A/D converter provides: Excellent INL The AD7676 hs mximum integrl nonlinerity (INL) of 1.0 LSB with no missing 16-bit code. Superior AC performnces The AD7676 hs minimum dynmic of 92 db (94 db typicl). Fst throughput Copyright 2004, Anlog Devices, Inc. All rights reserved. Anlog Devices ssumes no responsibility for customer product design or the use or ppliction of customers products or for ny infringements of ptents or rights of others which my result from Anlog Devices ssistnce. All trdemrks nd logos re property of their respective holders. Informtion furnished by Anlog Devices pplictions nd development tools engineers is believed to be ccurte nd relible, however no responsibility is ssumed by Anlog Devices regrding technicl ccurcy nd topiclity of the content provided in Anlog Devices Engineer-to-Engineer Notes.

2 The AD7676 is 500 ksps, chrgeredistribution, 16-bit SAR ADC with internl error correction circuitry. Single-supply opertion The AD7676 opertes from single 5 V supply nd typiclly dissiptes only 67 mw. It consumes 7 µw mximum in power-down. Seril or Prllel interfce Verstile prllel (8 or 16 bits) or 2-wire seril interfce rrngement comptible with 3 V or 5 V logic. About ADSP-21065L Processors ADSP-21065L processors re generl-purpose, progrmmble, 32-bit processors tht llow you to progrm with equl efficiency in fixed-point or floting-point rithmetic. This progrmming flexibility combined with the high-performnce core nd integrted peripherls give the ADSP L SHARC processors n outstnding price/performnce vlue for wide rnge of consumer, communictions, utomotive, industril, nd computer pplictions. ADSP-21065L processors re code comptible with the Anlog Devices (ADI) SHARC fmily of processors. As such, customers hve immedite ccess to softwre nd hrdwre development tools from ADI nd third prties. ADSP-21065L Seril Ports ADSP-21065L processors feture two synchronous seril ports (SPORTs) tht provide n inexpensive interfce to wide vriety of digitl nd mixed-signl peripherl devices. The seril ports cn operte t 1x clock frequency, providing ech with mximum dt rte of 33 Mbit/s. Ech seril port hs primry nd secondry set of trnsmit nd receive chnnels. Independent trnsmit nd receive functions provide greter flexibility for seril communictions. Seril port dt cn be trnsferred to nd from on-chip memory vi DMA utomticlly. Ech seril port supports three opertion modes: DSP seril port mode, I2S mode (n interfce commonly used by udio codecs), nd TDM (time division multiplex) multichnnel mode. The seril ports cn operte with little endin or big endin trnsmission formts, with selectble word lengths of 3 bits to 32 bits. Seril port clocks nd frme syncs cn generted internlly or externlly. Figure 1 shows the seril port in core driven mode. Figure 1. ADSP-21065L Seril Port Block Digrm AD7676-to-ADSP-21065L Interfce AD7676 ADCs cn be configured in seril mode or in prllel mode to trnsfer 16-bit digitized dt to DSP/processor or micro-controller. In seril mode, it cn be configured to provide seril bit clock for trnsferring dt to DSP (clled mster seril mode). In this mode, the seril clock is discontinuous (or gted) nd is present only while trnsferring dt. This provides better noise immunity. This ppliction note discusses the interfce in mster seril mode becuse the seril clock supplied by the A/D converter is gted nd requires specific sequence to receive dt over the seril port. Interfcing AD7676 ADCs to ADSP-21065L SHARC Processors (EE-247) Pge 2 of 7

3 The AD7676 converter's seril interfce signls tht re used with DSP seril port interfce comprises the following: /CNVST This convert strt signl strts conversion. A flling edge on this signl puts the internl smple-nd-hold into hold stte nd initites conversion. SDOUT The AD7676 drives out conversion results on this pin. The dt bits re clocked out on the rising edge or flling edge of the seril clock, bsed on the stte of the INVSCLK pin. SCLK The converter clocks the dt bits out on the seril clock edges. This cn be n input (Slve Seril Mode) or n output (Mster Seril Mode). SYNC This signl is used s digitl output frme synchroniztion with the internl dt clock. This cn be configured s n ctive high or n ctive low signl from the converter. Figure 2 shows the timing for the seril interfce protocol. trnsmit frme sync is configured to be n ctive low nd erly frme sync. Also, the frme sync is configured s dt-independent frme sync so tht the frme sync is periodiclly generted to cquire smples from the ADC. SPORT0 receive clock (RCLK0) nd receive frme sync (RFS0) re configured s externl. The SPORT receive frme sync is configured to be n ctive low, lte frme sync. The ADC is configured to strobe dt bits on the clock's flling edges; thus, the seril port is configured to smple dt on the seril clock's rising edges. Refer to Figure 3 for signl connections between the SHARC processors nd the ADC. ADSP L SPORT0 TFS0 RFS0 DR0A RCLK0 /CNVST SYNC SDOUT SCLK AD7676 Figure 2. AD7676 Seril Interfce Timing Digrm in Mster Seril Mode Red fter conversion Refer to the AD7676 dt sheet for detiled informtion bout the timing specifictions. Figure 3. ADSP-21065L Seril Port Interfce with AD Block Digrm SPORT0, which reds digitized smples from the ADC, must configured initilly for seril word length of 15 bits. Inside the first receive interrupt service routine (ISR), the seril world length should be chnged on-the-fly to 16 bits. Note tht the first two reds (the 15-bit red nd the next immedite red) must be dummy reds for the interfce to function properly. Figure 4 is one exmple of the seril interfce signls is one exmple. ADSP-21065L SPORT to AD7676 Seril port SPORT0 is used for this interfce. The SPORT0 trnsmit frme sync (TFS0) genertes /CNVST for the ADC. The SPORT0 Interfcing AD7676 ADCs to ADSP-21065L SHARC Processors (EE-247) Pge 3 of 7

4 Figure 4. ADSP-21065L SPORT Interfce with AD7676 Oscilloscope Cpture of Interfce Signls As shown in Figure 4, the ADC drives seril dt on the seril clock's flling edges. The ADSP L processor's seril port smples the dt on the seril clock's rising edges. The interfce functions stisfctorily with either frmed mode or unfrmed mode for receive frme sync. Interfcing AD7676 ADCs to ADSP-21065L SHARC Processors (EE-247) Pge 4 of 7

5 Appendix The project files re included in ZIP file ttched to this ppliction note. ADSP-21065L_SerilPort_with_AD7676.sm /******************************************************************************/ // // Nme: Interfcing ADSP-21065L with AD7676 // /****************************************************************************** (C) Copyright Anlog Devices, Inc. All rights reserved. File Nme: ADSP-21065L_SerilPort_with_AD7676.sm Dte Modified: 08/19/04 Rev 1.0 Softwre: Hrdwre: Purpose: VisulDSP++3.5 (July updte) ADSP-21065L EZ-KIT Lite To receive dt from AD7676 *******************************************************************************/ #include <def21065l.h> #define FRAMED_MODE //#define UNFRAMED_MODE.section/dm seg_dmd;.vr dc_dt;.vr counter = 0;.section/pm seg_rth; nop;nop;nop;nop; nop;jump strt; // Sport receive interrupt.section/pm seg_sp; nop;jump isr; rti;rti;.section/pm seg_pmco; strt: // Configure TFS (CONVST) to be generted continuously r0 = 0x0; dm(stctl0) = r0; r0 = 0xf0012; dm(tdiv0) = r0; r0 = DITFS SPEN_A SLEN32 LTFS ICLK ITFS TFSR ; dm(stctl0) = r0; Interfcing AD7676 ADCs to ADSP-21065L SHARC Processors (EE-247) Pge 5 of 7

6 r0 = 0x ; dm(tx0_a) = r0; // Enble interrupts bit set mode1 IRPTEN; bit set imsk SPR0I; r0 = 0x0; dm(srctl0) = r0; r1 = 0x0; r7 = 0x2; #ifdef UNFRAMED_MODE r0 = SPEN_A SLEN15 LRFS LAFS CKRE; #ifdef FRAMED_MODE r0 = SPEN_A SLEN15 LRFS LAFS RFSR CKRE; dm(srctl0) = r0; nop; nop; jump(pc,0);.section/pm seg_pmco; isr: r3 = dm(rx0_a); // If it is the first word received, reconfigure the sport for // 16 bits r0 = dm(counter); comp(r0,r1); if eq jump reconfigure; // Incrementing the counter r6 = dm(counter); r6 = r6 + 1; dm(counter) = r6; comp(r6,r7); if eq rti; dm(dc_dt) = r3; rti;.section/pm seg_pmco; reconfigure: // Reconfiguring the seril port for 16 bits. #ifdef UNFRAMED_MODE r0 = SPEN_A SLEN16 LRFS LAFS CKRE; #ifdef FRAMED_MODE r0 = SPEN_A SLEN16 LRFS LAFS RFSR CKRE; Interfcing AD7676 ADCs to ADSP-21065L SHARC Processors (EE-247) Pge 6 of 7

7 dm(srctl0) = r0; r2 = 1; dm(counter) = r2; rti; References [1] ADSP-21065L DSP Hrdwre Reference Mnul. Rev 2.0, July Anlog Devices, Inc. [2] AD7676 Preliminry Technicl Dt Sheet. Rev B. Anlog Devices, Inc. [3] ADSP-21065L DSP EZ-KIT Lite Evlution System Mnul. Rev 2.0, Jnury Anlog Devices, Inc. [4] Interfcing Gted Clocks to ADSP-21065L SHARC Processors (EE-244). Rev 1, September Anlog Devices Inc. Document History Revision Rev 1 October 05, 2004 by Aseem Vsudev Prbhugonkr Description Initil Relese Interfcing AD7676 ADCs to ADSP-21065L SHARC Processors (EE-247) Pge 7 of 7

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