EE Controls Lab #2: Implementing State-Transition Logic on a PLC

Transcription

1 Objective: EE 44 - Controls Lb #2: Implementing Stte-rnsition Logic on PLC ssuming tht speed is not of essence, PLC's cn be used to implement stte trnsition logic. he dvntge of using PLC over using hrdwre is tht progrmming is much esier nd more verstile thn building hrdwre. his lb ttempts to demonstrte tht stte-trnsition logic cn be implemented on PLC nd tht such implementtions re reltively esy to progrm. In order to implement switching logic, flip flops re required. wo bsic flip-flops re the, used in step, nd D, used in step 2. Once wy to implement flip flop is found, these cn be used to implement stte-trnsition logic, s described in step 4. Procedure: PLC Implementtion of Flip Flop. One wy to implement -flip flop uses synchronous logic. he output () should remin unchnged if =, nd flip if =. he eqution for this is = + his circuit cn then be implemented in ldder logic using the following progrm. Here, rising edge on switch # is detected in the first rung. his signl then toggles ccording to (). Step #: Progrm in the following circuit nd verify tht it does operte s -flip-flop. () P Flip Flop second wy to build -flip flop is to use n up-counter tht counts to. If = initilly, the counter is enbled through the 4th rung. When pulses, the counter increments, setting =. When pulses gin, the counter is clered. Step #2: Progrm in the following circuit nd verify tht it behves s -flip flop. 2-

2 P 2 2 UCN 4 2 Flip Flop Set-Cler Flip Flops (D Flip Flops) second type of flip flop is D-type. Here, = when set (D) goes high. = on cler. wo different circuits which implement this function follow: he first uses synchronous logic with = cler + D cler. (2) he second uses counter. Step #3: Progrm in ech of the following two circuits. Verify tht the output is set when SW (D) is high nd is clered when SW2 (cler) is high. set cler 2 set cler D Flip Flop set cler 2 UCN 4 set cler x Implementing Switching Logic on PLC Problem: Design circuit which counts how mny times SW goes high. On the 4th count, strt counting from zero gin. Solution: One solution is to use stte-trnsition logic. Ech stte defines one set of events. In this cse, whether the switch hs been set,, 2, or 3 times. When SW- () pulses, you re to go to the next stte. his cn be expressed symboliclly s follows: 2-2

3 2 B C D Implementtion Using D-ype Flip-Flops Using flip-flops, ech stte is ssigned unique bit pttern. Since 4 sttes exist, two bits re required, 2, with the vlue of 2 corresponding to ech stte being rbitrrily defined in the bove figure. Once the stte-trnsition digrm is defined, the inputs to the flip flops s function of the input nd the stte is determined. ssuming tht D-type flip flops re being used, the Krnough mps for Set nd Cler re s follows. Set 2 X X X X Cler 2 X X X Set2 2 X X X Cler2 2 X X X For exmple, if you re in stte () nd the input is, you wnt to remin in stte. his mens tht Set should be zero nd Cler cn be nything. his is denoted s Set= nd Cler=X in the upper left corner of ech mp. he miniml covering mps which define ech input re denoted by the circles on the Krnough mps nd result in the equtions Set = 2 Cler = 2 + Set2 = Cler2 = + 2 ldder-logic progrm to implement these equtions long with D-flip flops follows: (3) 2-3

4 P set cler set2 cler2 UCN 4 UCN Step #6: Progrm in the bove circuit nd verify tht 2 pss through the sttes... ech time SW pulses high. Implementtion Using synchronous Logic Insted of using stte-trnsition logic, synchronous logic could lso be used. Here, the sttes, nd 2, should be = ( 2 + ) + ( 2 ) 2 = (Set if you're in stte or x nd is low. lso set if you're in stte nd is high.) Step #7: Implement the following progrm on PLC. Verify tht the sttes trnsition from... ech time SW goes high. (4) 2-4

5 P Write-up: 2 2 ) Give the equivlent circuit for ech of the ldder-logic progrms using ND-OR-NO gtes. 2) Comment on the dvntges nd disdvntges of implementing switching logic with PLC's vs. discrete-components. 3) Comment on some of the dvntges nd disdvntges of using flip-flops insted of synchronous logic to implement switching logic. Which method would you prefer using if writing progrm? Which would you prefer if modifying someone else's progrm? Why? 4) Design J-K flip-flop using ltter logic. he logic digrm is J K 2-5