ISSCC 2006 / SESSION 21 / ADVANCED CLOCKING, LOGIC AND SIGNALING TECHNIQUES / 21.5

Transcription

1 21.5 A 1.1GHz Chrge-Recovery Logic Visvesh Sthe, Jung-Ying Chueh, Mrios Ppefthymiou University of Michign, Ann Aror, MI Boost Logic is chrge-recovery circuit fmily cple of operting t GHz-clss frequencies [1]. In this pper, the design nd experimentl vlidtion of 1.1GHz Boost Logic test chip is reported. The test chip is fricted in 0.13µm CMOS process with n integrted inductor nd n on-chip clock genertor. This chip is n implementtion of dynmic chrge-recovery logic fmily operting successfully in the GHz regime. Previous chrge-recovery circuit implementtions with on-chip clock genertors hve een reported to operte t frequencies no greter thn 1MHz [2, 3, 4]. In ddition to fst opertion, Boost Logic chieves high energy efficiency due to its (i) lnced clock lod, (ii) decoupled logic evlution nd chrge-recovery stges, nd (ii) sence of diodes. This Boost Logic chip recovers 60% of the energy supplied to it t ech clock cycle. Figure shows Boost Logic gte. It consists of dul-ril logic stge tht opertes in tndem with chrge-recovering oost stge. The logic stge performs functionl evlution nd is powered y dc supply V C = V dd V ss = V th, centered t V dd /2. The Boost stge then mplifies the potentil difference etween nd to V dd. Figure illustrtes the opertion of Boost inverter. During the oost stge, the heder nd footer trnsistors of the logic stge re off, isolting the puts from the logic rils. As φ(φ) trnsitions to V ss (V dd ), trnsistor M3 (M1) dischrges (chrges) the put node (). The put nodes trck the power-clocks until their potentil difference reches V th, t which time ll trnsistors in the oost stge re in cut-off nd remin so during the susequent logic stge. As φ flls elow V ss, logic evlution egins, resolving the put nodes to potentil difference of nerly V th, nd s φ crosses V dd, the oost stge drives the put nodes to the full ril. By relying on resonnce to drive the put nodes to voltge difference V dd, the oost stge efficiently provides high gte overdrive to fn logic stges. Although V C = V th, ll trnsistors conduct in the superthreshold liner region due to this high gte overdrive. Fricted in 0.13µm 8M (copper, 2 thick) 1.2V CMOS process, this test chip consists of 8 gte chins with totl of 1680 Boost gtes comprising AND, OR, XOR nd INV. The logic gtes nd clock genertor occupy totl re of µm 2. Complementry resonnt clocks φ nd φ re generted with n H- ridge topology. Pulses nd t 180 re derived from reference clock nd drive the clock genertor switches in tndem, periodiclly replenishing dissipted energy in the system. The frequency f of the reference clock is progrmmle in the rnge 700MHz f 1.3GHz. The resonnt clocks oscillte t the reference frequency f. For efficient opertion, f should e ner the nturl frequency f 0 1/ 2 LC where C is the totl cpcitnce resonted with inductnce L. To explore the impct of design trde-offs on energy efficiency, the clock genertor is designed with progrmmle switch widths (0µm<W<0µm) nd pulse duty cycle (0%<D<50%). The GHz frequency trget necessittes the deployment of n integrted inductor in chrge-recovery logic design. A 2.4nH 2.5-turn inductor is included in two top-level metl lyers to resonte 29pF (per-phse) of clock cpcitnce. Figure shows mesured supply current nd corresponding energy dissiption versus operting frequency for the test chip. Reported energy-dissiption numers include the energy dissipted in the resonnt network, clock genertor, nd clock genertor switches. Ech point in the plot corresponds to the minimum supply current or the energy dissiption of the circuit over ll possile V dd, V C, D, nd W vlues tht result in correct opertion, s verified y oserving the required signture wveform. The minimum current is mesured t 800MHz. The corresponding energy dissiption, is expectedly higher t 850MHz. The lod cn e nevertheless driven t frequencies ove t the expense of dditionl energy dissiption. By scling the supply voltge to 1.5V, correct opertion t 1.3GHz is verified. When resonting t 850MHz, the circuit recovers 60% of the pek energy stored in the system, which trnsltes to Q fctor of pproximtely By forcing the circuit to operte t 1GHz, the recovery drops to %. Figure shows the mesured energy dissiption s function of V C nd V dd. The optiml V C results from the trdeoff etween improved recovery efficiency t high V C nd lower conventionl energy dissiption t lower V C. The optiml V dd rises from the trdeoff etween reduced I 2 R losses due to lower oscilltion mplitude t low V dd nd higher gte overdrive t high V dd, which enles efficient chrge recovery in fn gtes. At 850MHz, the minimum mesured energy dissiption is oserved for V c = 0.45V, V dd =1.4V, D = 22%, nd W = 2µm. The I 2 R dissiption losses in the clock network re replenished y periodiclly injecting current into the inductor. The mount of energy replenished in ech cycle is function of the replenishing switch width W nd the duty cycle of the pulse duty cycle D, shown in Fig Figure shows the shmoo plot otined y vrying the two prmeters while ensuring correct opertion t 850MHz. Ech point in the plot signifies correct opertion for the corresponding pir (W, D). All points denoted y the sme symol fll within 4pJ-wide nd of mesured energy dissiption. The iso-energy nds illustrte the trdeoff etween W nd D. From this sctter plot it cn e inferred tht oth W nd D ply significnt role in controlling clock genertor dissiption. Figure shows microgrph of the 1.1GHz chrge-recovery chip. Including the mot round it, the 2.4nH on-chip inductor occupies 0.078mm 2. Inductor size decreses for higher operting frequencies or lrger designs. The complementry clock phses, φ nd φ, re red from opposite sides of the inductor with min trunk for ech phse running long the length of the chins. Alternting shielded spines of φ nd φ re striped cross the ctive logic re with 16µm pitch. The implementtion of fully integrted GHz-clss chrge-recovery dynmic logic is presented. Voltge nd current mesurements indicte tht t the nturl frequency of the design, 60% energy recovery is chieved. Correct opertion is verified up to 1.3GHz. Acknowledgments: This reserch ws supported in prt y ARO under Grnt No. DAAD We thnk Snjy Pnt nd Dvid Roerts for help with design nd testing. References: [1] V. S. Sthe, et l., A GHz-Clss Chrge Recovery Logic, ISLPED, pp , Aug., [2] S. Kim, et l., True Single-Phse Aditic Circuitry, Trnsctions on VLSI Systems, pp , Fe., [3] D. Suvkovic, C. Slm, Two Phse Non-Overlpping Clock Aditic Differentil Cscode Voltge Switch Logic (ADCVSL), ISSCC Dig. Tech. Ppers, pp , Fe., [4] D. Mksimovic, V. Oklodzij, B. Nikolic, nd K. Current, Clocked CMOS Aditic Logic with Integrted Single-Phse Power-Clock Supply, Trnsctions on VLSI Systems, Aug., 2000.

2 ISSCC 2006 / Ferury 7, 2006 / 3:45 PM inputs inputs LOGIC Vdd Vss M5 True Evlution Tree M6 Vdd M8 Complementry Evlution Tree M7 Vss BOOST Figure : Schemtic digrm of Boost-Logic gte with NMOS-only pulldown evlution trees. M1 M2 M4 M3 Voltges Boost Logic Boost m 900m 800m 700m 600m 500m 0m 0m 200m 100m 0 1n 2n 3n 4n Time Figure : Simultion wveform of Boost-Logic inverter. 50 Energy Reference Clock 1/2f 1/f 1/f Progrmmle Dely Progrmmle Dely 2W W V dd 2.4nH V ss 2W W Progrmmle Schmitt Triggers reset Boost-Logic gte chins Signture Outputs Energy Dissiption per Cycle(pJ) 45 Current 20 Current(mA) Operting Frequency (GHz) Figure : Boost-Logic test chip. Figure : Mesured current nd corresponding energy versus frequency. Mximum Energy Bnd (64 68pJ) 60 Energy per Cycle (pj) Pulse Duty Cycle, D(%) Minimum Energy Bnd (32 36pJ) V C (V) V dd (V) Clock Genertor Switch Width, W(m) Figure : Mesured energy dissiption s function of V C nd V dd. Figure : Shmoo plot of Boost chip.

3 Clock-genertor switches Boost-Logic gte chins Clock-genertor switches Progrmmle Schmitt triggers Figure : Die microgrph of Boost-Logic test chip.

4 LOGIC Vdd M5 BOOST inputs True Evlution Tree M1 M4 M6 Vss Vdd M8 M2 M3 inputs Complementry Evlution Tree M7 Vss Figure : Schemtic digrm of Boost-Logic gte with NMOS-only pulldown evlution trees.

5 1.2 Boost Logic Boost m 900m 800m Voltges 700m 600m 500m 0m 0m 200m 100m 0 1n 2n 3n 4n Time Figure : Simultion wveform of Boost-Logic inverter.

6 V dd reset Boost-Logic gte chins 1/f 2W 2W 1/2f 1/f W 2.4nH W Progrmmle Dely V ss Reference Clock Progrmmle Dely Progrmmle Schmitt Triggers Signture Outputs Figure : Boost-Logic test chip.

7 50 Energy Current Energy Dissiption per Cycle(pJ) Current(mA) Operting Frequency (GHz) Figure : Mesured current nd corresponding energy versus frequency.

8 60 55 Energy per Cycle (pj) V C (V) V dd (V) 1.45 Figure : Mesured energy dissiption s function of V C nd V dd.

9 Mximum Energy Bnd (64 68pJ) Pulse Duty Cycle, D(%) Minimum Energy Bnd (32 36pJ) Figure : Shmoo plot of Boost chip. Clock Genertor Switch Width, W(m)

10 Clock-genertor switches Boost-Logic gte chins Clock-genertor switches Progrmmle Schmitt triggers Figure : Die microgrph of Boost-Logic test chip.