# ECE 274 Digital Logic. Digital Design. Datapath Components Shifters, Comparators, Counters, Multipliers Digital Design

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1 ECE 27 Digitl Logic Shifters, Comprtors, Counters, Multipliers Digitl Design..7 Digitl Design Chpter : Slides to ccompny the textbook Digitl Design, First Edition, by Frnk Vhid, John Wiley nd Sons Publishers, Copyright 2007 Frnk Vhid Instructors of courses requiring Vhid's Digitl Design textbook (published by John Wiley nd Sons) hve permission to modify nd use these slides for customry course-relted ctivities, subject to keeping this copyright notice in plce nd unmodified. These slides my be posted s unnimted pdf versions on publicly-ccessible course websites.. PowerPoint source (or pdf with nimtions) my not be posted to publicly-ccessible websites, but my be posted for students on internl protected sites or distributed directly to students by other electronic mens. Instructors my mke printouts of the slides vilble to students for resonble photocopying chrge, without incurring roylties. Any other use requires explicit permission. Instructors my obtin PowerPoint source or obtin specil use permissions from Wiley see for informtion. Shifters. Shifter Exmple: Temperture Averger Shifting (e.g., left shifting 00 yies 00) useful for: Mnipulting bits Converting seril dt to prllel (remember erlier bove-mirror disply exmple with shift registers) Shift left once is sme s multiplying by 2 (00 (3) becomes 00 (6)) Why? Essentilly ppending 0 -- Note tht multiplying deciml number by 0 ccomplished just be ppending 0, i.e., by shifting left (55 becomes 550) i3 i2 i i0 Shift right once sme s dividing by 2 << Symbol i3 i2 i i0 q3 q2 q q0 Left shifter in i3 i2 i i q3 q2 q q0 Shifter with left shift or no shift in sh inr shl shr s0 s q3 q2 q q0 Shifter with left shift, right shift, nd no shift inl 3 Four registers storing history of tempertures Wnt to output the verge of those tempertures Add, then divide by four Sme s shift right by 2 Use three dders, nd right shift by two 0000 (7) (8) 0000 (2) 00 (5) T R Rb Rc Rd clk shift in (2) divide by 0 >> (0) Rvg Tvg

2 Brrel Shifter in A shifter tht cn shift by ny mount sh -bit brrel left shift cn shift left by 0,, 2, or 3 positions q3 q2 q q0 8-bit brrel left shifter cn shift left by Shift by shifter uses 2x muxes. 8x 0,, 2, 3,, 5, 6, or 7 positions mux solution for 8-bit brrel shifter: too (Shifting n 8-bit number by 8 positions mny wires. is pointless -- you just lose ll the bits) Q: xyz=??? to Cou design using 8x muxes nd lots shift by 5? 8 I of wires Too mny wires x sh << in 0 More elegnt design (by ) Chin three shifters:, 2, nd 0 Cn chieve ny shift of 0..7 by y sh <<2 in 0 enbling the correct combintion of 8 those three shifters, i.e., shifts shou sum to desired mount z sh << in 0 i3 i2 i i0 Net result: shift by 5: (by ) Q 5 Comprtors N-bit equlity comprtor: Outputs if two N-bit numbers re equl -bit equlity comprtor with inputs A nd B 3 must equl b3, 2 = b2, = b, 0 = b0 Two bits re equl if both, or both 0 eq = (3b3 + 3 b3 ) * (2b2 + 2 b2 ) * (b + b ) * (0b0 + 0 b0 ) Recll tht XNOR outputs if its two input bits re the sme eq = (3 xnor b3) * (2 xnor b2) * ( xnor b) * (0 xnor b0) 3 b3 2 b2 b 0 b0 00 = 0? eq ( ) b3 b2 b b0 -bit equlity comprtor eq ( b ).5 6 Mgnitude Comprtor Mgnitude Comprtor N-bit mgnitude comprtor Indictes whether A>B, A=B, or A<B, for its two N-bit inputs A nd B How to design? Consider how compre by hnd. First compre 3 nd b3. If equl, compre 2 nd b2. And so on. Stop if comprison not equl -- whichever s bit is is greter. If never see unequl bit pir, A=B. A=0 B= Equl 0 00 Equl 0 00 Unequl So A > B By-hnd exmple leds to ide for design Strt t left, compre ech bit pir, pss results to the right Ech bit pir clled stge Ech stge hs 3 inputs indicting results of higher stge, psses results to lower stge 3 b3 2 b2 b 0 b0 Igt Ieq Ilt Stge 3 Stge 2 ( ) Stge Stge 0 AgtB AeqB AltB 7 0 Igt b3 b2 b b0 Ieq -bit mgnitude comprtor 0 Ilt ( b ) AgtB AeqB AltB 8 2

3 Mgnitude Comprtor Mgnitude Comprtor Exmple: Minimum of Two Numbers Igt Ieq Ilt 3 b3 2 b2 b 0 b0 AgtB AeqB AltB Design combintionl component tht computes the minimum of two 8-bit numbers Stge 3 Stge 2 Stge Stge 0 Ech stge: out_gt = in_gt + (in_eq * * b ) A>B (so fr) if lredy determined in higher stge, or if higher stges equl but in this stge = nd b=0 out_lt = in_lt + (in_eq * * b) A<B (so fr) if lredy determined in higher stge, or if higher stges equl but in this stge =0 nd b= out_eq = in_eq * ( XNOR b) A=B (so fr) if lredy determined in higher stge nd in this stge =b too Simple circuit inside ech stge, just few gtes (not shown) 9 0 Counters.6 Counter Exmple: Above Mirror Disply N-bit up-counter: N-bit register tht cn increment (dd ) to its own vlue on ech clock cycle 0000, 000, 000, 00,..., 0,, 0000 Note how count rolls over from to 0000 Terminl (lst) count, tc, equls during vlue just before rollover Internl design Register, incrementer, nd N-input AND gte to detect terminl count 0 -bit up-counter -bit up-counter t c -bit register C + Recll bove-mirror disply exmple from Chpter 2 Assumed component tht incremented xy input ech time button pressed: 00, 0, 0,, 00, 0, 0,, 00,... Cn use 2-bit up-counter Assumes mode= for just one clock cycle during ech button press Recll Button press synchronizer circuit mode clk 2-bit up c ou n t er t c c c0 x y 2 3

4 Counter Exmple: Hz Pulse Genertor Using 256 Hz Oscilltor Down-Counter Suppose hve 256 Hz oscilltor, but wnt Hz pulse Hz is pulse per second -- useful for keeping time Design using 8-bit upcounter, use tc output s pulse Counts from 0 to 255 (256 counts), so pulses tc every 256 cycles 8-bit up-counter osc (256 Hz) 8 p (unused) ( Hz) -bit down-counter, 0, 0, 00,, 00, 000, 000, 0000,, Terminl count is 0000 Use NOR gte to detect Need decrementer (-) design like designed incrementer -bit down-counter -bit register 3 Up/Down-Counter Counter with Prllel Lod Cn count either up or down Includes both incrementer nd decrementer Use dir input to select, using 2x: dir=0 mens up Likewise, dir selects pproprite terminl count vlue dir clr clr -bit up/down counter -bit 2 x 0 -bit register + Up-counter tht cn be loded with externl vlue Designed using 2x mux input selects incremented vlue or externl vlue Lod the internl register when loding externl vlue or when counting t c L -bit 2 x 0 -bit register C + 2 x 0 t c C 5 6

5 Counter with Prllel Lod Useful to crete pulses t specific multiples of clock Not just t N-bit counter s nturl wrp-round of 2 N Exmple: Pulse every 9 clock cycles Use -bit down-counter with prllel lod Set prllel lod input to 8 (000) Use terminl count to relod When count reches 0, next cycle lods 8. Why lod 8 nd not 9? Becuse 0 is included in count sequence: 8, 7, 6, 5,, 3, 2,, 0 9 counts clk 000 L -bit down-counter Counter Exmple: Timer A type of counter used to mesure time If we know the counter s clock frequency nd the count, we know the time tht s been counted Exmple: Compute cr s speed using two sensors First sensor () clers nd strts timer Second sensor (b) stops timer Assuming clock of khz, timer output represents time to trvel between sensors. Knowing the distnce, we cn compute speed 7 8 Multipliers Arry Style Cn bui multiplier tht mimics multipliction by hnd Notice tht multiplying multiplicnd by is sme s ANDing with.7 Multipliers Arry Style Generlized representtion of multipliction by hnd

6 Multipliers Arry Style Multiplier design rry of AND gtes b0 b pp In-clss Exercise Design somewht ccurte Celsius to Fhrenheit converter. The conversion circuit receives digitized temperture in Celsius s 6-bit binry number C nd outputs the temperture in Fhrenheit s 6-bit output F using the following pproximtion: F = C*30/ pp2 0 0 b2 + (5-bit) b3 pp3 pp (6-bit) A B * P + (7-bit) Block symbol p7..p

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