CS2204 DIGITAL LOGIC & STATE MACHINE DESIGN fall 2008

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1 CS224 DIGITAL LOGIC & STATE MACHINE DESIGN fll 28 STAND ALONE XILINX PROJECT 2-TO- MULTIPLEXER. Gols : Lern how to develop stnd lone 2-to- multiplexer () Xilinx project during which the following re introduced : Schemtic design on Xilinx softwre, How to simulte nd verify logic circuits, The Digilent XLA FPGA bord, nd How to test circuits on FPGA bords 2. Lb Work : Follow the first two of three mjor digitl product development cycles given below. These two development cycles re the development cycle on computers, nd the development cycle with FPGA chips. All three development cycles re described in detil in hndout titled Digitl Product Development. 2. Development Cycle on Pper/Computers : The development cycle on computers consists of three steps : Logic design Input/output reltionship Implementtion (the schemtic) Test Modify The logic design consists of obtining the precise input-output reltionship nd then the implementtion. The input/ output reltionship mens we specify exctly which opertion hppens when. The implementtion mens we get the full schemtic. The test is the simultion of the circuit on computers nd modifiction is the simple chnge of the schemtic bsed on test results. As we know, if circuit is simple one completely designs it on pper. There is no need to do block prtitioning. For the 2-to-, it is the cse. So, we design it on pper completely nd then move the design to the computer Logic Design : 2... The Input-Output Reltionship : The digitl circuit is viewed s blck box with only its inputs nd outputs considered. Then, the outputs re relted to the inputs. A 2-to- hs three inputs nd one output. The blck box view nd input-output reltionship of the re s follows : (control input) (dt input ) (dt input ) b c select 2-to- y (dt output) If = then y = b else y = c Input is the select input (control input) which selects one of the other two inputs (dt inputs). The selected dt input is connected to output y. Thus, t ny moment, the output is equl to one of the two dt inputs. In order to understnd the blck box view nd the input-output reltionship better, inputs b nd c re lbeled s nd, respectively. It is becuse, the output is equl to b when is nd the output is equl to input c when is. In fct, lbeling dt inputs with numbers strting t is custom in dt mnuls. Polytechnic Institute of NYU Pge of 4 Stnd Alone Xilinx Project - 2-to- September 23, 28

2 The textul input/output reltionship of the 2-to- is then : Output y is equl to b when is nd is equl to c when is. We cn restte the textul reltionship the following wy s well : This cn be restted s : Output y is when is AND b is OR when is AND c is. Output y is when is NOT AND b is OR when is AND c is. Another wy to describe the input-output reltionship is by mens of truth tble tht shows the vlue of the output for ech input combintion : b c y The implementtion : The implementtion is bout determining the components nd their wiring bsed on mjor opertions, design gols (speed, cost, power consumption, relibility, size, weight, etc.) nd vilble components of the technology. For the, the mjor opertion is the selection opertion s described by the truth tble bove. Throughout the semester, we will im t fstest circuits nd miniml circuits (miniml number of components in the circuit). Finlly, in the lb, our components re those provided by the Xilinx softwre nd listed in the Symbols Toolbox window. In order to determine the components, first, the librry of components (gtes, flip-flops nd Xilinx Design Blocks, XDBs, lso known s Xilinx mcros) is serched to see if there is ny component tht immeditely implements this circuit (the textul input-output reltionship/the truth tble). We relize tht the librry does contin 2-to- mcro, nmed M2_. But, for the ske of getting more experience with gtes nd their wiring, we decide to implement the multiplexer ourselves by using gtes, i.e. gte network. So, we will not use tht Xilinx mcro. The gte network implements the input/output reltionship (the textul one nd the truth tble). It is one gte network, becuse we know there is just one output. How cn we get the gte network? How cn we determine the gtes nd their wiring? First, we re given three types of gtes : AND, OR nd NOT. Second, we re currently studying Switching Algebr where the three gtes re defined s follows : b b AND b =. b AND Gte. b b b OR b = + b OR Gte + b NOT Gte NOT = The dot symbol is for the AND gte, the plus symbol is for the OR gte nd the overline is for the NOT gte. There re other nmes used for the NOT gte, including Inverter nd Complement. The Xilinx softwre clls it INV, mening inverter. Polytechnic Institute of NYU Pge 2 of 4 CS224 Stnd Alone Xilinx Project - 2-to- September 23, 28

3 In clss, we obtined n expression for this circuit by using Switching Algebr. The Switching Algebr expression tht precisely describes the 2-to- multiplexer circuit : y = b + c We study in clss how one cn convert switching expression to gte network. The gte network for the 2-to- multiplexer with FPGA switch inputs (SW, SW2 nd SW3) nd the LED light output (LD4) is s follows : Pin 28 Pin 27 SW SW2 b b LD4 Pin 66 Pin 26 SW3 c c y = b + c The reson why this expression is correct (stisfies the textul description nd the truth tble) cn be shown by ssigning the two possible vlues to input : ) When = => y = (( ). b) + (. c) = (( ). b) + (. c) = (. b) + () = b + = b 2) When = => y = (( ). b) + (. c) = (( ). b) + (. c) = (. b) + (c) = + c = c Clerly, the switching expression does stisfy (implement) the input-output reltionship. Note tht Switching Algebr llows us to derive miniml expressions nd so miniml gte networks (miniml hrdwre) strting with truth tble, not textul reltionship. One cn use Truth-Functionl Clculus, insted of Switching Algebr, to get the expression. In this clculus, we concentrte on input nd output vlues tht re equl to. Let s strt with the textul description of the multiplexer where the input nd output vlues re : Output y is when is NOT AND b is OR is AND c is. The clculus works on compound sttements formed by declrtive sentences connected by logicl connectives. For exmple, is is declrtive sentence. is AND c is is lso declrtive sentence. AND nd OR re logicl connectives. How do we determine the gte network then? The connectives imply the gtes to use. Tht is, the words in cpitl nd bold fce in the bove sentence indicte the gtes : one NOT gte, two AND gtes nd one OR gte. Next, how do we determine the gte connections? The text hs two declrtive sentences, forming compound sttement by mens of the word OR. The first sentence hs n AND connective relting input to input b. Also, input is in the negtive form. In the second sentence connective, AND is used to relte input to c. In terms of truth-functionl clculus, the expression for the multiplexer is : y = (( ) Λ b) ( Λ c) One then converts the Λ symbol to n AND opertion symbol nd the symbol to n OR opertion symbol to obtin the finl miniml expression : y = (( ). b) + (. c) We re done with the design of the multiplexer on pper nd now redy to move the design to the computer. Note tht for lrge circuits, we still do the design on pper. First, the initil design steps : the blck box is prtitioned into smller (sub)blocks on pper (block prtitioning). Then, for ech (sub)block, the component determintion nd wiring re crried out on pper. When we re stisfied with the pper design of the (sub)block, we move it to the computer. We will prctice this frequently this semester Circuit Design on the Computer (Xilinx Softwre) : Follow the steps given below to develop the circuit. Note tht throughout the semester, the steps to go through will be given where the bullet symbol shows new step. Key presses nd mouse selections re shown in bold. Also, throughout the semester, the hndouts will be prepred by ssuming tht students use their S drive s their Polytechnic Institute of NYU Pge 3 of 4 CS224 Stnd Alone Xilinx Project - 2-to- September 23, 28

4 project storge spce. If students re not ble to ccess the S drive, for exmple, in plce where no network connection is possible, they should use the defult Xilinx project directory which hs the pth \Fndtn\ctive\projects\... Lter, students move their project to the S drive when they estblish the connection. Another convention to remember is tht when we sy click the mouse, we men clicking the left mouse button. The right mouse click will be explicitly mentioned. First tsk before strting new project : In order to keep our designs orgnized, we need to hve them stored with respect to their experiment number. For exmple for ech project, we will hve directory on the S drive. Therefore, for the current experiment, we will do the following : By using My Computer crete new directory nmed smux under cs224. smux stnds for stnd lone. We will hve our multiplexer circuit in this smux folder. Strting the Xilinx softwre : On your PC, strt the Xilinx Project Mnger by doing one of the two below : Double click on the Xilinx Project Mnger icon, Go through menu selections : Strt (on the lower left corner of Microsoft Windows) -> Progrms -> Xilinx Foundtion 4.2 -> Project Mnger. You will see Getting Strted window in the foreground nd Project Mnger window in the bckground : Creting New Project : Since we hve not designed the project yet, we will strt with creting new project. In the Getting Strted dilogue box, click on the rdio button with lbel Crete New project. Click OK Polytechnic Institute of NYU Pge 4 of 4 CS224 Stnd Alone Xilinx Project - 2-to- September 23, 28

5 A dilogue box with the nme New Project will pop up : In the dilogue box, enter mux2to s the nme of your design. We will chnge the directory of the project to the cs224\smux directory on the S drive. Click on the Browse... button nd select the project directory (your working directory) s the smux directory. All your 2-to- multiplexer files will be kept there. Click on the rdio button with lbel Schemtic since we will hve schemtic design, not n HDL design. Finlly, there re three list boxes on the lst row. They re specificlly bout the FPGA chip. We hve to mke sure tht the choices re Sprtn, SPC84, nd 3. Click on the rrow in the Flow re nd scroll until you see Sprtn. Select it. Click on the rrow in the re to the right nd scroll down until you see SPC84. Select it. Click on the rrow in the re to the right nd select speed 3 for the FPGA. Press OK. The computer now shows the Project Mnger window with three pnels s shown on the next pge. The upper left pnel displys the project file hierrchy, the upper right one shows the flow the project follows until it is completed. Finlly, on the bottom, there re notes (ctions, error messges nd wrnings) tht the softwre plces s it goes through the phses of the flow. From time to time, students hve to red these notes to get sense of wht the softwre is doing during the circuit development. Let s discuss the three pnels in more detil : The upper left pnel shows the files in your project nd the versions. Right click on one of the listed items, sy simprims, you cn get more detiled informtion bout the simsprism Librry Mnger window. This mnger is not importnt for us to discuss t this point. We will close it. The upper right pnel is the work region. It shows the design in different phses of the flow. For exmple, one sequence of circuit development steps is the verticl progression which is s follows : DESIGN ENTRY -> IMPLEMENTATION -> PROGRAMMING. This would be the cse if the circuit hd no errors, such s ll components, connections nd pin numbers re correct. The DESIGN ENTRY lets you input your design by using either the HDL Editor or FSM Editor or the Schemtic Editor. Note tht we will use only the Schemtic Editor this semester. Polytechnic Institute of NYU Pge 5 of 4 CS224 Stnd Alone Xilinx Project - 2-to- September 23, 28

6 The IMPLEMENTATION converts the design (the schemtic) to wht is clled the bit file. It is the bit file tht is downloded to the FPGA chip. During Implementtion, the softwre plces nd routes the design components nd wires bsed on the device (FPGA chip) model. The PROGRAMMING downlods your design to the FPGA bord, i.e. it progrms the FPGA chip by downloding the bit file to the chip. Two kinds of testing of the circuit on the computer re provided s you see on the upper right pnel : Simultion nd Verifiction : Simultion is used to check if your schemtic design implements the required logic. It does not consider the chip tht will be used. Tht is, it ssumes idel components re used. Thus, it just indictes if the logic is correct. This simultion is lso clled functionl simultion. Verifiction hs two options nd so two buttons re provided. The one on the left is Timing Simultion nd the one on the right is Timing Anlyzer. The Timing Simultion is the one we will use this semester. It uses the dely informtion derived in the IMPLEMENTATION step : The Timing Simultion is done fter we go through the IMPLEMENTATION step which tkes into ccount the FPGA chip. The Timing Simultion gives better sense if the design stisies the ppliction requirements! Thus, it gives better ide bout the speed of the circuit nd ctches timing relted errors in the design. We re now redy to strt the Schemtic editor to begin the schemtic design of the 2-to- multiplexer circuit. The schemtic design Click on the Schemtic Editor button to strt the schemtic editor : A blnk design sheet (window) will be shown. The schemtic editor is lwys in the Select nd Drg mode when it is strted. Before we drw the schemtic, i.e. plcing the components nd wiring them, we show the finl circuit we will obtin below : Polytechnic Institute of NYU Pge 6 of 4 CS224 Stnd Alone Xilinx Project - 2-to- September 23, 28

7 Our first tsk on the schemtic is entering our nmes (designers nmes) on the lower right corner of the schemtic. The softwre hs lredy prepred the templte there. Completely zoom out by selecting Disply -> Full Pge. You will notice the rectngulr re on the lower right which we will hve our informtion plced in. Go through File -> Tble Setup... You will be shown dilogue box titled Edit Stndrd Tble. On Line: enter your nme nd the nme of one of your prtners. On Line2: enter your temmte (s) nme(s). On Line3: enter CS224 - Your Section - Fll 28 Click OK. In order to plce components (such s n AND gte) on the design sheet, we need to chnge the mode to the Symbols mode. This cn be done in three different wys : Click on the Symbols toolbox icon on the left side of the screen : Pull down the menu Mode then select Symbols, or Press key F3. The SC Symbols window ppers on the right side. This is the librry of components we will use this semester. Scroll down the list to become fmilir with it : Polytechnic Institute of NYU Pge 7 of 4 CS224 Stnd Alone Xilinx Project - 2-to- September 23, 28

8 Let s plce one of the two 2-input AND gtes on the sheet : Click on the AND2 component inside the window of the librry list. Now n AND2 gte is ttched to your mouse nd you cn plce it on the design sheet wherever you wnt. Move the mouse to the left nd click it in the middle of the sheet. Now we will give nme to the AND gte. Nming components is helpful for understnding nd debugging of the circuit. It is lso very criticl for documenttion. Documenttion is necessry for engineers who cooperte on design nd lso for those who would be working on the design in the future. Do one of four steps below to return to the Select nd Drg mode in which the nming will be performed : Double click in the smll box in the upper left corner of the SC Symbols box, or Click on or Press Esc, (Escpe) or Go through Mode -> Select nd Drg. To nme the AND gte do the following : Click the right mouse button on the AND gte. A pop up menu will be shown next to the gte. Click on the first menu commnd Symbol Properties A window nmed Symbol Properties will be shown with lrge number of choices : Locte the second horizontl field on the left : the Reference: field. Replce the defult nme by entering U2, Click the OK button. The nme U2 will pper just bove the AND gte symbol. It is custom to give nmes s U, U2, etc. to the gtes, FFs nd Xilinx mcros in schemtic digrms. Repet the bove steps to pick, plce nd nme components for the remining gtes : Plce nother 2-input AND gte below the first one nd nme it U3. Polytechnic Institute of NYU Pge 8 of 4 CS224 Stnd Alone Xilinx Project - 2-to- September 23, 28

9 Plce 2-input OR gte to the right of the AND gtes nd nme it U4. On the SC Symbols librry, 2-input OR gte is nmed OR2 which is seen fter considerble scrolling. In order to quickly select component down the list, do the following : Type in OR2 on the bottom empty spce of the SC Symbols window. Plce NOT gte (clled INV by Xilinx) to the left of the top AND gte nd nme it U. Now, we will connect the symbols (components) by wiring them. We need to enter the Drw Wires mode which cn be done in three different wys : Pull down the menu Mode then select Drw Wires, or Press key F4, or Click on the icon nmed Drw wires on the left edge of the screen : Now, to wire the components : Click on one side of gte nd move the mouse (s it is stretched by the softwre) to the pproprite gte nd click on the pproprite side to ttch the wire. To mke sure the wire is connecting the two components, switch to the Select nd Drg mode. Click on one of the wired components nd drg it. If the wire is stretched with it, there is connection. Do the sme thing on the other component. If the wire hs blue dot t the touching point of component, it mens the wire is not ctully mking contct with the component. If wire hs to be connected to gte on one side nd hs to hve no connection on the other side, double click the mouse on the non-touching side fter you stretched the wire long enough. Note tht even if two wires re not connected to ech other, they hve the sme vlue if they hve the sme nme. The softwre connects them internlly. The circuit is redy! But, in order to downlod the circuit to the FPGA chip, we need to ttch input buffers nd output buffers nd lso input pds nd output pds. We hve to ttch these components to be ble to ccess the gtes from the externl world. Note tht these devices would not be needed if FPGA chips were not used. Strt with the SC Symbols window nd continue with the following : Plce n IBUF device selected from the SC Symbols window to the left of the gtes. IBUF stnds for Input Buffer. Press key F2 to switch to the Select nd Drg mode nd nme this input buffer A_BUF s we did for the gtes. Repet this for the other two inputs nd nme the IBUFs s B_BUF nd C_BUF. Connect n IPAD device selected from the SC Symbols window to the input of the top IBUF. IPAD stnds for Input Pd. Thus, the position of the IPAD is to the left of A_BUF. Press key F2 to switch to the Select nd Drg mode nd nme this input pd A_PAD. Repet this for the other two inputs, by ttching two IPADs nd nme them s B_PAD nd C_PAD. Drw the wires connected to the IBUFs nd IPADs s seen in figure on pge 7. Plce n OBUF device selected from the SC Symbols window to the right of the OR gte. OBUF stnds for Output Buffer. Press key F2 to switch to the Select nd Drg mode nd nme this output buffer Y_BUF s we did for the input buffers. Polytechnic Institute of NYU Pge 9 of 4 CS224 Stnd Alone Xilinx Project - 2-to- September 23, 28

10 Connect n OPAD device selected from the SC Symbols window to the output of the OBUF. OPAD stnds for Output Pd. Thus, the position of the OPAD is to the right of the OBUF. Press key F2 to switch to the Select nd Drg mode nd nme this output pd Y_PAD. Drw the wires connected to the OBUF nd OPAD s seen in figure on pge 7. We will now nme the wires. Note tht nother nme used for wires is net. Those wires whose vlues we will check during our simultions must be nmed. It is dvisble to nme s mny other wires s possible for documenttion purposes. But, often time is limiting fctor. Also, too mny nmes in the schemtic would be confusing. Thinking of pproprite nmes becomes hrd nd typing mistkes re quite likely. Thus, it is left to students judgement to decide which other wires should be nmed. Also, if simultions show errors, you will nme more wires to observe their vlues. During these nmings, you need to hve nming convention in order to be consistent nd not to be confused. We will use the convention below : Press key F2 to switch to the Select nd Drg mode. Right click on the wire tht is connected to the input of U Select the menu commnd Net Properties nd nme this net A. Repet this for the other wires connecting buffers to gtes s B nd C. Also nme the wires tht connect pds nd buffers s B_NP2B, A_NP2B, C_NP2B, nd Y_NB2P, where the N in the nme is for net. The P2B portion mens Pd to Buffer nd the B2B portion mens Buffer to Pd. Next, we hve to indicte to the Xilinx softwre which pin of the FPGA chip is connected to which IPAD or OPAD. This opertion is clled binding the input nd output PADs to the PINs. If you study the picture of the FPGA bord or the PINout tble of the bord, you will relize tht some FPGA pins re permnently connected to toggle switches, push buttons, 7-segment disply nd LED lights. Wht we will do is to connect the three IPADs to three toggle switches nd the OPAD to LED light. A toggle switch genertes or, depending on the position of its hndle. A LED light gives off light when it is pplied. We decide to use toggle switches SW, SW2 nd SW3 which re connected to PINs 28, 27 nd 26 of the FPGA chip, s, b nd c inputs, respectively. We lso decide to use LED light LD4 to show the output vlue of the AND gte. This light is connected to PIN 66 of the FPGA chip. Thus, we will use PIN 66 s output y : Press F2 to enter the Select nd Drg mode. Right click on A_PAD. Select Symbol Properties Locte the Prmeters: section of the Symbol Properties window which is the lower prt of the window. In the Nme: list box (gin inside the Prmeters: pnel), select LOC. In the Description: field type in p28. Click on the Add button fter which ## LOC=P28 ppers in the box under the Description: field. Press the OK button. Now this input PAD is bound to PIN 28 of the FPGA chip. You will see LOC=P28 just below the IPAD. Bind the other input PADs nd the output PAD to PIN 27, PIN 26 nd PIN 66, respectively. The schemtic design is over! We now hve to sve our design in the LABS domin : Go through File -> Sve. We then minimize Schemtic Editor nd return to the Project Mnger window. You will see the? mrk next to the nme of schemtic design file : mux2to.sch. Polytechnic Institute of NYU Pge of 4 CS224 Stnd Alone Xilinx Project - 2-to- September

11 If we summrize the design steps : We select logic components from the SC Symbols window nd connect them by using nets (wires). We nme these components nd wires. We connect input nd output buffers to input nd output wires then connect input nd output PADs to the buffers. We lso nme them. We then bind the PADs to the FPGA pins. Note tht besides explicit documenttion tht helps reder, the designer cn help more by just simply drwing schemtic tht looks good to the eye. We cll it beutifying the circuit. This mens components tht do similr work form horizontl nd verticl lines, line tnglings re minimized nd there is enough spce between components to identify circuits, subcircuits, nd so on. We re now redy to strt the next step of the development cycle on computers : the testing. This step will show if we hve ny logic or connection problem in our circuit Integrity Test : An esy wy to see if there is simple error, such s typing error in nming or wiring error, do the following on the schemtic editor window : Select Options -> Integrity Test. You would receive messge Integrity test pssed successfully if there is no problem. You cn continue with the functionl simultion step below. At other times, the test shows the following messge : Integrity test pssed successfully, wrnings detected. Plese inspect Project Mnger window for detils. Click OK. If you red Integrity test pssed successfully on the Project Mnger window, then, you cn continue with the functionl simultion step below. Otherwise, the schemtic needs to be corrected nd nother Integrity Test must be pplied Test vi Functionl Simultion : We must hve the Project Mnger with three pnels on the screen. We locte the lrge Simultion button on the upper right pnel. Click on the Simultion button to enter the logic simultor. If pop up menu wrns tht the Schemtic netlist is older thn click Yes. Mximize the Logic Simultor window. Go through Signl -> Add Signls to select input signls to ssign vlues to nd n output signl to observe its vlue. You will see three djcent pnels with nmes Signls Selection, Chip Selection nd Scn Hierrchy. In the Signls Selection pnel, double-click on signls nmed A_NP2B, B_NP2B, C_NP2B, nd Y_NB2P. Then close the Signls Selection window, by clicking on the Close button right below the Signls Selection pnel. Be creful not close the Logic Simultor window. Now the selected signls re listed on the first column. The softwre requires ll input signls be renmed : Click on signl A_NP2B which will be highlighted. Mke selections Signl -> Add Stimultors A keybord will be shown on the screen. Click key q on the keybord. Stimultor q is ssigned to signl A_NP2B. This selection of nme is completely rbitrry. Polytechnic Institute of NYU Pge of 4 CS224 Stnd Alone Xilinx Project - 2-to- September

12 Click on signl B_NP2B which will be highlighted. Click key w on the keybord. Stimultor w is ssigned to signl B_NP2B. Click on signl C_NP2B which will be highlighted. Click key e on the keybord. Stimultor e is ssigned to signl C_NP2B. Close the keybord by clicking on the Close button. We hve ssigned nmes to the inputs (stimultors). We will not do nming for the output. Click on q in red color to toggle the logic vlue of signl A_NP2B. You will see the short line next to the chrcter q moving up nd down (toggling) with ech press on q. We cn now simulte the circuit for ny input combintion : Set vlues of signls A_NP2B, B_NP2B nd C_NP2B to ll, by clicking on q, w nd e, ppropritely. Click the button locted just below the View menu nme on top nd wtch the wveforms of input nd output signls. The output vlue, Y_NB2P should show. Click the button severl times to comfortbly observe tht it is. Repet this simultion for ll other input combintions,,,, etc. to mke sure your design works right. The truth tble whose output vlue we re observing vi simultions is given in clss, on pge 7 of the Development Cycle with FPGAs For New Chip hndout nd lso below. SW SW2 SW3 LD4 If ll input combintions result in correct outputs, we end the functionl simultion step : Close Logic Simultor window to return to the Project Mnger. If the wveform does not mtch your expected result, you will need to go bck to your schemtic design to check it. Often, the common problem is tht some wires do not mke contct with the components. Another wy to see if there is wiring error in the circuit is by doing the IMPLEMENTATION step of the Xilinx softwre on the Project Mnger. Recll tht this step is needed to obtin the bit file. If there re errors, depending on the severity of the error, the IMPLEMENTATION is stopped. Whether the IMPLEMENTATION is stopped or not, messges re generted in the Implementtion Log File in the form of error messges nd wrning messges. All error messges hve to be resolved. Among the wrning messges, logicl net xyz hs multiple drivers nd logicl net xyz hs no driver must be lso resolved. Driver mens output. A Multiple Drivers messge mens there re two or more outputs with the sme nme. The No Driver messge mens there is no input signl connected to component therefore the output cnnot be generted. The logicl net xyz hs no lod wrning mens the output is not connected to ny input. Tht is, the output is not used. In some cses, some outputs re not needed nd so not used. In other cses, by mistke the output is not used nd this hs to be corrected. The term project t the course web site hs 24 no lod wrnings which re fine. We do not need these 24 outputs. Strting with the Project Mnger window nd by following Reports -> Implementtion Log Files, one cn red the Implementtion Log File nd see wht the problems re. Polytechnic Institute of NYU Pge 2 of 4 CS224 Stnd Alone Xilinx Project - 2-to- September

13 If we summrize the simultion steps : We select signls whose vlues we wnt to observe. We renme inputs (dd stimultors to inputs) to be ble to ssign vlues to them. We observe input nd output wveforms Development Cycle on Bredbords with FPGAs : As described in the Development Cycle with FPGAs for New Chip hndout, go through the following cycles : Do Xilinx IMPLEMENTATION of the design, then perform timing simultions nd then Downlod the design to the FPGA chip. In order to do timing simultions, the simultor is strted s described bove. The simultor is in the Functionl simultion mode which is shown in n re ner the top of the simultor window. Click on the selection rrow nd select the Timing option to chnge the mode. Test the design on the FPGA bord. Modify the schemtic design if errors re encountered. EXERCISES : ) Develop 2-bit 2-to- circuit implemented by two gte networks. Nme this project mux2b2t. Appropritely nme the components nd wires. Beutify the schemtic design. In order to design the 2-bit 2-to-, study the logic design of the below : Input-output reltionship : A 2-bit 2-to- hs four dt inputs, one control input nd two dt outputs. Its blck box view nd the inputoutput reltionship in the form of n opertion tble re given below : (K, K ) K (M, M ) M select bit 2-to- 2 Y (Y, Y ) select Y K M Since the circuit is complex, with five inputs, we cnnot use truth-functionl clculus nor truth tble. For exmple, the truth tble of this circuit would need 2 5 rows = 32 rows. It would be hrd to obtin the expressions. Thus, one needs to divide the circuit into blocks nd design the blocks seprtely. How cn we divide the blocks? If we consider the inputs nd outputs in more detil, we would see the following : K K M M select 2-bit 2-to- Y Y select Y K M Y K M Polytechnic Institute of NYU Pge 3 of 4 CS224 Stnd Alone Xilinx Project - 2-to- September

14 We see tht we cn prtition the circuit into two identicl blocks. Ech block is 2-to- tht we hve just designed. Tht is, the we hve designed is in fct -bit 2-to-, but becuse of convention, the -bit prt is not mentioned. Then, here re the two blocks of the circuit : K 2-to- M Y select K M 2-to- Y select 2) Develop (-bit) 4-to- circuit nd nme this project mux4t. Appropritely nme the components nd wires. Beutify the schemtic design. In order to design the 4-to-, study the logic design of the below : Input-output reltionship : A 4-to- hs four dt inputs, two control inputs nd one dt output. Its blck box view, the input-output reltionship in the form of n opertion tble re given below : b c d select select 2 3 msb 4-to- Y select select Y b c d Since the circuit is complex, with six inputs, we cnnot use truth-functionl clculus nor truth tble. For exmple, the truth tble of this circuit hs 2 6 rows = 64 rows. One needs to divide the circuit into blocks nd design the blocks seprtely. How cn we divide the blocks? We see tht we cn perform the top two rows of the opertion tble in prllel with the bottom two rows by using select input, select nd then we select one out of the two by using select. Thus, we would use three 2-to- circuits designed in this experiment : b select 2-to- p c d select 2-to- q p q select 2-to- Y 3) By using the concepts introduced in Exercises nd 2, develop 2-bit 4-to- circuit. Nme this project mux2b4t. Appropritely nme the components nd wires. Beutify the schemtic design. 4) By using the concepts introduced in Exercises, 2 nd 3, develop 4-bit 2-to- circuit. Nme this project mux4b2t. Appropritely nme the components nd wires. Beutify the schemtic design. Polytechnic Institute of NYU Pge 4 of 4 CS224 Stnd Alone Xilinx Project - 2-to- September

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