Mixed CMOS PTL Adders

Size: px
Start display at page:

Download "Mixed CMOS PTL Adders"

Transcription

1 Anis do XXVI Congresso d SBC WCOMPA l I Workshop de Computção e Aplicções de julho de 2006 Cmpo Grnde, MS Mixed CMOS PTL Adders Déor Mott, Reginldo d N. Tvres Engenhri em Sistems Digitis Universidde Estdul do Rio Grnde do Sul (UERGS) Guí, RS Brzil {deor-mott,reginldo-tvres}@uergs.edu.r Astrct. This pper presents simple method to design mixed CMOS PTL dders. The ide is to comine conventionl sttic CMOS gtes with psstrnsistor logic (PTL). With this strtegy is possile to design dders with smller numer of trnsistors nd reduced current consumption when compred with CMOS version. 1. Introduction In this pper we present method to design full dders with reduced current consumption. The method is sed on comining conventionl CMOS sttic gtes with pss-trnsistors logic (PTL). Full dders nd rithmetic circuits re frequently used s prt of opertive units nd processors. Becuse of rithmetic opertions re intensively used, the design of n dder circuit with low current consumption is required. Low current consumption is n importnt key for deep-sumicron-designs (DSM). PTL is frequently used to improve the design of rithmetic nd logic circuits. Sometimes different PTL design techniques re employed in order to chieve high speed or lower power dissiption s shown in [Yno, Ymnk, et.l.,1990][ Suzuki, Ohkuo, et.l., 1993]. Some synthesis techniques tht comine conventionl sttic CMOS gtes nd pss-trnsistor gtes re lredy proposed such s [Yng nd Ciesielsky 1999][Ynin, Sptnekr nd Bmji, 1998]. Pss-trnsistors design is n interesting re of the digitl integrted circuits, nd severl synthesis techniques were developed such s [Yng nd Ciesielsky, 1999][Scholl nd Becker, 1999][Ynin, Sptnekr nd Bmji, 1998][Tvres nd Berkelr, 1999]. Pss-trnsistors cn e employed to design logic circuits with reduced numer of trnsistors when compred with conventionl sttic CMOS. It cn e verified for some logic functions such s multiplexer nd exclusive-or. When the numer of trnsistors is reduced, we cn decrese the numer of lyout elements nd prsitic cpcitnces. Severl prsitic cpcitnces re chrging nd dischrging during signl propgtion, nd some current is consumed. Therefore, PTL design cn e used to remove some trnsistors, nd, it my e importnt to reduce the current consumption. However, some electricl prolems must e ddressed. There re situtions in which the input signl of PTL gte is pssed to the output node, ut the output signl sometimes cn e degrded. For instnce, the 1 input logic vlue when trnsmitted through NMOS trnsistor cnnot chrge the output prsitic cpcitnce to level. The mximum voltge stored y the output cpcitnce is -Vth. Vth is the threshold voltge of the NMOS trnsistor. The sme hppens when PMOS trnsistor is eing considered. In this cse the 0 input logic vlue when trnsmitted is not totlly propgted, nd Vth voltge remins stored in the output cpcitnce. 34

2 In this pper we propose design technique le to reduce the current demnded y full dder circuit. The min ide is to design full dder circuit with CMOS nd PTL gtes. A complete full dder design description cn e found in [Rey, Chndrksn nd Nikolic 2003]. 2. Mixed CMOS nd PTL Gtes Becuse pss-trnsistor cn propgte logic signl with some electricl degrdtion, technique to regenerte eventul pss signls is necessry. The technique presented in this pper is simple. It consists of inserting pss-trnsistor gte etween two sttic CMOS gtes. There re two importnt points ehind this ide: first, n pproprite trnsistor sizing of the sttic CMOS gte should e used in order to gurntee the norml output swing voltge levels. Second, only single pss-trnsistor is inserted etween two CMOS sttic logic pth. Note tht chin of pss-trnsistors my slow down the signl propgtion, nd, therefore it is not ttrctive s n implementtion option for dder circuits where the crry signl my e propgted through long pth. 3. Full Adders An dder circuit cn e implemented with exclusive-or (XOR) gtes, nd crry propgtion circuit cn e implemented with AND, NAND, OR, NOR nd Inverter gtes. Figure 1. Full Adder logic circuit. The leftmost circuit is n ordinry Full Adder. The rightmost circuit is Full Adder implemented with 2-input gtes nd inverters. The ordinry full dder circuit is shown in figure 1. The circuit cn e decomposed on simple 2-input gtes. In this new decomposed circuit there re more opportunities to insert pss-trnsistor gtes. Exclusive-or gtes cn e implemented not only with conventionl sttic CMOS gtes, ut lso with pss-trnsistor logic. However, n exclusive-or gte when implemented with sttic CMOS hs significnt cost. The cost is normlly mesured in terms of trnsistors re or its dely. Also comintion of trnsistor re nd dely my e used to reflect the cost. An importnt point is tht gte must drive n output 35

3 cpcitnce under time constrint. Then lrger trnsistors re necessry to drive the output lod depending on the numer of trnsistors in series, the internl gte cpcitnces, nd the output lod. Unfortuntely, lrger trnsistors my increse re nd current consumption. An exclusive-or function cn e implemented y 2-input NAND logic circuit. A NAND gte hs importnt fetures to chieve some performnce. For exmple, NAND cn compute the output quickly. A NAND is fster thn NOR gte. A low fnout NAND cn e designed with minimum size for N nd P trnsistors. An equivlent logic expression sed on NAND opertions cn e completely generted through logic trnsformtions such s: = + =.. A sttic circuit implementtion of this expression cn e seen in figure 2. The 2-input XOR circuit sed on sttic CMOS NAND gtes hs cost of 16 trnsistors. Output Out Figure 2. A 2-input XOR circuit. The leftmost circuit is sttic CMOS version. The rightmost circuit is mixed XOR gte. A mixed CMOS PTL implementtion of XOR gte is simple. It strts with 2- input NAND pss-trnsistor gte. This gte cn e implemented y sic PMOS- NMOS pss-trnsistor structure. The rightmost circuit from figure 2 shows the psstrnsistor circuit structure. Note tht 4 pss-trnsistors re used, nd they replce 12 trnsistors used in the sttic circuit. The totl numer of trnsistors is reduced to 8, i.e., this circuit performs XOR logic function with hlf of trnsistors of the sttic version. The crry propgtion function cn e descried y the logic expression: + c + c. This expression is esily trnsformed in n equivlent expression such s:... c.. c. This lst expression is sed on NAND opertions. A CMOS sttic crry propgtion circuit cn e implemented directly. It is shown in figure 3. 36

4 Cout Figure 3. Sttic CMOS crry propgtion circuit. The mixed crry propgtion circuit is shown in figure 4. As done efore, sttic NAND gtes were replced y PMOS-NMOS pss-trnsistor structures. An input inverter is used to generte the complementry input. Note tht pss-trnsistor circuits re inserted etween sttic gtes. Unfortuntely, in the crry propgtion circuit the numer of trnsistors remins the sme for oth designs. Cout Figure 4. Mixed crry propgtion circuit. When we compre the numer of trnsistor we see tht the conventionl sttic CMOS full dder uses 54 trnsistors, nd the mixed version is implemented with 38 trnsistors. The reduction in terms of trnsistors is out 30%. 4. Experiments A 4-input full dder circuit with sttic CMOS gtes nd 4-input full dder circuit sed on mixed gtes were simulted with SPICE from Berkeley. All trnsistors hve the sme size of 1µm. All possile input vectors were used to perform the electricl 37

5 simultion. The technology employed in the simultion ws the 0.13µm from Berkeley, nd 1.5V s reference voltge. Figure 5 shows the grphicl current ehvior of the oth dder circuits. The green curve represents the current consumption of the sttic CMOS 4-input dder, nd the red curve represents the current consumption from the mixed 4-input dder. For ech it position minimum size inverter ws used s lod. The grphic shows close current curves, ut they re not equl. For this experiment the mixed dder current consumption is out 20% lower thn the conventionl sttic CMOS. When we increse the lod up to 5 times the mixed dder current consumption is out 10% lower. 4.1 Crry Propgtion Dely Figure 5. Current consumption sttic dder x mixed dder. Severl full dders were uilt with sizes of 4, 8, 12, 16, 20, 24, 28 e 32 inputs. SPICE simultions were done in order to check the crry propgtion dely. The dely ws mesured from the first crry-in it position to the lst crry-out it position. An pproprite input vector ws pplied in order to gurntee the propgtion of the crry signl. The figure 6 shows the delys for ech dder simulted. As one cn see, the mixed circuits hve lmost the sme dely when compred with the conventionl CMOS version. But, the crry dely of the mixed gtes increses when the numer of inputs increses significntly. Dely (ns) Crry- out Dely X Input its 3,9 3,6 3,3 3,0 2,7 2,4 2,1 1,8 1,5 1,2 0,9 0,6 0,3 0, Input Bits CMOS complementry Pss trnsistor logic Figure 6. Full Adder dely. 38

6 5. Conclusion This pper presented technique tht cn e useful in reducing re nd current consumption of dder circuits. Adders re logic circuits tht re used in severl pplictions, nd, therefore, design techniques le to improve some performnce re desired. This technique is le to reduce the trnsistor re in 30%, nd the reduction in terms of current consumption cn e etween 10% nd 20%. However, some dely penlty my occur for lrge dders. A possile solution is to replce the mixed crry propgtion circuit y the conventionl circuit since the numer of trnsistors is the sme, nd in this cse the trnsistor re re comprle. PMOS-NMOS pss-trnsistors cn generte signls with some electricl degrdtion. However, in the full dder design we considered this prolem. For exmple, ll PMOS pss-trnsistors re ttched to. In this cse only the NMOS trnsistor is responsile to propgte 1 nd 0 logic signls. It is very importnt ecuse the propgtion of poor signls is reduced considerly. References Scholl, C. nd Becker, B. On the Genertion of Multiplexer Circuits for Pss Trnsistor Logic. In Proc. Interntionl Workshop on Logic Synthesis, Rey, M. Jn, Chndrksn, A. nd Nikolic, B. Digitl Integrted Circuits, Second Edition. Edited y Prentice-Hll. Tvres, R. nd Berkelr, M. Reducing Switching Activity in Pss Trnsistor Circuits. In Proc. Interntionl Workshop on Logic Synthesis, Suzuki, M., Ohkuo, N., Shino, T., Ymnk, T., Shimizu, A., Sski, K. nd Nkgome, Y. A 1.5-ns 32- CMOS ALU in Doule Pss Trnsistor Logic. In IEEE Journl of Solid Stte Circuits, Vol.28, NO.11, Novemer Ynin, J., Sptnekr, S. nd Bmji, C. A Fst Glol Gte Collpsing Technique for High Performnce Designs using Sttic CMOS nd Pss Trnsistor Logic. In Proc. Interntionl Conference on Computer Design, Yng, C. nd Ciesielsky, M. Synthesis for Mixed CMOS/PTL Logic. In Proc. Interntionl Workshop on Logic Synthesis, Yno, K., Ymnk, T., Nishid, T., Sito, M., Shimohigshi, A. nd Shimizu, A. A 3.8-ns CMOS 16x16- Multiplier Using Complementry Pss-Trnsistor Logic. In IEEE Journl of Solid Stte Circuits, Vol.25, NO.2, April

CHAPTER 2 LITERATURE STUDY

CHAPTER 2 LITERATURE STUDY CHAPTER LITERATURE STUDY. Introduction Multipliction involves two bsic opertions: the genertion of the prtil products nd their ccumultion. Therefore, there re two possible wys to speed up the multipliction:

More information

Kirchhoff s Rules. Kirchhoff s Laws. Kirchhoff s Rules. Kirchhoff s Laws. Practice. Understanding SPH4UW. Kirchhoff s Voltage Rule (KVR):

Kirchhoff s Rules. Kirchhoff s Laws. Kirchhoff s Rules. Kirchhoff s Laws. Practice. Understanding SPH4UW. Kirchhoff s Voltage Rule (KVR): SPH4UW Kirchhoff s ules Kirchhoff s oltge ule (K): Sum of voltge drops round loop is zero. Kirchhoff s Lws Kirchhoff s Current ule (KC): Current going in equls current coming out. Kirchhoff s ules etween

More information

ISSCC 2006 / SESSION 21 / ADVANCED CLOCKING, LOGIC AND SIGNALING TECHNIQUES / 21.5

ISSCC 2006 / SESSION 21 / ADVANCED CLOCKING, LOGIC AND SIGNALING TECHNIQUES / 21.5 21.5 A 1.1GHz Chrge-Recovery Logic Visvesh Sthe, Jung-Ying Chueh, Mrios Ppefthymiou University of Michign, Ann Aror, MI Boost Logic is chrge-recovery circuit fmily cple of operting t GHz-clss frequencies

More information

CS 135: Computer Architecture I. Boolean Algebra. Basic Logic Gates

CS 135: Computer Architecture I. Boolean Algebra. Basic Logic Gates Bsic Logic Gtes : Computer Architecture I Boolen Algebr Instructor: Prof. Bhgi Nrhri Dept. of Computer Science Course URL: www.ses.gwu.edu/~bhgiweb/cs35/ Digitl Logic Circuits We sw how we cn build the

More information

Multi-beam antennas in a broadband wireless access system

Multi-beam antennas in a broadband wireless access system Multi-em ntenns in rodnd wireless ccess system Ulrik Engström, Mrtin Johnsson, nders Derneryd nd jörn Johnnisson ntenn Reserch Center Ericsson Reserch Ericsson SE-4 84 Mölndl Sweden E-mil: ulrik.engstrom@ericsson.com,

More information

Area-Time Efficient Digit-Serial-Serial Two s Complement Multiplier

Area-Time Efficient Digit-Serial-Serial Two s Complement Multiplier Are-Time Efficient Digit-Seril-Seril Two s Complement Multiplier Essm Elsyed nd Htem M. El-Boghddi Computer Engineering Deprtment, Ciro University, Egypt Astrct - Multipliction is n importnt primitive

More information

A COMPARISON OF CIRCUIT IMPLEMENTATIONS FROM A SECURITY PERSPECTIVE

A COMPARISON OF CIRCUIT IMPLEMENTATIONS FROM A SECURITY PERSPECTIVE A COMPARISON OF CIRCUIT IMPLEMENTATIONS FROM A SECURITY PERSPECTIVE Mster Thesis Division of Electronic Devices Deprtment of Electricl Engineering Linköping University y Timmy Sundström LITH-ISY-EX--05/3698--SE

More information

MOS Transistors. Silicon Lattice

MOS Transistors. Silicon Lattice rin n Width W chnnel p-type (doped) sustrte MO Trnsistors n Gte Length L O 2 (insultor) ource Conductor (poly) rin rin Gte nmo trnsistor Gte ource pmo trnsistor licon sustrte doped with impurities dding

More information

Design and Development of 8-Bits Fast Multiplier for Low Power Applications

Design and Development of 8-Bits Fast Multiplier for Low Power Applications IACSIT Interntionl Journl of Engineering nd Technology, Vol. 4, No. 6, Decemer 22 Design nd Development of 8-Bits Fst Multiplier for Low Power Applictions Vsudev G. nd Rjendr Hegdi, Memer, IACSIT proportionl

More information

To provide data transmission in indoor

To provide data transmission in indoor Hittite Journl of Science nd Engineering, 2018, 5 (1) 25-29 ISSN NUMBER: 2148-4171 DOI: 10.17350/HJSE19030000074 A New Demodultor For Inverse Pulse Position Modultion Technique Mehmet Sönmez Osmniye Korkut

More information

CHAPTER 3 AMPLIFIER DESIGN TECHNIQUES

CHAPTER 3 AMPLIFIER DESIGN TECHNIQUES CHAPTER 3 AMPLIFIER DEIGN TECHNIQUE 3.0 Introduction olid-stte microwve mplifiers ply n importnt role in communiction where it hs different pplictions, including low noise, high gin, nd high power mplifiers.

More information

Simulation of Transformer Based Z-Source Inverter to Obtain High Voltage Boost Ability

Simulation of Transformer Based Z-Source Inverter to Obtain High Voltage Boost Ability Interntionl Journl of cience, Engineering nd Technology Reserch (IJETR), olume 4, Issue 1, October 15 imultion of Trnsformer Bsed Z-ource Inverter to Obtin High oltge Boost Ability A.hnmugpriy 1, M.Ishwry

More information

Sequential Logic (2) Synchronous vs Asynchronous Sequential Circuit. Clock Signal. Synchronous Sequential Circuits. FSM Overview 9/10/12

Sequential Logic (2) Synchronous vs Asynchronous Sequential Circuit. Clock Signal. Synchronous Sequential Circuits. FSM Overview 9/10/12 9//2 Sequentil (2) ENGG5 st Semester, 22 Dr. Hden So Deprtment of Electricl nd Electronic Engineering http://www.eee.hku.hk/~engg5 Snchronous vs Asnchronous Sequentil Circuit This Course snchronous Sequentil

More information

Design and implementation of a high-speed bit-serial SFQ adder based on the binary decision diagram

Design and implementation of a high-speed bit-serial SFQ adder based on the binary decision diagram INSTITUTE OFPHYSICS PUBLISHING Supercond. Sci. Technol. 16 (23) 1497 152 SUPERCONDUCTORSCIENCE AND TECHNOLOGY PII: S953-248(3)67111-3 Design nd implementtion of high-speed it-seril SFQ dder sed on the

More information

Pennsylvania State University. University Park, PA only simple two or three input gates (e.g., AND/NAND,

Pennsylvania State University. University Park, PA only simple two or three input gates (e.g., AND/NAND, High-throughput nd Low-power DSP Using locked-mos ircuitry Mnjit Borh Robert Michel Owens Deprtment of omputer Science nd Engineering Pennsylvni Stte University University Prk, PA 16802 Mry Jne Irwin Abstrct

More information

Direct Current Circuits. Chapter Outline Electromotive Force 28.2 Resistors in Series and in Parallel 28.3 Kirchhoff s Rules 28.

Direct Current Circuits. Chapter Outline Electromotive Force 28.2 Resistors in Series and in Parallel 28.3 Kirchhoff s Rules 28. P U Z Z L E R If ll these pplinces were operting t one time, circuit reker would proly e tripped, preventing potentilly dngerous sitution. Wht cuses circuit reker to trip when too mny electricl devices

More information

(1) Non-linear system

(1) Non-linear system Liner vs. non-liner systems in impednce mesurements I INTRODUCTION Electrochemicl Impednce Spectroscopy (EIS) is n interesting tool devoted to the study of liner systems. However, electrochemicl systems

More information

(CATALYST GROUP) B"sic Electric"l Engineering

(CATALYST GROUP) Bsic Electricl Engineering (CATALYST GROUP) B"sic Electric"l Engineering 1. Kirchhoff s current l"w st"tes th"t (") net current flow "t the junction is positive (b) Hebr"ic sum of the currents meeting "t the junction is zero (c)

More information

Lecture 16: Four Quadrant operation of DC Drive (or) TYPE E Four Quadrant chopper Fed Drive: Operation

Lecture 16: Four Quadrant operation of DC Drive (or) TYPE E Four Quadrant chopper Fed Drive: Operation Lecture 16: Four Qudrnt opertion of DC Drive (or) TYPE E Four Qudrnt chopper Fed Drive: Opertion The rmture current I is either positive or negtive (flow in to or wy from rmture) the rmture voltge is lso

More information

Chapter 2 Literature Review

Chapter 2 Literature Review Chpter 2 Literture Review 2.1 ADDER TOPOLOGIES Mny different dder rchitectures hve een proposed for inry ddition since 1950 s to improve vrious spects of speed, re nd power. Ripple Crry Adder hve the simplest

More information

The Discussion of this exercise covers the following points:

The Discussion of this exercise covers the following points: Exercise 4 Bttery Chrging Methods EXERCISE OBJECTIVE When you hve completed this exercise, you will be fmilir with the different chrging methods nd chrge-control techniques commonly used when chrging Ni-MI

More information

High Speed On-Chip Interconnects: Trade offs in Passive Termination

High Speed On-Chip Interconnects: Trade offs in Passive Termination High Speed On-Chip Interconnects: Trde offs in Pssive Termintion Rj Prihr University of Rochester, NY, USA prihr@ece.rochester.edu Abstrct In this pper, severl pssive termintion schemes for high speed

More information

Open Access A Novel Parallel Current-sharing Control Method of Switch Power Supply

Open Access A Novel Parallel Current-sharing Control Method of Switch Power Supply Send Orders for Reprints to reprints@enthmscience.e 170 The Open Electricl & Electronic Engineering Journl, 2014, 8, 170-177 Open Access A Novel Prllel Current-shring Control Method of Switch Power Supply

More information

Geometric quantities for polar curves

Geometric quantities for polar curves Roerto s Notes on Integrl Clculus Chpter 5: Bsic pplictions of integrtion Section 10 Geometric quntities for polr curves Wht you need to know lredy: How to use integrls to compute res nd lengths of regions

More information

Homework #1 due Monday at 6pm. White drop box in Student Lounge on the second floor of Cory. Tuesday labs cancelled next week

Homework #1 due Monday at 6pm. White drop box in Student Lounge on the second floor of Cory. Tuesday labs cancelled next week Announcements Homework #1 due Mondy t 6pm White drop ox in Student Lounge on the second floor of Cory Tuesdy ls cncelled next week Attend your other l slot Books on reserve in Bechtel Hmley, 2 nd nd 3

More information

Soft switched DC-DC PWM Converters

Soft switched DC-DC PWM Converters Soft switched DC-DC PWM Converters Mr.M. Prthp Rju (), Dr. A. Jy Lkshmi () Abstrct This pper presents n upgrded soft switching technique- zero current trnsition (ZCT), which gives better turn off chrcteristics

More information

Dokic: A Review on Energy Efficient CMOS Digital Logic

Dokic: A Review on Energy Efficient CMOS Digital Logic ETASR - Engineering, Technology & Applied Science Reserch ol. 3, o. 6, 013, 55-561 55 A Review on Energy Efficient CMOS Digitl Logic Brnko L. Dokić University of Bnj Luk Fculty of Electricl Engineering

More information

Threshold Logic Computing: Memristive-CMOS Circuits for Fast Fourier Transform and Vedic Multiplication

Threshold Logic Computing: Memristive-CMOS Circuits for Fast Fourier Transform and Vedic Multiplication 1 Threshold Logic Computing: Memristive-CMOS Circuits for Fst Fourier Trnsform nd edic Multipliction Alex Pppchen Jmes, Dinesh S. Kumr, nd Arun Ajyn Abstrct Brin inspired circuits cn provide n lterntive

More information

Experiment 3: Non-Ideal Operational Amplifiers

Experiment 3: Non-Ideal Operational Amplifiers Experiment 3: Non-Idel Opertionl Amplifiers Fll 2009 Equivlent Circuits The bsic ssumptions for n idel opertionl mplifier re n infinite differentil gin ( d ), n infinite input resistnce (R i ), zero output

More information

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad

INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad Hll Ticket No Question Pper Code: AEC009 INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigl, Hyderd - 500 043 MODEL QUESTION PAPER Four Yer B.Tech V Semester End Exmintions, Novemer - 2018 Regultions:

More information

Research Letter Investigation of CMOS Varactors for High-GHz-Range Applications

Research Letter Investigation of CMOS Varactors for High-GHz-Range Applications Reserch Letters in Electronics Volume 29, Article ID 53589, 4 pges doi:1.1155/29/53589 Reserch Letter Investigtion of CMOS Vrctors for High-GHz-Rnge Applictions Ming Li, Rony E. Amy, Roert G. Hrrison,

More information

The Design and Verification of A High-Performance Low-Control-Overhead Asynchronous Differential Equation Solver

The Design and Verification of A High-Performance Low-Control-Overhead Asynchronous Differential Equation Solver he Design nd Verifiction of A High-Performnce Low-Control-Overhed Asynchronous Differentil Eqution Solver Kenneth Y. Yun, Memer, IEEE, Peter A. Beerel, Memer, IEEE, Vid Vkilotojr, Student Memer, IEEE,

More information

Experiment 3: Non-Ideal Operational Amplifiers

Experiment 3: Non-Ideal Operational Amplifiers Experiment 3: Non-Idel Opertionl Amplifiers 9/11/06 Equivlent Circuits The bsic ssumptions for n idel opertionl mplifier re n infinite differentil gin ( d ), n infinite input resistnce (R i ), zero output

More information

Automatic Synthesis of Compressor Trees: Reevaluating Large Counters

Automatic Synthesis of Compressor Trees: Reevaluating Large Counters Automtic Snthesis of Compressor Trees: Reevluting Lrge Counters Aj K. Verm AjKumr.Verm@epfl.ch Polo Ienne Polo.Ienne@epfl.ch Ecole Poltechnique Fédérle de Lusnne (EPFL) School of Computer nd Communiction

More information

Introduction. 1.1 A Brief History

Introduction. 1.1 A Brief History Introduction. Brief History In 958, Jck Kily uilt the first integrted circuit flip-flop with two trnsistors t Texs Instruments. In 28, Intel s Itnium microprocessor contined more thn 2 illion trnsistors

More information

Three-Phase Synchronous Machines The synchronous machine can be used to operate as: 1. Synchronous motors 2. Synchronous generators (Alternator)

Three-Phase Synchronous Machines The synchronous machine can be used to operate as: 1. Synchronous motors 2. Synchronous generators (Alternator) Three-Phse Synchronous Mchines The synchronous mchine cn be used to operte s: 1. Synchronous motors 2. Synchronous genertors (Alterntor) Synchronous genertor is lso referred to s lterntor since it genertes

More information

MEASURE THE CHARACTERISTIC CURVES RELEVANT TO AN NPN TRANSISTOR

MEASURE THE CHARACTERISTIC CURVES RELEVANT TO AN NPN TRANSISTOR Electricity Electronics Bipolr Trnsistors MEASURE THE HARATERISTI URVES RELEVANT TO AN NPN TRANSISTOR Mesure the input chrcteristic, i.e. the bse current IB s function of the bse emitter voltge UBE. Mesure

More information

On the Description of Communications Between Software Components with UML

On the Description of Communications Between Software Components with UML On the Description of Communictions Between Softwre Components with UML Zhiwei An Dennis Peters Fculty of Engineering nd Applied Science Memoril University of Newfoundlnd St. John s NL A1B 3X5 zhiwei@engr.mun.c

More information

Network Theorems. Objectives 9.1 INTRODUCTION 9.2 SUPERPOSITION THEOREM

Network Theorems. Objectives 9.1 INTRODUCTION 9.2 SUPERPOSITION THEOREM M09_BOYL3605_13_S_C09.indd Pge 359 24/11/14 1:59 PM f403 /204/PH01893/9780133923605_BOYLSTAD/BOYLSTAD_NTRO_CRCUT_ANALYSS13_S_978013... Network Theorems Ojectives Become fmilir with the superposition theorem

More information

Implementation of Different Architectures of Forward 4x4 Integer DCT For H.264/AVC Encoder

Implementation of Different Architectures of Forward 4x4 Integer DCT For H.264/AVC Encoder Implementtion of Different Architectures of Forwrd 4x4 Integer DCT For H.64/AVC Encoder Bunji Antoinette Ringnyu, Ali Tngel, Emre Krulut 3 Koceli University, Institute of Science nd Technology, Koceli,

More information

Fuzzy Logic Controller for Three Phase PWM AC-DC Converter

Fuzzy Logic Controller for Three Phase PWM AC-DC Converter Journl of Electrotechnology, Electricl Engineering nd Mngement (2017) Vol. 1, Number 1 Clusius Scientific Press, Cnd Fuzzy Logic Controller for Three Phse PWM AC-DC Converter Min Muhmmd Kml1,, Husn Ali2,b

More information

MAXIMUM FLOWS IN FUZZY NETWORKS WITH FUNNEL-SHAPED NODES

MAXIMUM FLOWS IN FUZZY NETWORKS WITH FUNNEL-SHAPED NODES MAXIMUM FLOWS IN FUZZY NETWORKS WITH FUNNEL-SHAPED NODES Romn V. Tyshchuk Informtion Systems Deprtment, AMI corportion, Donetsk, Ukrine E-mil: rt_science@hotmil.com 1 INTRODUCTION During the considertion

More information

A New Algorithm to Compute Alternate Paths in Reliable OSPF (ROSPF)

A New Algorithm to Compute Alternate Paths in Reliable OSPF (ROSPF) A New Algorithm to Compute Alternte Pths in Relile OSPF (ROSPF) Jin Pu *, Eric Mnning, Gholmli C. Shoj, Annd Srinivsn ** PANDA Group, Computer Science Deprtment University of Victori Victori, BC, Cnd Astrct

More information

Regular languages can be expressed as regular expressions.

Regular languages can be expressed as regular expressions. Regulr lnguges cn e expressed s regulr expressions. A generl nondeterministic finite utomton (GNFA) is kind of NFA such tht: There is unique strt stte nd is unique ccept stte. Every pir of nodes re connected

More information

Alternating-Current Circuits

Alternating-Current Circuits chpter 33 Alternting-Current Circuits 33.1 AC Sources 33.2 esistors in n AC Circuit 33.3 Inductors in n AC Circuit 33.4 Cpcitors in n AC Circuit 33.5 The LC Series Circuit 33.6 Power in n AC Circuit 33.7

More information

Application Note. Differential Amplifier

Application Note. Differential Amplifier Appliction Note AN367 Differentil Amplifier Author: Dve n Ess Associted Project: Yes Associted Prt Fmily: CY8C9x66, CY8C7x43, CY8C4x3A PSoC Designer ersion: 4. SP3 Abstrct For mny sensing pplictions, desirble

More information

Use of compiler optimization of software bypassing as a method to improve energy efficiency of exposed data path architectures

Use of compiler optimization of software bypassing as a method to improve energy efficiency of exposed data path architectures Guzm et l. EURASIP Journl on Emedded Systems 213, 213:9 RESEARCH Open Access Use of compiler optimiztion of softwre ypssing s method to improve energy efficiency of exposed dt pth rchitectures Vldimír

More information

Asynchronous Data-Driven Circuit Synthesis

Asynchronous Data-Driven Circuit Synthesis Asynchronous Dt-Driven Circuit Synthesis Sm Tylor, Doug Edwrds, Luis A Pln, Senior Memer, IEEE nd Luis A. Trzon D., Student Memer, IEEE Astrct A method is descried for synthesising synchronous circuits

More information

Timing Macro-modeling of IP Blocks with Crosstalk

Timing Macro-modeling of IP Blocks with Crosstalk Timing Mcro-modeling of IP Blocks with Crosstlk Ruiming Chen nd Hi Zhou Electricl nd Computer Engineering Northwestern Universit Evnston, IL 60208 Astrct With the increse of design compleities nd the decrese

More information

Dataflow Language Model. DataFlow Models. Applications of Dataflow. Dataflow Languages. Kahn process networks. A Kahn Process (1)

Dataflow Language Model. DataFlow Models. Applications of Dataflow. Dataflow Languages. Kahn process networks. A Kahn Process (1) The slides contin revisited mterils from: Peter Mrwedel, TU Dortmund Lothr Thiele, ETH Zurich Frnk Vhid, University of liforni, Riverside Dtflow Lnguge Model Drsticlly different wy of looking t computtion:

More information

& Y Connected resistors, Light emitting diode.

& Y Connected resistors, Light emitting diode. & Y Connected resistors, Light emitting diode. Experiment # 02 Ojectives: To get some hndson experience with the physicl instruments. To investigte the equivlent resistors, nd Y connected resistors, nd

More information

Control of high-frequency AC link electronic transformer

Control of high-frequency AC link electronic transformer Control of high-frequency AC link electronic trnsformer H. Krishnswmi nd V. Rmnrynn Astrct: An isolted high-frequency link AC/AC converter is termed n electronic trnsformer. The electronic trnsformer hs

More information

A Practical DPA Countermeasure with BDD Architecture

A Practical DPA Countermeasure with BDD Architecture A Prcticl DPA Countermesure with BDD Architecture Toru Akishit, Msnou Ktgi, Yoshikzu Miyto, Asmi Mizuno, nd Kyoji Shiutni System Technologies Lortories, Sony Corportion, -7- Konn, Minto-ku, Tokyo 8-75,

More information

Lab 8. Speed Control of a D.C. motor. The Motor Drive

Lab 8. Speed Control of a D.C. motor. The Motor Drive Lb 8. Speed Control of D.C. motor The Motor Drive Motor Speed Control Project 1. Generte PWM wveform 2. Amplify the wveform to drive the motor 3. Mesure motor speed 4. Mesure motor prmeters 5. Control

More information

CVM-B100 CVM-B150. Power analyzers for panel

CVM-B100 CVM-B150. Power analyzers for panel Power nlyzers CVM-150 Power nlyzers for pnel Description The nd CVM-150 units re pnel mounted three-phse power nlyzers (dimensions: x nd 144x144 mm, respectively). oth offer 4-qudrnt mesurement (consumption

More information

Two-layer slotted-waveguide antenna array with broad reflection/gain bandwidth at millimetre-wave frequencies

Two-layer slotted-waveguide antenna array with broad reflection/gain bandwidth at millimetre-wave frequencies Two-lyer slotted-wveguide ntenn rry with rod reflection/gin ndwidth t millimetre-wve frequencies S.-S. Oh, J.-W. Lee, M.-S. Song nd Y.-S. Kim Astrct: A 24 24 slotted-wveguide rry ntenn is presented in

More information

Discontinued AN6262N, AN6263N. (planed maintenance type, maintenance type, planed discontinued typed, discontinued type)

Discontinued AN6262N, AN6263N. (planed maintenance type, maintenance type, planed discontinued typed, discontinued type) ICs for Cssette, Cssette Deck ANN, ANN Puse Detection s of Rdio Cssette, Cssette Deck Overview The ANN nd the ANN re the puse detection integrted circuits which select the progrm on the cssette tpe. In

More information

Transformerless Three-Level DC-DC Buck Converter with a High Step-Down Conversion Ratio

Transformerless Three-Level DC-DC Buck Converter with a High Step-Down Conversion Ratio 7 Journl of Power Electronics, Vol. 13, No. 1, Jnury 213 JPE 13-1-8 http://dx.doi.org/1.6113/jpe.213.13.1.7 rnsformerless hree-level DC-DC Buck Converter with High Step-Down Conversion tio Yun Zhng, Xing-to

More information

ABB STOTZ-KONTAKT. ABB i-bus EIB Current Module SM/S Intelligent Installation Systems. User Manual SM/S In = 16 A AC Un = 230 V AC

ABB STOTZ-KONTAKT. ABB i-bus EIB Current Module SM/S Intelligent Installation Systems. User Manual SM/S In = 16 A AC Un = 230 V AC User Mnul ntelligent nstlltion Systems A B 1 2 3 4 5 6 7 8 30 ma 30 ma n = AC Un = 230 V AC 30 ma 9 10 11 12 C ABB STOTZ-KONTAKT Appliction Softwre Current Vlue Threshold/1 Contents Pge 1 Device Chrcteristics...

More information

Experiment 8 Series DC Motor (II)

Experiment 8 Series DC Motor (II) Ojectives To control the speed of loded series dc motor y chnging rmture voltge. To control the speed of loded series dc motor y dding resistnce in prllel with the rmture circuit. To control the speed

More information

A Development of Earthing-Resistance-Estimation Instrument

A Development of Earthing-Resistance-Estimation Instrument A Development of Erthing-Resistnce-Estimtion Instrument HITOSHI KIJIMA Abstrct: - Whenever erth construction work is done, the implnted number nd depth of electrodes hve to be estimted in order to obtin

More information

5 I. T cu2. T use in modem computing systems, it is desirable to. A Comparison of Half-Bridge Resonant Converter Topologies

5 I. T cu2. T use in modem computing systems, it is desirable to. A Comparison of Half-Bridge Resonant Converter Topologies 74 EEE TRANSACTONS ON POER ELECTRONCS, VOL. 3, NO. 2, APRL 988 A Comprison of Hlf-Bridge Resonnt Converter Topologies Abstrct-The hlf-bridge series-resonnt, prllel-resonnt, nd combintion series-prllel

More information

DIGITAL multipliers [1], [2] are the core components of

DIGITAL multipliers [1], [2] are the core components of World Acdemy of Science, Engineering nd Technology 9 8 A Reduced-Bit Multipliction Algorithm for Digitl Arithmetic Hrpreet Singh Dhillon nd Ahijit Mitr Astrct A reduced-it multipliction lgorithm sed on

More information

Back to the Future: Digital Circuit Design in the FinFET Era

Back to the Future: Digital Circuit Design in the FinFET Era Copyright 2017 Americn Scientific Pulishers All rights reserved Printed in the United Sttes of Americ Journl of Low Power Electronics Vol. 13, 1 18, 2017 Bck to the Future: Digitl Circuit Design in the

More information

Design of a Pipelined DSP Microprocessor MUN DSP2000

Design of a Pipelined DSP Microprocessor MUN DSP2000 Design of Pipeline DSP icroprocessor N DSP2000 Cheng Li, Lu io, Qiyo Yu, P.Gillr n R.Venktesn Fculty of Engineering n Applie Science emoril niversity of Newfounln St. John s, NF, Cn A1B 3 E-mil: {licheng,

More information

Modeling of Conduction and Switching Losses in Three-Phase Asymmetric Multi-Level Cascaded Inverter

Modeling of Conduction and Switching Losses in Three-Phase Asymmetric Multi-Level Cascaded Inverter Proceedings of the 5th WEA nt. onf. on Power ystems nd Electromgnetic omptibility, orfu, Greece, August 23-25, 2005 (pp176-181) Modeling of onduction nd witching Losses in Three-Phse Asymmetric Multi-Level

More information

Logic Design of Elementary Functional Operators in Quaternary Algebra

Logic Design of Elementary Functional Operators in Quaternary Algebra Interntionl Journl of Computer Theory nd Engineering, Vol. 8, No. 3, June 206 Logic Design of Elementry unctionl Opertors in Quternry Alger Asif iyz, Srh Nhr Chowdhury, nd Khndkr Mohmmd Ishtik Astrct Multivlued

More information

Localization of Latent Image in Heterophase AgBr(I) Tabular Microcrystals

Localization of Latent Image in Heterophase AgBr(I) Tabular Microcrystals Interntionl ymposium on ilver Hlide Technology Locliztion of Ltent Imge in Heterophse AgBr(I) Tulr Microcrystls Elen V. Prosvirkin, Aigul B. Aishev, Timothy A. Lrichev, Boris A. echkrev Kemerovo tte University,

More information

DP4T RF CMOS Switch: A Better Option to Replace the SPDT Switch and DPDT Switch

DP4T RF CMOS Switch: A Better Option to Replace the SPDT Switch and DPDT Switch Send Orders of Reprints t reprints@enthmscience.org 244 Recent Ptents on Electricl & Electronic Engineering 2012, 5, 244-248 DP4T RF CMOS Switch: A Better Option to Replce the SPDT Switch nd DPDT Switch

More information

A New Stochastic Inner Product Core Design for Digital FIR Filters

A New Stochastic Inner Product Core Design for Digital FIR Filters MATEC Web of Conferences, (7) DOI:./ mtecconf/7 CSCC 7 A New Stochstic Inner Product Core Design for Digitl FIR Filters Ming Ming Wong,, M. L. Dennis Wong, Cishen Zhng, nd Ismt Hijzin Fculty of Engineering,

More information

EE Controls Lab #2: Implementing State-Transition Logic on a PLC

EE Controls Lab #2: Implementing State-Transition Logic on a PLC Objective: EE 44 - Controls Lb #2: Implementing Stte-rnsition Logic on PLC ssuming tht speed is not of essence, PLC's cn be used to implement stte trnsition logic. he dvntge of using PLC over using hrdwre

More information

A Novel Back EMF Zero Crossing Detection of Brushless DC Motor Based on PWM

A Novel Back EMF Zero Crossing Detection of Brushless DC Motor Based on PWM A ovel Bck EMF Zero Crossing Detection of Brushless DC Motor Bsed on PWM Zhu Bo-peng Wei Hi-feng School of Electricl nd Informtion, Jingsu niversity of Science nd Technology, Zhenjing 1003 Chin) Abstrct:

More information

Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures

Subword Permutation Instructions for Two-Dimensional Multimedia Processing in MicroSIMD Architectures Suword Permuttion Instructions for Two-Dimensionl Multimedi Processing in MicroSIMD rchitectures Ruy. Lee Princeton University rlee@ee.princeton.edu strct MicroSIMD rchitectures incorporting suword prllelism

More information

Experimental Application of H Output-Feedback Controller on Two Links of SCARA Robot

Experimental Application of H Output-Feedback Controller on Two Links of SCARA Robot INTERNATIONAL JOURNAL OF CONTROL, AUTOMATION AND SYSTEMS VOL.5 NO. Jnury 6 ISSN 65-877 (Print) ISSN 65-885 (Online) http://www.reserchpu.org/journl/jc/jc.html Experimentl Appliction of H Output-Feedck

More information

Design And Implementation Of Luo Converter For Electric Vehicle Applications

Design And Implementation Of Luo Converter For Electric Vehicle Applications Design And Implementtion Of Luo Converter For Electric Vehicle Applictions A.Mnikndn #1, N.Vdivel #2 ME (Power Electronics nd Drives) Deprtment of Electricl nd Electronics Engineering Sri Shkthi Institute

More information

Improved Ensemble Empirical Mode Decomposition and its Applications to Gearbox Fault Signal Processing

Improved Ensemble Empirical Mode Decomposition and its Applications to Gearbox Fault Signal Processing IJCSI Interntionl Journl of Computer Science Issues, Vol. 9, Issue, No, Novemer ISSN (Online): 9- www.ijcsi.org 9 Improved Ensemle Empiricl Mode Decomposition nd its Applictions to Gerox Fult Signl Processing

More information

This is a repository copy of Four-port diplexer for high Tx/Rx isolation for integrated transceivers.

This is a repository copy of Four-port diplexer for high Tx/Rx isolation for integrated transceivers. This is repository copy of Four-port diplexer for high Tx/Rx isoltion for integrted trnsceivers. White Rose Reserch Online URL for this pper: http://eprints.whiterose.c.uk/124000/ Version: Accepted Version

More information

Electronic Circuits I - Tutorial 03 Diode Applications I

Electronic Circuits I - Tutorial 03 Diode Applications I Electronic Circuits I - Tutoril 03 Diode Applictions I -1 / 9 - T & F # Question 1 A diode cn conduct current in two directions with equl ese. F 2 When reverse-bised, diode idelly ppers s short. F 3 A

More information

POWER QUALITY IMPROVEMENT BY SRF BASED CONTROL USING DYNAMIC VOLTAGE RESTORER (DVR)

POWER QUALITY IMPROVEMENT BY SRF BASED CONTROL USING DYNAMIC VOLTAGE RESTORER (DVR) Interntionl Journl of Electricl Engineering & Technology (IJEET) Volume 9, Issue 1, Jn-Fe 2018, pp. 51 57, rticle ID: IJEET_09_01_005 ville online t http://www.ieme.com/ijeet/issues.sp?jtype=ijeet&vtype=9&itype=1

More information

FPGA Based Five-Phase Sinusoidal PWM Generator

FPGA Based Five-Phase Sinusoidal PWM Generator 22 IEEE Interntionl Conference on Power nd Energy (PECon), 25 Decemer 22, Kot Kinlu Sh, Mlysi FPGA Bsed FivePhse Sinusoidl PWM Genertor Tole Sutikno Dept. of Electricl Engineering Universits Ahmd Dhln

More information

Three-Phase NPC Inverter Using Three-Phase Coupled Inductor

Three-Phase NPC Inverter Using Three-Phase Coupled Inductor ThreePhse NPC Inverter Using ThreePhse Coupled Inductor Romeu Husmnn 1, Rodrigo d Silv 2 nd Ivo Brbi 2 1 Deprtment of Electricl nd Telecommuniction Engineering, University of Blumenu FURB Blumenu SC Brzil,

More information

ECE 274 Digital Logic. Digital Design. Datapath Components Shifters, Comparators, Counters, Multipliers Digital Design

ECE 274 Digital Logic. Digital Design. Datapath Components Shifters, Comparators, Counters, Multipliers Digital Design ECE 27 Digitl Logic Shifters, Comprtors, Counters, Multipliers Digitl Design..7 Digitl Design Chpter : Slides to ccompny the textbook Digitl Design, First Edition, by Frnk Vhid, John Wiley nd Sons Publishers,

More information

Device installation. AFR 1xx - Feature Description of the Smart Load. AFR1xx 145 % 200 %

Device installation. AFR 1xx - Feature Description of the Smart Load. AFR1xx 145 % 200 % KM systems, s.r.o. Dr. M. Horákové 559, 460 06 Lierec 7, Czech Repulic tel. +420 485 130 314, fx +420 482 736 896 emil : km@km.cz, url : www.km.cz sturtion of the mgnetic circuit of the VT. This often

More information

A Simple Approach to Control the Time-constant of Microwave Integrators

A Simple Approach to Control the Time-constant of Microwave Integrators 5 VOL., NO.3, MA, A Simple Approch to Control the Time-constnt of Microwve Integrtors Dhrmendr K. Updhyy* nd Rkesh K. Singh NSIT, Division of Electronics & Communiction Engineering New Delhi-78, In Tel:

More information

Solutions to exercise 1 in ETS052 Computer Communication

Solutions to exercise 1 in ETS052 Computer Communication Solutions to exercise in TS52 Computer Communiction 23 Septemer, 23 If it occupies millisecond = 3 seconds, then second is occupied y 3 = 3 its = kps. kps If it occupies 2 microseconds = 2 6 seconds, then

More information

Exercise 1-1. The Sine Wave EXERCISE OBJECTIVE DISCUSSION OUTLINE. Relationship between a rotating phasor and a sine wave DISCUSSION

Exercise 1-1. The Sine Wave EXERCISE OBJECTIVE DISCUSSION OUTLINE. Relationship between a rotating phasor and a sine wave DISCUSSION Exercise 1-1 The Sine Wve EXERCISE OBJECTIVE When you hve completed this exercise, you will be fmilir with the notion of sine wve nd how it cn be expressed s phsor rotting round the center of circle. You

More information

THE present trends in the development of integrated circuits

THE present trends in the development of integrated circuits On-chip Prmetric Test of -2 Ldder Digitl-to-Anlog Converter nd Its Efficiency Dniel Arbet, Vier Stopjková, Jurj Brenkuš, nd Gábor Gyepes Abstrct This pper dels with the investigtion of the fult detection

More information

Math Circles Finite Automata Question Sheet 3 (Solutions)

Math Circles Finite Automata Question Sheet 3 (Solutions) Mth Circles Finite Automt Question Sheet 3 (Solutions) Nickols Rollick nrollick@uwterloo.c Novemer 2, 28 Note: These solutions my give you the nswers to ll the prolems, ut they usully won t tell you how

More information

AN ELECTRON SWITCH. by C. DORSMAN and S. L. de BRUIN.

AN ELECTRON SWITCH. by C. DORSMAN and S. L. de BRUIN. SEPTEMBER 1939 267 AN ELECTRON SWITCH y C. DORSMAN nd S. L. de BRUIN. 621.317.755.06 An pprtus is descried with which the time function of two different mgnitudes cn e oserved simultneouslyon the fluorescent

More information

Understanding Basic Analog Ideal Op Amps

Understanding Basic Analog Ideal Op Amps Appliction Report SLAA068A - April 2000 Understnding Bsic Anlog Idel Op Amps Ron Mncini Mixed Signl Products ABSTRACT This ppliction report develops the equtions for the idel opertionl mplifier (op mp).

More information

Computing Logic-Stage Delays Using Circuit Simulation and Symbolic Elmore Analysis

Computing Logic-Stage Delays Using Circuit Simulation and Symbolic Elmore Analysis Computing Logic-Stge Delys Using Circuit Simultion nd Symolic Elmore Anlysis Clyton B. McDonld Rndl E. Brynt Deprtment of Electricl nd Computer Engineering Crnegie Mellon University, Pittsurgh, PA 15213

More information

10.4 AREAS AND LENGTHS IN POLAR COORDINATES

10.4 AREAS AND LENGTHS IN POLAR COORDINATES 65 CHAPTER PARAMETRIC EQUATINS AND PLAR CRDINATES.4 AREAS AND LENGTHS IN PLAR CRDINATES In this section we develop the formul for the re of region whose oundry is given y polr eqution. We need to use the

More information

Safety Relay Unit. Main contacts Auxiliary contact Number of input channels Rated voltage Model Category. possible 24 VAC/VDC G9SA-501.

Safety Relay Unit. Main contacts Auxiliary contact Number of input channels Rated voltage Model Category. possible 24 VAC/VDC G9SA-501. Sfety Rely Unit The Series Offers Complete Line-up of Compct Units. Four kinds of -mm wide Units re ville: A -pole model, -pole model, nd models with poles nd OFF-dely poles, s well s Two-hnd ler. Simple

More information

Investigation of propagation of partial discharges in power transformers and techniques for locating the discharge

Investigation of propagation of partial discharges in power transformers and techniques for locating the discharge Investigtion of propgtion of prtil dischrges in power trnsformers nd techniques for locting the dischrge S.N. Hettiwtte, Z.D. Wng nd P.A. Crossley Astrct: The loction of prtil dischrges in power trnsformer

More information

Module 9. DC Machines. Version 2 EE IIT, Kharagpur

Module 9. DC Machines. Version 2 EE IIT, Kharagpur Module 9 DC Mchines Version EE IIT, Khrgpur esson 40 osses, Efficiency nd Testing of D.C. Mchines Version EE IIT, Khrgpur Contents 40 osses, efficiency nd testing of D.C. mchines (esson-40) 4 40.1 Gols

More information

Design Techniques for Low Power High Bandwidth Upconversion in CMOS

Design Techniques for Low Power High Bandwidth Upconversion in CMOS Design Techniques for Low Power High Bndwidth Upconversion in CMOS Crl De Rnter crl.dernter@ieee.org Ktholieke Universiteit Leuven Dept. Elektrotechniek, fd. ESAT-MICAS Ksteelprk Arenerg 10 B-3001 Leuven,

More information

Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses

Eliminating Non-Determinism During Test of High-Speed Source Synchronous Differential Buses Eliminting Non-Determinism During of High-Speed Source Synchronous Differentil Buses Abstrct The t-speed functionl testing of deep sub-micron devices equipped with high-speed I/O ports nd the synchronous

More information

Calculation of Leakage Current in CMOS Circuit Design in DSM Technology

Calculation of Leakage Current in CMOS Circuit Design in DSM Technology Interntionl Journl of Coputer Applictions (75 8887) Volue 155 No 11, Deceer 2016 Clcultion of Lekge Current in CMOS Circuit Design in DSM Technology Shy Mni Pndey Tru College of Science nd Technology Bhopl,

More information

All-optical busbar differential protection scheme for electric power systems

All-optical busbar differential protection scheme for electric power systems All-opticl usr differentil protection scheme for electric power systems M Nsir +, A Dysko, P. Niewczs, G Fusiek Institute for Energy nd Environment, Electronic nd Electricl Enginering Deprtment. University

More information

Section 2.2 PWM converter driven DC motor drives

Section 2.2 PWM converter driven DC motor drives Section 2.2 PWM converter driven DC motor drives 2.2.1 Introduction Controlled power supply for electric drives re obtined mostly by converting the mins AC supply. Power electronic converter circuits employing

More information