# CHAPTER 2 LITERATURE STUDY

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1 CHAPTER LITERATURE STUDY. Introduction Multipliction involves two bsic opertions: the genertion of the prtil products nd their ccumultion. Therefore, there re two possible wys to speed up the multipliction: reduce the number of prtil products or ccelerte their ccumultion [5]. A smller number of prtil products lso reduces the compleity, nd s result, reduces the time needed to ccumulte the prtil products. Both solutions cn be pplied simultneously.. High Speed Multiplier.. Arry Multiplier [6] The rry multiplier origintes from the multipliction prllelogrm. As shown in Figure., ech stge of the prllel dders should receive some prtil product inputs. The crry-out is propgted into the net row. The bold line is the criticl pth of the multiplier. In non-pipelined rry multiplier, ll of the prtil products re generted t the sme time. It is observed tht the criticl pth consists of two prts: verticl nd horizontl. Both hve the sme dely in terms of full dder delys nd gte delys. For n n-bit by n-bit rry multiplier, the verticl nd the horizontl delys re both the sme s the dely of n n-bit full dder.

2 Figure. : -bits -bits Arry Multiplier [6] One dvntge of the rry multiplier comes from its regulr structure. Since it is regulr, it is esy to lyout nd hs smll size. The design time of n rry multiplier is much less thn tht of tree multiplier. A second dvntge of the rry multiplier is its ese of design for pipelined rchitecture. The min disdvntge of the rry multiplier is the worst-cse dely of the multiplier proportionl to the width of the multiplier. The speed will be slow for very wide multiplier... Tree Multiplier In the multiplier bsed on Wllce tree, the multiplicnd-multiples re summed up in prllel by mens of tree of crry sve dders. A Crry Sve Adder sums up three binry numbers nd produces two binry numbers [6]. Figure. illustrtes block digrm of multiplier bsed on Wllce tree. This consists of full dders, just like the rry multiplier. 5

3 Figure. : A Multiplier with Wllce Tree [6] One dvntge of the Wllce tree is it hs smll dely. The number of logic levels required to perform the summtion cn be reduced with Wllce tree. The min disdvntges of Wllce tree is comple to lyout nd hs irregulr wires []... Booth Multiplier The modified Booth recoding lgorithm is the most frequently used method to generte prtil products [8]. This lgorithm llows for the reduction of the number of prtil products to be compressed in crry-sve dder tree. Thus the compression speed cn be enhnced. This Booth Mc Sorley lgorithm is simply clled the Booth lgorithm, nd the two-bit recoding using this lgorithm scns triplet of bits to reduce the number of prtil products by roughly one hlf. The -bit recoding mens tht the multiplier B is divided into groups of two bits, nd the lgorithm is pplied to this group of divided bits. The Booth lgorithm is implemented into two steps: Booth encoding nd Booth selecting. The Booth encoding step is to generte one of the five vlues from the 6

4 djcent three bits. The Booth selector genertes prtil product bit by utilizing the output signls. One dvntge of the Booth multiplier is, it reduce the number of prtil product, thus mke it etensively used in multiplier with long opernds (>6 bits) [7]. The min disdvntge of Booth multiplier is the compleity of the circuit to generte prtil product bit in the Booth encoding [9].. Modified Bugh-Wooley Two s Complement Signed Multiplier.. Two's Complement System [5] Two's complement is the most populr method of representing signed integers in computer science. It is lso n opertion of negtion (converting positive to negtive numbers or vice vers) in computers which represent negtive numbers using two's complement. Its use is ubiquitous tody becuse it does not require the ddition nd subtrction circuitry to emine the signs of the opernds to determine whether to dd or subtrct, mking it both simpler to implement nd cpble of esily hndling higher precision rithmetic. Two s complement nd one s complement representtions re commonly used since rithmetic units re simpler to design. Figure., shows two s complement nd one s complement representtions. Figure. : Two s Complement nd One s Complement Representtions 7

5 In n n-bit binry number, the most significnt bit is usully the n s plce. But in the two's complement representtion, its plce vlue is negted; it becomes the n s plce nd is clled the sign bit. If the sign bit is, the vlue is positive; if it is, the vlue is negtive. To negte two's complement number, invert ll the bits then dd to the result. If ll bits re, the vlue is. If the sign bit is but the rest of the bits re, the vlue is the most negtive number, n for n n-bit number. The bsolute vlue of the most negtive number cnnot be represented with the sme number of bits becuse it is greter thn the most positive number tht two's complement number by ectly. A two's complement 8-bits binry numerl cn represent every integer in the rnge 8 to +7. If the sign bit is, then the lrgest vlue tht cn be stored in the remining seven bits is 7, or 7. Using two's complement to represent negtive numbers llows only one representtion of zero, nd to hve effective ddition nd subtrction while still hving the most significnt bit s the sign bit... Modified Bugh-Wooley Two s Complement Signed Multiplier One importnt compliction in the development of the efficient multiplier implementtions is the multipliction of two s complement signed numbers. The Modified Bugh-Wooley Two s Complement Signed Multiplier is the best known lgorithm for signed multipliction becuse it mimizes the regulrity of the multiplier logic nd llows ll the prtil products to hve positive sign bits []. 8

6 Bugh-Wooley technique ws developed to design direct multipliers for two s complement numbers [9]. When multiplying two s complement numbers directly, ech of the prtil products to be dded is signed number. Thus, ech prtil product hs to be sign-etended to the width of the finl product in order to form the correct sum by the Crry Sve Adder tree. According to the Bugh- Wooley pproch, n efficient method of dding etr entries to the bit mtri is suggested to void hving to del with the negtively weighted bits in the prtil product mtri. In Figure. prtil product rry s of 5-bits 5-bits unsigned bit re shown below : Figure. : Unsigned Multipliction [9] Prtil product rry s of two s complement multipliction of 5-bits 5- bits re shown in Figure.5 : Figure.5 : Two s Complement Multipliction [9] 9

7 Here is how the lgorithm works. Knowing tht the sign bit in two s complement numbers hs negtive weight, the entry the term cn be written in terms of. = ( ) = (.) Hence, the term is replced with nd. If is used insted of, the column sum increses by. Thus, must be inserted in the net higher column in order to compenste the effect of. The sme is done for nd. In ech column, nd cncel, ech other out. The p column gets entry, which is replceble by. 8 This cn be repeted for ll entries, yielding to the insertion of in the p column, nd p 8 in the column. There re two - s in the eighth column now, which is equivlent to - entry in p 9 nd tht cn be replced wit nd borrow into the non-eisting tenth column. Bugh-Wooley method increses the height of the longest column by two, which my led to greter dely through the Crry Sve Adder tree. In the given emple of Figure.6 column height chnges from 5 to 7, requiring n etr Crry Sve Adder level p p p p p p p p p p c. Bugh-Wooley Figure.6 : Bugh-Wooley Two s Complement Signed Multipliction [9]

8 Removing from fourth column nd writing two entries in the third column, which hs only four entries, cn reduce the etr dely cused by the dditionl Crry Sve Adder level. Thus, the mimum number of entries in one column becomes si, which cn be implemented with three level Crry Sve Adder tree. All negtively weighted terms cn be trnsferred to the bottom row, which leds to two negtive numbers in the lst two rows, where subtrction opertion from the sum of ll the positive elements is necessry. Insted of subtrcting two s complement of cn be dded times. This method is known s the Modified Bugh-Wooley lgorithm s shown in Figure p p p p p p p p p p d. Modified B-W Figure.7 : Modified Bugh-Wooley Two s Complement Signed Multipliction Modified form of the Bugh-Wooley method, is more preferble since it does not increse the height of the columns in the mtri. However, this type of multiplier is suitble for pplictions where opernds with less thn bits re processed, like digitl filters where smll opernds like 6, 8, nd 6 bits re used. Bugh-Wooley scheme becomes slow nd re consuming when opernds re greter thn or equl to bits.

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