Sequential Logic (2) Synchronous vs Asynchronous Sequential Circuit. Clock Signal. Synchronous Sequential Circuits. FSM Overview 9/10/12


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1 9//2 Sequentil (2) ENGG5 st Semester, 22 Dr. Hden So Deprtment of Electricl nd Electronic Engineering Snchronous vs Asnchronous Sequentil Circuit This Course snchronous Sequentil snchronous Comintionl n In snchronous sequentil circuits, ll stte elements re updted snchronousl ccording to single clock signl n In snchronous sequentil circuits, stte elements m e updted with multiple clocks, no clock signl, or n other schemes. st semester, 22 ENGG5  H. So 2 input Snchronous Sequentil Circuits n A snchronous sequentil circuit contins exctl clock signl n All stte elements re connected to the sme clock signl è the stte of the entire circuit is updted t the sme time n Common form of snchronous sequentil circuits: Com Com Com Com output Clock Signl n A clock signl is prticulrl importnt signl in snchronous sequentil circuit It controls the ction of ll DFFs n A clock signl toggles etween nd periodicll n The frequenc of the toggling determines the mximum speed of the circuit E.g.: in the ccumultor exmple erlier, the output S cnnot chnge fster thn the clock frequenc X x x x2 S x x + x x + x + x2 clock period = clock frequenc clock period e.g. Intel CPU runs t 3 GHz, Moile phone processors t GHz L FPGA ord t 5 MHz st semester, 22 ENGG5  H. So 3 st semester, 22 ENGG5  H. So 4 FSM Overview FINITE STATE MACHINE n Finite Stte Mchine (FSM) is n strction of computtion Cn e used to model mn computing tsks, oth in softwre nd in hrdwre n Ver useful strction to help design sequentil circuits It is sstemtic, nd cn e nlzed mthemticll n Used to descrie ver complex ehvior of circuits nd sstems Decision mking Network communiction Microprocessor control st semester, 22 ENGG5  H. So 5 st semester, 22 ENGG5  H. So 6
2 9//2 Defining Finite Stte Mchines n Ech FSM defines: Finite numer of sttes tht the mchine cn e in The conditions under which it will trnsition from one stte to nother n At n moment in time, n FSM cn onl exist in of the defined sttes n The output of n FSM depends on the stte tht the FSM Optionll depend on the input to the FSM Stte Trnsition Digrm n A grphicl tool to descrie the ehvior of n FSM n Represent sttes s locks Leled: nme of the stte n Represent trnsitions s directed edge Direction of n edge represents the direction of stte trnsition n All possile sttes & trnsitions re included S3 S S2 S st semester, 22 ENGG5  H. So 7 st semester, 22 ENGG5  H. So 8 Quick Quiz Stte Trnsitions n Which of the following is/ re possile sequence(s) of sttes tht the FSM m go through? S S condition / output S S S S3 S2 S 2 S S S S2 S2 S 3 S S S S S3 S3 S3 4 S2 S2 S S S S S3 S2 S n Ech stte trnsition is leled with:. Condition tht the trnsition should tke plce 2. Output of the FSM during the trnsition n There should onl e ctive trnsition t n one time The input conditions of ll trnsitions in FSM should e mutull exclusive st semester, 22 ENGG5  H. So 9 st semester, 22 ENGG5  H. So Ex: Ticket Gte t MTR n The gte should onl open fter vlid Octopus crd is scnned. n It should close the gte fter person hs pssed through the gte. FSM in Hrdwre n FSM cn e efficientl implemented in hrdwre using snchronous sequentil circuits FSM sttes cn e implemented registers Stte trnsition conditions cn e implemented comintionl function on input signls nd the sttes FSM outputs re simpl output signls of the circuit n Trnsition condition is checked on ever clock edge st semester, 22 ENGG5  H. So st semester, 22 ENGG5  H. So 2 2
3 9//2 Ticket Gte Control () Ticket Gte Control (2) Step : Define the input/output signls n We use the following signls: Tpe Nme Description input vlid if vlid Octopus crd is presented, otherwise input pssed if pssenger hs completel pssed through the gte, otherwise output motor close the ticket gte turning on motor, otherwise st semester, 22 ENGG5  H. So 3 Step 2: Determine how the FSM sttes will e represented in hrdwre n 2 FSM sttes è DFF needed n Encode the stte s follows: è stte è stte st semester, 22 ENGG5  H. So 4 Ticket Gte Control (3) Step 3: Implement the stte trnsition logic n At ech ccle, determine wht is the next stte this FSM should e in in the next ccle Determine which trnsition is ctive checking ll the trnsition conditions n The next stte logic is comintionl function of the current stte nd the input signls the input to the stte register Cn e found using truth tle st semester, 22 ENGG5  H. So 5 Ticket Gte Control (3) ns = s vlid + s pssed s vlid pssed ns st semester, 22 ENGG5  H. So 6 Ticket Gte Control (4) Ticket Gte Control (4) Step 4: Determine the output logic n Cn e performed similr to the w the next stte logic is otined st semester, 22 ENGG5  H. So 7 motor = s vlid + s pssed s vlid pssed ns motor st semester, 22 ENGG5  H. So 8 3
4 9//2 Ticket Gte Control (5) Moore Mchine vs Mel Mchine Step 4: Implement the circuit input s Next Stte ns stte register s Output output n In Mel mchine, the output depends on oth input nd the current stte of the mchine n In Moore mchine, the output depends onl on the current stte, ut not the input n Next stte (ns) is comintionl function on current stte (s) nd current input n After clock edge, ns ecomes the current stte (s) in the next ccle è connect to stte register n Output depends on current stte n Output m depend on input s well n Moore mchine void comintionl pth etween input nd output of stte mchine n However, in generl, Moore mchine requires more sttes to implement the sme function thn Mel mchine st semester, 22 ENGG5  H. So 9 st semester, 22 ENGG5  H. So 2 Stte Encoding n Stte encoding refers to the w the strct FSM sttes re represented in hrdwre n In inr encoding scheme, ech stte is encoded using n nit inr numer. 2 n possile sttes The ticket gte exmple is the simplest inr encoding with it = 2 sttes n In onehot encoding scheme, ech FSM stte is encoded using it t unique it position n DFFs re used to encode n FSM sttes Stte Encoding Stte Binr OneHot Stte_A Stte_B Stte_C Stte_D Oservtions: Exmple: encoding 4 sttes using different encoding scheme n Onehot encoding scheme requires more DFFs for lrge FSMs But generll simpler next stte/output logic n The mpping etween stte nd its encoding cn e quite ritrr E.g. No reson wh Stte_C cnnot e n Nontrivil to define the est encoding st semester, 22 ENGG5  H. So 2 st semester, 22 ENGG5  H. So 22 Stte Encoding n In either encoding scheme, there will e codes tht do not correspond to n FSM stte E.g. is not vlid onehot encoding E.g. m not e vlid if there re onl 5 sttes in the FSM. n How to hndle invlid sttes? Ignore them since in theor our stte mchine will never end up in tht stte Flg n error, stop the mchine Reset the mchine/jump to defult stte Tke dvntge of them to simplif the design of next stte/output logic CIRCUIT TIMING st semester, 22 ENGG5  H. So 23 st semester, 22 ENGG5  H. So 24 4
5 9//2 Timing of Circuits n So fr, we hve ssumed: output of comintionl circuit chnges instntneous w.r.t. input Output of FF chnges instntneousl w.r.t. clock edge n In relit, it tkes finite mount of time for signl to trvel through circuit. n The timing of different prts of circuit m cuse glitches in output, limit the mximum speed of design st semester, 22 ENGG5  H. So 25 Propgtion Del c d n Ech logic gte incurs del etween the input nd output to llow signl to propgte Such del is referred s propgtion del n Exct vlue is technologdependent n In this clss, we ssume ll gtes hve the sme unit propgtion del. The speed of circuit is lws limited the slowest pth st semester, 22 ENGG5  H. So 26 3 units of del from to unit of del from d to Worst cse del = 3 units Glitches x n Glitches refer to n momentril chnge in signl vlue n One common cuse is due to rce condition etween signl pths Imlnced propgtion del n M cuse incorrect output if signl is used during the glitch x stle time Timing in Snchronous Circuits c d n In snchronous sequentil circuit, signl chnges occur onl during clock edge n All signls re therefore snchronized to chnge vlues right fter clock edge n In the ove exmple, need to mke sure correct vlue of ville BEFORE next clock edge st semester, 22 ENGG5  H. So 27 st semester, 22 ENGG5  H. So 28 Timing in Snchronous Circuits n In generl, the propgtion del through the comintionl logic etween n two registers must e shorter thn the clock period n The longest such pth is clled the criticl pth of the circuit n The criticl pth determines the mximum clock speed x From glitch exmple Com Stle efore clock edge Snchronous Circuits Timing Trdeoff n Since onl vlues right efore the clock edge in the input port re cptured, ll the glitches within the circuit re ignored n A short period of time efore clock edge must e llocted to ensure stle inputs Too smll è Chnce of filing circuit Too ig è Wsted idle time n Since ll circuit runs on the sme clock, clock frequenc limited the longest criticl pth st semester, 22 ENGG5  H. So 29 st semester, 22 ENGG5  H. So 3 5
6 9//2 Summr n Snchronous sequentil circuits contin one single clock All FFs connected to the sme clock All signl chnge snchronized to the sme clock edge n Stte mchine is n importnt strction for computtion Stright forwrd implementtion s snchronous sequentil logic n Propgtion del of logic gtes determines the highest frequenc snchronous sequentil circuit cn run st semester, 22 ENGG5  H. So 3 6
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