DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING, THE UNIVERSITY OF NEW MEXICO ECE-238L:

Transcription

1 PATMNT OF LCTICAL AN COMPUT NGINING, TH UNIVITY OF NW MXICO C-238L: Computer Logic eign Fll 23 AYNCHONOU UNTIAL CICUIT: Note - Chpter 5 Ltch: t+ t t+ t retricted Ltch Ltch with enle: ' t+ t t+ t t t ' Ltch with enle: Thi i eentilly n Ltch, where ' t+ t ' Intructor: niel Llmocc

2 PATMNT OF LCTICAL AN COMPUT NGINING, TH UNIVITY OF NW MXICO C-238L: Computer Logic eign Fll 23 YNCHONOU UNTIAL CICUIT: Flip Flop Flip flop re mde out of: o A Ltch with n enle input. o An dge detector circuit. The figure depict n Ltch, where the enle i connected to the output of n dge etector Circuit. The input to the dge etector i ignl clled ''. A ignl i n qure wve with fied frequency. T Period Frequency = /T ' Flip Flop dge etector or ' The edge detector circuit generte hort-durtion pule during riing (or flling) edge. Thee pule ct enle of the Ltch. The ehvior of the flip flop cn e decried tht of Ltch tht i only enled during riing (or flling edge). Flip flop clifiction: o Poitive-edge triggered flip flop: The edge detector circuit generte pule during riing edge. o Negtive-edge triggered flip flop: The edge detector circuit generte pule during flling edge. Poitive edge-triggered Negtive edge-triggered Flip Flop t+ t+ t t Intructor: niel Llmocc

3 PATMNT OF LCTICAL AN COMPUT NGINING, TH UNIVITY OF NW MXICO C-238L: Computer Logic eign Fll 23 Flip Flop t+ Flip Flop dge etector T Flip Flop T T T t+ t t Flip Flop t+ t t ynchronou/aynchronou Input o fr, the flip flop cn only chnge their output on the riing (or flling edge). The output re uully chnged due to chnge in the input. Thee input re known ynchronou input, the input' tte i only checked on the riing (or flling) edge. However, in mny intnce, it i ueful to hve input tht force the prn output to vlue immeditely, diregrding the riing (or flling edge). Thee input re known ynchronou input. In the emple, we ee Flip Flop with two ynchronou input: o prn: Preet (ctive low). When prn='', the output q ecome. o : Cler (ctive low). When ='', the output q ecome. If 'prn' nd '' re oth, uully i given priority. A Flip flop could hve more thn one ynchronou input, or none. Intructor: niel Llmocc

4 PATMNT OF LCTICAL AN COMPUT NGINING, TH UNIVITY OF NW MXICO C-238L: Computer Logic eign Fll 23 PACTIC XCI. Complete the timing digrm of the circuit hown elow: 2. Complete the VHL decription of the circuit hown elow: lirry ieee; ue ieee.td_logic_64.ll; entity circ i port (,,,, : in td_logic; q: out td_logic); --??? end ; 3. Complete the timing digrm of the circuit hown elow. If the frequency of the ignl i 25 MHz, wht i the frequency (in MHz) of the ignl? '' T 4. Complete the timing digrm of the circuit whoe VHL decription i hown elow: lirry ieee; ue ieee.td_logic_64.ll; entity circ i port (,, : in td_logic; q: out td_logic); ignl qt: td_logic; proce (,, ) if = then q <= ; elif ( event nd = ) then if = then qt <= not (qt); end if; end if; end proce; end ; Intructor: niel Llmocc

5 PATMNT OF LCTICAL AN COMPUT NGINING, TH UNIVITY OF NW MXICO C-238L: Computer Logic eign Fll Complete the timing digrm of the circuit hown elow: Full Adder y FA cin cout 6. Complete the VHL decription of the ynchronou equentil circuit whoe truth tle i hown elow: lirry ieee; ue ieee.td_logic_64.ll; entity circ i port ( A, B, C: in td_logic;, : in td_logic; q: out td_logic); --??? end ; X A B t+ C t t X X 7. Complete the timing digrm of the circuit hown elow: y y 8. Complete the timing digrm of the circuit hown elow: Ltch L L Intructor: niel Llmocc