Design and implementation of a high-speed bit-serial SFQ adder based on the binary decision diagram

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1 INSTITUTE OFPHYSICS PUBLISHING Supercond. Sci. Technol. 16 (23) SUPERCONDUCTORSCIENCE AND TECHNOLOGY PII: S (3) Design nd implementtion of high-speed it-seril SFQ dder sed on the inry decision digrm Kenji Kwski 1,Kenichi Yod 1,Nouyuki Yoshikw 1, Akir Fujimki 2,Hirotk Teri 3 nd Shinichi Yorozu 4 1 Deprtment of Electricl nd Computer Engineering, Yokohm Ntionl University, 79-5 Tokiwdi, Hodogy-ku, Yokohm , Jpn 2 Deprtment of Quntum Engineering, Ngoy University, Furo-cho, Chikus-ku, Ngoy , Jpn 3 Communiction Reserch Lortory, Iwok, Nishi-ku, Koe , Jpn 4 SRL-ISTEC, 34 Miyukigok, Tsuku , Jpn E-mil: Received 4 August 23 Pulished 7 Novemer 23 Online t stcks.iop.org/sust/16/1497 Astrct We hve designed high-speed SFQ it-seril crry-sve dder sed on the inry decision digrm (BDD). A simple it-seril crry-sve dder sed on the BDD we first designed hs crry-feedck loop. Its input dt frequency is limited y the propgtion dely in the feedck loop. In our second dder design, we hve replced one BDD gte with nondestructive inry switch, y which we cn eliminte the crry-feedck loop. We hve designed the high-speed BDD SFQ it-seril dder using the NEC 2.5 ka cm 2 N stndrd process nd the CONNECT cell lirry. The circuit simultion indictes tht the mximum operting frequency is 38 GHz nd the dc is mrgin t 1 GHz is ±23%. We hve confirmed its correct opertion in the on-chip high-speed test. The mximum operting frequency ws found to e 23.8 GHz. 1. Introduction Rpid single flux quntum (RSFQ) logic circuits [1] re promising circuit technology ecuse of their high-speed nd low-power opertion. We hve een developing it-seril SFQ microprocessor, where its speed is mostly limited y it-seril full dder. Mny seril dders hve een studied nd re reported in [1 4]. In this study, we hve investigted it-seril SFQ dder rchitecture sed on the inry decision digrm (BDD) [5] to increse n input dt frequency. The BDD SFQ circuits re dt-driven self-timed (DDST) system [6], nd hve the following dvntges: (i) the timing design is simple due to its synchronous nture nd (ii) the propgtion dely is smll ecuse of their smll gte counts. Our first dder design uses one-it BDD dder with crry-feedck loop, whose input dt frequency is limited y the propgtion dely in the crry-feedck loop. In our new dder design, we eliminte the crry-feedck loop in order to increse the input dt frequency. We hve c c c () crry c c () crry Figure 1. Ainry decision digrm (BDD) of one-it full dder. () A nd crry re clculted seprtely. () Common nodes re comined together. implemented the high-speed it-seril dder nd tested it t high speed /3/ $3. 23 IOP Pulishing Ltd Printed in the UK 1497

2 KKwski et l c c () crry DC Bis Mrgin (%) Dt Frequency (GHz) () Figure 2. Ait-seril crry-sve BDD dder with crry-feedck loop. ()ABDD representtion. () The dependences of the upper nd lower is mrgins of the dder on the input dt frequency. 2. Adder design sed on the inry decision digrm Figure 1() showsthebdd representtion of nd crry of one-it full dder [5]. The BDD is directionl grph, which is composed of mny inry switches (nodes) with one input nd two outputs. Ech node switches the input c c c crry () DC Bis Mrgin (%) Dt Frequency (GHz) () Figure 3. Ahigh-speed crry-sve BDD dder without crry-feedck loop. () ABDD representtion. A doule circle denotes the nondestructive version of the Bin cell. ()The dependences of the upper nd lower is mrgins of the dder on the input dt frequency. SFQ pulse into one of two directions depending on its internl stte s designted in the figure. The internl stte of the node is defined y the dul-ril input (it is not shown in the figure) efore the input of the SFQ pulse. The result of the clcultion of the BDD dder corresponds to the finl destintion of the Figure 4. Acircuit schemtic of the high-speed crry-sve BDD dder without crry-feedck loop. 1498

3 () () Design nd implementtion of high-speed it-seril SFQ dder sed on the BDD 2.1. Crry-sve dder with crry-feedck loop Asimple wy to mke the one-it BDD full dder in figure 1 into it-seril crry-sve dder is y just dding crryfeedck loop s shown in figure 2(). The crry-feedck loop is designted in the figure s dotted line. We hve designed this type of dder using CONNECT cell lirry [7], nd evluted its performnce y circuit simultions. The Bin cell [5], which is destructive dely flip-flop with dulril input nd output, ws used s the inry switch in the BDD. Figure 2() shows dependences of the upper nd lower dc is mrgins on the input dt frequency otined from circuit simultions, where NEC N 2.5 ka cm 2 process is sed. The simultion results show tht the mximum input dt frequency is 13 GHz, which is limited y the propgtion dely in the crry-feedck loop High-speed crry-sve dder without crry-feedck loop Aclose oservtion of the crry-feedck loop in figure 2() rings out the ide tht the feedck loop cn e eliminted in the dder y replcing the lower right node with nondestructive dely flip-flop ecuse its next internl stte is just the sme with the current stte. Such new crry-sve dder is presented in figure 3(), where the nondestructive version of the Bin cell is denoted y doule circle in the figure. Figure 3() showsthedependence of the dc is mrgins of the high-speed crry-sve dder without the crryfeedck loop on the input dt frequency, which is otined y the circuit simultions. The circuit is designed y using the CONNECT cell lirry nd the NEC N 2.5 ka cm 2 process. As cn e seen in the figure, the mximum input dt frequency is incresed up to 38 GHz y eliminting the crry-feedck loop (c) Figure 5. Low-speed test results of the high-speed crry-sve BDD dder. Ech rising edge corresponds to n input of n SFQ pulse for, ā, nd. Ech trnsition corresponds to n output of n SFQ pulse for nd. () nd () disply the input dt sequence = ( ) nd = ( ), respectively. (c) istheoutput dt of = ( ). SFQ pulse, which is denoted y or 1 in the ox. The one-it BDD full dder cn e simplified furthermore y comining the nodes with the common function s shown in figure 1(). 3. Test results We hve implemented the high-speed it-seril dder without the feedck loop using the NEC N 2.5 ka cm 2 process nd tested it t low speed. A circuit schemtic of the BDD dder is shown in figure 4. Thedder contins 513 Josephson junctions nd its size is 6 µm 72 µm. Figure 5 shows its test results t low speed, where dul-ril it-seril dt, = ( ) nd = ( ), re inputted. We cn clerly see tht = ( ) re otined correctly. The low-speed dc is mrgin is found to e 16.5% +19.1%. We hve lso tested the dder t high speed using the on-chip high-speed test system [8]. Figure 6 shows circuit schemtic of the system. The system is composed of two four-it DDST shift registers for loding the dt, one four-it DDST shift register for reding the dt, nd four-it clock genertor (CG) to provide high-speed clock to the input shift registers. The on-chip high-speed test is performed s follows: first, input dt re loded to the input shift registers t low speed (denoted s (1) in figure 6). Then CG trigger pulse is pplied to the CG, which genertes four-it highspeed clock nd provides it to the input shift registers ((2) in the figure). This high-speed clock pushes the dt in the shift registers, which send the dt pulses to the dder t high speed 1499

4 KKwski et l shift register (1) (3) (5) CG trigger CG (2) (1) shift register (3) Adder (4) shift register Red Figure 6. Acircuit schemtic of the on-chip high-speed test system. Figure 7. A photogrph of the on-chip high-speed test system. ((3) in the figure). Output dt clculted y the dder re sent to the output shift register t high speed simultneously ((4) in the figure). Finlly the dt in the output shift register re red out y pplying the red pulses to the output shift register t low speed ((5) in the figure). A photogrph of the on-chip high-speed test system is shown in figure 7. The system contins 1434 Josephson junctions nd its size is 12 µm 24 µm. Results of the on-chip high-speed test t 16 GHz re shown in figure 8, wheredul-ril it-seril dt, = (11), = (11) nd = (11), = (11), re inputted successively. One cn clerly see tht output dt, = (1) nd = (111), re otined correctly. We hve estimted the frequency of the CG y the circuit simultion. Seprte high-speed mesurement of the CG shows tht the tested frequency grees well with the circuit simultion results [9]. The operting mrgins of the dder were lso exmined t vrious frequencies y chnging the is current of the CG independently. Figure 9 shows the dependences of the upper nd lower mrgins of the dder on the dt input frequency. Simultion results re lso plotted in the figure for comprison. The mximum frequency of the dder ws found to e 23.8 GHz from the on-chip high-speed test. 15

5 Design nd implementtion of high-speed it-seril SFQ dder sed on the BDD () () Red CG trigger (c) (d ) Figure 8. High-speed test results of the high-speed crry-sve BDD dder. Prts () nd () disply the input dt = (11), (11) nd = (11), (11), respectively. Prt (c) isthe red nd CG trigger pulses. Prt (d) istheoutput dt, = (1), (111). dder cn e incresed up to 38 GHz in the simultion. The high-speed dder ws implemented y using the CONNECT cell lirry nd the NEC N stndrd process, nd its correct opertion ws confirmed t low nd high speeds. The mximum frequency of dder ws 23.8 GHz in the on-chip high-speed test. Acknowledgments Figure 9. The dependences of the upper nd lower is mrgins of the high-speed crry-sve BDD dder on the input dt frequency otined y the high-speed tests nd the circuit simultions. 4. Conclusions We hve designed the high-speed BDD crry-sve dders. By eliminting the feedck loop, the mximum frequency of the The uthors would like to thnk the CONNECT cell lirry development tems of Ngoy University, NEC Inc. nd CRL for fruitful discussions. This work ws supported y the New Energy nd Industril Technology Development Orgniztion (NEDO) through ISTEC s Collortive Reserch nd Superconductors Network Device Project. References [1] Likhrev K K nd Semenov V K 1992 IEEE Trns. Appl. Supercond. 1 1 [2] Mrtinet S S nd Bocko M F 1993 IEEE Trns. Appl. Supercond [3] Polonsky S V, Lin J C nd Rylykov A V 1995 IEEE Trns. Appl. Supercond

6 KKwski et l [4] Polonsky S V, Semenov V K nd Kirichenko A F 1994 IEEE Trns. Appl. Supercond [5] Yoshikw N nd Koshiym J 21 IEEE Trns. Appl. Supercond [6] Deng Z J, Yoshikw N, Whiteley S R nd Duzer T Vn 1999 IEEE Trns. Appl. Supercond. 9 7 [7] Yorozu S, Kmed Y, Teri H, Fujimki A, Ymd T nd Thr S 22 Physic C [8] Deng Z J, Yoshikw N, Whiteley S R nd Duzer T Vn 1997 IEEE Trns. Appl. Supercond [9] Ito M, Nkjim N, Fujiwr K, Yoshikw N, Fujimki A, Teri H nd Yorozu S 23 Physic Csumitted 152

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