Design and implementation of a high-speed bit-serial SFQ adder based on the binary decision diagram
|
|
- Belinda Collins
- 6 years ago
- Views:
Transcription
1 INSTITUTE OFPHYSICS PUBLISHING Supercond. Sci. Technol. 16 (23) SUPERCONDUCTORSCIENCE AND TECHNOLOGY PII: S (3) Design nd implementtion of high-speed it-seril SFQ dder sed on the inry decision digrm Kenji Kwski 1,Kenichi Yod 1,Nouyuki Yoshikw 1, Akir Fujimki 2,Hirotk Teri 3 nd Shinichi Yorozu 4 1 Deprtment of Electricl nd Computer Engineering, Yokohm Ntionl University, 79-5 Tokiwdi, Hodogy-ku, Yokohm , Jpn 2 Deprtment of Quntum Engineering, Ngoy University, Furo-cho, Chikus-ku, Ngoy , Jpn 3 Communiction Reserch Lortory, Iwok, Nishi-ku, Koe , Jpn 4 SRL-ISTEC, 34 Miyukigok, Tsuku , Jpn E-mil: yoshi@yoshil.dnj.ynu.c.jp Received 4 August 23 Pulished 7 Novemer 23 Online t stcks.iop.org/sust/16/1497 Astrct We hve designed high-speed SFQ it-seril crry-sve dder sed on the inry decision digrm (BDD). A simple it-seril crry-sve dder sed on the BDD we first designed hs crry-feedck loop. Its input dt frequency is limited y the propgtion dely in the feedck loop. In our second dder design, we hve replced one BDD gte with nondestructive inry switch, y which we cn eliminte the crry-feedck loop. We hve designed the high-speed BDD SFQ it-seril dder using the NEC 2.5 ka cm 2 N stndrd process nd the CONNECT cell lirry. The circuit simultion indictes tht the mximum operting frequency is 38 GHz nd the dc is mrgin t 1 GHz is ±23%. We hve confirmed its correct opertion in the on-chip high-speed test. The mximum operting frequency ws found to e 23.8 GHz. 1. Introduction Rpid single flux quntum (RSFQ) logic circuits [1] re promising circuit technology ecuse of their high-speed nd low-power opertion. We hve een developing it-seril SFQ microprocessor, where its speed is mostly limited y it-seril full dder. Mny seril dders hve een studied nd re reported in [1 4]. In this study, we hve investigted it-seril SFQ dder rchitecture sed on the inry decision digrm (BDD) [5] to increse n input dt frequency. The BDD SFQ circuits re dt-driven self-timed (DDST) system [6], nd hve the following dvntges: (i) the timing design is simple due to its synchronous nture nd (ii) the propgtion dely is smll ecuse of their smll gte counts. Our first dder design uses one-it BDD dder with crry-feedck loop, whose input dt frequency is limited y the propgtion dely in the crry-feedck loop. In our new dder design, we eliminte the crry-feedck loop in order to increse the input dt frequency. We hve c c c () crry c c () crry Figure 1. Ainry decision digrm (BDD) of one-it full dder. () A nd crry re clculted seprtely. () Common nodes re comined together. implemented the high-speed it-seril dder nd tested it t high speed /3/ $3. 23 IOP Pulishing Ltd Printed in the UK 1497
2 KKwski et l c c () crry DC Bis Mrgin (%) Dt Frequency (GHz) () Figure 2. Ait-seril crry-sve BDD dder with crry-feedck loop. ()ABDD representtion. () The dependences of the upper nd lower is mrgins of the dder on the input dt frequency. 2. Adder design sed on the inry decision digrm Figure 1() showsthebdd representtion of nd crry of one-it full dder [5]. The BDD is directionl grph, which is composed of mny inry switches (nodes) with one input nd two outputs. Ech node switches the input c c c crry () DC Bis Mrgin (%) Dt Frequency (GHz) () Figure 3. Ahigh-speed crry-sve BDD dder without crry-feedck loop. () ABDD representtion. A doule circle denotes the nondestructive version of the Bin cell. ()The dependences of the upper nd lower is mrgins of the dder on the input dt frequency. SFQ pulse into one of two directions depending on its internl stte s designted in the figure. The internl stte of the node is defined y the dul-ril input (it is not shown in the figure) efore the input of the SFQ pulse. The result of the clcultion of the BDD dder corresponds to the finl destintion of the Figure 4. Acircuit schemtic of the high-speed crry-sve BDD dder without crry-feedck loop. 1498
3 () () Design nd implementtion of high-speed it-seril SFQ dder sed on the BDD 2.1. Crry-sve dder with crry-feedck loop Asimple wy to mke the one-it BDD full dder in figure 1 into it-seril crry-sve dder is y just dding crryfeedck loop s shown in figure 2(). The crry-feedck loop is designted in the figure s dotted line. We hve designed this type of dder using CONNECT cell lirry [7], nd evluted its performnce y circuit simultions. The Bin cell [5], which is destructive dely flip-flop with dulril input nd output, ws used s the inry switch in the BDD. Figure 2() shows dependences of the upper nd lower dc is mrgins on the input dt frequency otined from circuit simultions, where NEC N 2.5 ka cm 2 process is sed. The simultion results show tht the mximum input dt frequency is 13 GHz, which is limited y the propgtion dely in the crry-feedck loop High-speed crry-sve dder without crry-feedck loop Aclose oservtion of the crry-feedck loop in figure 2() rings out the ide tht the feedck loop cn e eliminted in the dder y replcing the lower right node with nondestructive dely flip-flop ecuse its next internl stte is just the sme with the current stte. Such new crry-sve dder is presented in figure 3(), where the nondestructive version of the Bin cell is denoted y doule circle in the figure. Figure 3() showsthedependence of the dc is mrgins of the high-speed crry-sve dder without the crryfeedck loop on the input dt frequency, which is otined y the circuit simultions. The circuit is designed y using the CONNECT cell lirry nd the NEC N 2.5 ka cm 2 process. As cn e seen in the figure, the mximum input dt frequency is incresed up to 38 GHz y eliminting the crry-feedck loop (c) Figure 5. Low-speed test results of the high-speed crry-sve BDD dder. Ech rising edge corresponds to n input of n SFQ pulse for, ā, nd. Ech trnsition corresponds to n output of n SFQ pulse for nd. () nd () disply the input dt sequence = ( ) nd = ( ), respectively. (c) istheoutput dt of = ( ). SFQ pulse, which is denoted y or 1 in the ox. The one-it BDD full dder cn e simplified furthermore y comining the nodes with the common function s shown in figure 1(). 3. Test results We hve implemented the high-speed it-seril dder without the feedck loop using the NEC N 2.5 ka cm 2 process nd tested it t low speed. A circuit schemtic of the BDD dder is shown in figure 4. Thedder contins 513 Josephson junctions nd its size is 6 µm 72 µm. Figure 5 shows its test results t low speed, where dul-ril it-seril dt, = ( ) nd = ( ), re inputted. We cn clerly see tht = ( ) re otined correctly. The low-speed dc is mrgin is found to e 16.5% +19.1%. We hve lso tested the dder t high speed using the on-chip high-speed test system [8]. Figure 6 shows circuit schemtic of the system. The system is composed of two four-it DDST shift registers for loding the dt, one four-it DDST shift register for reding the dt, nd four-it clock genertor (CG) to provide high-speed clock to the input shift registers. The on-chip high-speed test is performed s follows: first, input dt re loded to the input shift registers t low speed (denoted s (1) in figure 6). Then CG trigger pulse is pplied to the CG, which genertes four-it highspeed clock nd provides it to the input shift registers ((2) in the figure). This high-speed clock pushes the dt in the shift registers, which send the dt pulses to the dder t high speed 1499
4 KKwski et l shift register (1) (3) (5) CG trigger CG (2) (1) shift register (3) Adder (4) shift register Red Figure 6. Acircuit schemtic of the on-chip high-speed test system. Figure 7. A photogrph of the on-chip high-speed test system. ((3) in the figure). Output dt clculted y the dder re sent to the output shift register t high speed simultneously ((4) in the figure). Finlly the dt in the output shift register re red out y pplying the red pulses to the output shift register t low speed ((5) in the figure). A photogrph of the on-chip high-speed test system is shown in figure 7. The system contins 1434 Josephson junctions nd its size is 12 µm 24 µm. Results of the on-chip high-speed test t 16 GHz re shown in figure 8, wheredul-ril it-seril dt, = (11), = (11) nd = (11), = (11), re inputted successively. One cn clerly see tht output dt, = (1) nd = (111), re otined correctly. We hve estimted the frequency of the CG y the circuit simultion. Seprte high-speed mesurement of the CG shows tht the tested frequency grees well with the circuit simultion results [9]. The operting mrgins of the dder were lso exmined t vrious frequencies y chnging the is current of the CG independently. Figure 9 shows the dependences of the upper nd lower mrgins of the dder on the dt input frequency. Simultion results re lso plotted in the figure for comprison. The mximum frequency of the dder ws found to e 23.8 GHz from the on-chip high-speed test. 15
5 Design nd implementtion of high-speed it-seril SFQ dder sed on the BDD () () Red CG trigger (c) (d ) Figure 8. High-speed test results of the high-speed crry-sve BDD dder. Prts () nd () disply the input dt = (11), (11) nd = (11), (11), respectively. Prt (c) isthe red nd CG trigger pulses. Prt (d) istheoutput dt, = (1), (111). dder cn e incresed up to 38 GHz in the simultion. The high-speed dder ws implemented y using the CONNECT cell lirry nd the NEC N stndrd process, nd its correct opertion ws confirmed t low nd high speeds. The mximum frequency of dder ws 23.8 GHz in the on-chip high-speed test. Acknowledgments Figure 9. The dependences of the upper nd lower is mrgins of the high-speed crry-sve BDD dder on the input dt frequency otined y the high-speed tests nd the circuit simultions. 4. Conclusions We hve designed the high-speed BDD crry-sve dders. By eliminting the feedck loop, the mximum frequency of the The uthors would like to thnk the CONNECT cell lirry development tems of Ngoy University, NEC Inc. nd CRL for fruitful discussions. This work ws supported y the New Energy nd Industril Technology Development Orgniztion (NEDO) through ISTEC s Collortive Reserch nd Superconductors Network Device Project. References [1] Likhrev K K nd Semenov V K 1992 IEEE Trns. Appl. Supercond. 1 1 [2] Mrtinet S S nd Bocko M F 1993 IEEE Trns. Appl. Supercond [3] Polonsky S V, Lin J C nd Rylykov A V 1995 IEEE Trns. Appl. Supercond
6 KKwski et l [4] Polonsky S V, Semenov V K nd Kirichenko A F 1994 IEEE Trns. Appl. Supercond [5] Yoshikw N nd Koshiym J 21 IEEE Trns. Appl. Supercond [6] Deng Z J, Yoshikw N, Whiteley S R nd Duzer T Vn 1999 IEEE Trns. Appl. Supercond. 9 7 [7] Yorozu S, Kmed Y, Teri H, Fujimki A, Ymd T nd Thr S 22 Physic C [8] Deng Z J, Yoshikw N, Whiteley S R nd Duzer T Vn 1997 IEEE Trns. Appl. Supercond [9] Ito M, Nkjim N, Fujiwr K, Yoshikw N, Fujimki A, Teri H nd Yorozu S 23 Physic Csumitted 152
Mixed CMOS PTL Adders
Anis do XXVI Congresso d SBC WCOMPA l I Workshop de Computção e Aplicções 14 20 de julho de 2006 Cmpo Grnde, MS Mixed CMOS PTL Adders Déor Mott, Reginldo d N. Tvres Engenhri em Sistems Digitis Universidde
More informationCHAPTER 2 LITERATURE STUDY
CHAPTER LITERATURE STUDY. Introduction Multipliction involves two bsic opertions: the genertion of the prtil products nd their ccumultion. Therefore, there re two possible wys to speed up the multipliction:
More informationTo provide data transmission in indoor
Hittite Journl of Science nd Engineering, 2018, 5 (1) 25-29 ISSN NUMBER: 2148-4171 DOI: 10.17350/HJSE19030000074 A New Demodultor For Inverse Pulse Position Modultion Technique Mehmet Sönmez Osmniye Korkut
More informationChapter 2 Literature Review
Chpter 2 Literture Review 2.1 ADDER TOPOLOGIES Mny different dder rchitectures hve een proposed for inry ddition since 1950 s to improve vrious spects of speed, re nd power. Ripple Crry Adder hve the simplest
More informationDirect measurements of propagation delay of single-flux-quantum circuits by time-to-digital converters
Direct measurements of propagation delay of single-flux-quantum circuits by time-to-digital converters Kazunori Nakamiya 1a), Nobuyuki Yoshikawa 1, Akira Fujimaki 2, Hirotaka Terai 3, and Yoshihito Hashimoto
More informationISSCC 2006 / SESSION 21 / ADVANCED CLOCKING, LOGIC AND SIGNALING TECHNIQUES / 21.5
21.5 A 1.1GHz Chrge-Recovery Logic Visvesh Sthe, Jung-Ying Chueh, Mrios Ppefthymiou University of Michign, Ann Aror, MI Boost Logic is chrge-recovery circuit fmily cple of operting t GHz-clss frequencies
More informationArea-Time Efficient Digit-Serial-Serial Two s Complement Multiplier
Are-Time Efficient Digit-Seril-Seril Two s Complement Multiplier Essm Elsyed nd Htem M. El-Boghddi Computer Engineering Deprtment, Ciro University, Egypt Astrct - Multipliction is n importnt primitive
More informationImplementation of Different Architectures of Forward 4x4 Integer DCT For H.264/AVC Encoder
Implementtion of Different Architectures of Forwrd 4x4 Integer DCT For H.64/AVC Encoder Bunji Antoinette Ringnyu, Ali Tngel, Emre Krulut 3 Koceli University, Institute of Science nd Technology, Koceli,
More informationMulti-beam antennas in a broadband wireless access system
Multi-em ntenns in rodnd wireless ccess system Ulrik Engström, Mrtin Johnsson, nders Derneryd nd jörn Johnnisson ntenn Reserch Center Ericsson Reserch Ericsson SE-4 84 Mölndl Sweden E-mil: ulrik.engstrom@ericsson.com,
More informationSafety Relay Unit. Main contacts Auxiliary contact Number of input channels Rated voltage Model Category. possible 24 VAC/VDC G9SA-501.
Sfety Rely Unit The Series Offers Complete Line-up of Compct Units. Four kinds of -mm wide Units re ville: A -pole model, -pole model, nd models with poles nd OFF-dely poles, s well s Two-hnd ler. Simple
More informationEE Controls Lab #2: Implementing State-Transition Logic on a PLC
Objective: EE 44 - Controls Lb #2: Implementing Stte-rnsition Logic on PLC ssuming tht speed is not of essence, PLC's cn be used to implement stte trnsition logic. he dvntge of using PLC over using hrdwre
More informationSynchronous Generator Line Synchronization
Synchronous Genertor Line Synchroniztion 1 Synchronous Genertor Line Synchroniztion Introduction One issue in power genertion is synchronous genertor strting. Typiclly, synchronous genertor is connected
More informationSynchronous Machine Parameter Measurement
Synchronous Mchine Prmeter Mesurement 1 Synchronous Mchine Prmeter Mesurement Introduction Wound field synchronous mchines re mostly used for power genertion but lso re well suited for motor pplictions
More informationSynchronous Machine Parameter Measurement
Synchronous Mchine Prmeter Mesurement 1 Synchronous Mchine Prmeter Mesurement Introduction Wound field synchronous mchines re mostly used for power genertion but lso re well suited for motor pplictions
More informationINSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigal, Hyderabad
Hll Ticket No Question Pper Code: AEC009 INSTITUTE OF AERONAUTICAL ENGINEERING (Autonomous) Dundigl, Hyderd - 500 043 MODEL QUESTION PAPER Four Yer B.Tech V Semester End Exmintions, Novemer - 2018 Regultions:
More informationCS 135: Computer Architecture I. Boolean Algebra. Basic Logic Gates
Bsic Logic Gtes : Computer Architecture I Boolen Algebr Instructor: Prof. Bhgi Nrhri Dept. of Computer Science Course URL: www.ses.gwu.edu/~bhgiweb/cs35/ Digitl Logic Circuits We sw how we cn build the
More informationUniversity of North Carolina-Charlotte Department of Electrical and Computer Engineering ECGR 4143/5195 Electrical Machinery Fall 2009
Problem 1: Using DC Mchine University o North Crolin-Chrlotte Deprtment o Electricl nd Computer Engineering ECGR 4143/5195 Electricl Mchinery Fll 2009 Problem Set 4 Due: Thursdy October 8 Suggested Reding:
More informationDigital Design. Sequential Logic Design -- Controllers. Copyright 2007 Frank Vahid
Digitl Design Sequentil Logic Design -- Controllers Slides to ccompny the tetook Digitl Design, First Edition, y, John Wiley nd Sons Pulishers, 27. http://www.ddvhid.com Copyright 27 Instructors of courses
More information& Y Connected resistors, Light emitting diode.
& Y Connected resistors, Light emitting diode. Experiment # 02 Ojectives: To get some hndson experience with the physicl instruments. To investigte the equivlent resistors, nd Y connected resistors, nd
More informationSequential Logic (2) Synchronous vs Asynchronous Sequential Circuit. Clock Signal. Synchronous Sequential Circuits. FSM Overview 9/10/12
9//2 Sequentil (2) ENGG5 st Semester, 22 Dr. Hden So Deprtment of Electricl nd Electronic Engineering http://www.eee.hku.hk/~engg5 Snchronous vs Asnchronous Sequentil Circuit This Course snchronous Sequentil
More informationAlgorithms for Memory Hierarchies Lecture 14
Algorithms for emory Hierrchies Lecture 4 Lecturer: Nodri Sitchinv Scribe: ichel Hmnn Prllelism nd Cche Obliviousness The combintion of prllelism nd cche obliviousness is n ongoing topic of reserch, in
More informationDP4T RF CMOS Switch: A Better Option to Replace the SPDT Switch and DPDT Switch
Send Orders of Reprints t reprints@enthmscience.org 244 Recent Ptents on Electricl & Electronic Engineering 2012, 5, 244-248 DP4T RF CMOS Switch: A Better Option to Replce the SPDT Switch nd DPDT Switch
More informationA Practical DPA Countermeasure with BDD Architecture
A Prcticl DPA Countermesure with BDD Architecture Toru Akishit, Msnou Ktgi, Yoshikzu Miyto, Asmi Mizuno, nd Kyoji Shiutni System Technologies Lortories, Sony Corportion, -7- Konn, Minto-ku, Tokyo 8-75,
More informationLATEST CALIBRATION OF GLONASS P-CODE TIME RECEIVERS
LATEST CALIBRATION OF GLONASS P-CODE TIME RECEIVERS A. Fos 1, J. Nwroci 2, nd W. Lewndowsi 3 1 Spce Reserch Centre of Polish Acdemy of Sciences, ul. Brtyc 18A, 00-716 Wrsw, Polnd; E-mil: fos@c.ww.pl; Tel.:
More informationA Development of Earthing-Resistance-Estimation Instrument
A Development of Erthing-Resistnce-Estimtion Instrument HITOSHI KIJIMA Abstrct: - Whenever erth construction work is done, the implnted number nd depth of electrodes hve to be estimted in order to obtin
More informationModule 9. DC Machines. Version 2 EE IIT, Kharagpur
Module 9 DC Mchines Version EE IIT, Khrgpur esson 40 osses, Efficiency nd Testing of D.C. Mchines Version EE IIT, Khrgpur Contents 40 osses, efficiency nd testing of D.C. mchines (esson-40) 4 40.1 Gols
More informationMAXIMUM FLOWS IN FUZZY NETWORKS WITH FUNNEL-SHAPED NODES
MAXIMUM FLOWS IN FUZZY NETWORKS WITH FUNNEL-SHAPED NODES Romn V. Tyshchuk Informtion Systems Deprtment, AMI corportion, Donetsk, Ukrine E-mil: rt_science@hotmil.com 1 INTRODUCTION During the considertion
More information(1) Non-linear system
Liner vs. non-liner systems in impednce mesurements I INTRODUCTION Electrochemicl Impednce Spectroscopy (EIS) is n interesting tool devoted to the study of liner systems. However, electrochemicl systems
More informationDIGITAL multipliers [1], [2] are the core components of
World Acdemy of Science, Engineering nd Technology 9 8 A Reduced-Bit Multipliction Algorithm for Digitl Arithmetic Hrpreet Singh Dhillon nd Ahijit Mitr Astrct A reduced-it multipliction lgorithm sed on
More informationControl of high-frequency AC link electronic transformer
Control of high-frequency AC link electronic trnsformer H. Krishnswmi nd V. Rmnrynn Astrct: An isolted high-frequency link AC/AC converter is termed n electronic trnsformer. The electronic trnsformer hs
More informationMath Circles Finite Automata Question Sheet 3 (Solutions)
Mth Circles Finite Automt Question Sheet 3 (Solutions) Nickols Rollick nrollick@uwterloo.c Novemer 2, 28 Note: These solutions my give you the nswers to ll the prolems, ut they usully won t tell you how
More informationThis is a repository copy of Four-port diplexer for high Tx/Rx isolation for integrated transceivers.
This is repository copy of Four-port diplexer for high Tx/Rx isoltion for integrted trnsceivers. White Rose Reserch Online URL for this pper: http://eprints.whiterose.c.uk/124000/ Version: Accepted Version
More informationExercise 1-1. The Sine Wave EXERCISE OBJECTIVE DISCUSSION OUTLINE. Relationship between a rotating phasor and a sine wave DISCUSSION
Exercise 1-1 The Sine Wve EXERCISE OBJECTIVE When you hve completed this exercise, you will be fmilir with the notion of sine wve nd how it cn be expressed s phsor rotting round the center of circle. You
More informationFuzzy Logic Controller for Three Phase PWM AC-DC Converter
Journl of Electrotechnology, Electricl Engineering nd Mngement (2017) Vol. 1, Number 1 Clusius Scientific Press, Cnd Fuzzy Logic Controller for Three Phse PWM AC-DC Converter Min Muhmmd Kml1,, Husn Ali2,b
More informationOpen Access A Novel Parallel Current-sharing Control Method of Switch Power Supply
Send Orders for Reprints to reprints@enthmscience.e 170 The Open Electricl & Electronic Engineering Journl, 2014, 8, 170-177 Open Access A Novel Prllel Current-shring Control Method of Switch Power Supply
More informationPB-735 HD DP. Industrial Line. Automatic punch and bind machine for books and calendars
PB-735 HD DP Automtic punch nd bind mchine for books nd clendrs A further step for the utomtion of double loop binding. A clever nd flexible mchine ble to punch nd bind in line up to 9/16. Using the best
More informationMETHOD OF LOCATION USING SIGNALS OF UNKNOWN ORIGIN. Inventor: Brian L. Baskin
METHOD OF LOCATION USING SIGNALS OF UNKNOWN ORIGIN Inventor: Brin L. Bskin 1 ABSTRACT The present invention encompsses method of loction comprising: using plurlity of signl trnsceivers to receive one or
More informationExperiment 8 Series DC Motor (II)
Ojectives To control the speed of loded series dc motor y chnging rmture voltge. To control the speed of loded series dc motor y dding resistnce in prllel with the rmture circuit. To control the speed
More informationKirchhoff s Rules. Kirchhoff s Laws. Kirchhoff s Rules. Kirchhoff s Laws. Practice. Understanding SPH4UW. Kirchhoff s Voltage Rule (KVR):
SPH4UW Kirchhoff s ules Kirchhoff s oltge ule (K): Sum of voltge drops round loop is zero. Kirchhoff s Lws Kirchhoff s Current ule (KC): Current going in equls current coming out. Kirchhoff s ules etween
More informationCHAPTER 3 AMPLIFIER DESIGN TECHNIQUES
CHAPTER 3 AMPLIFIER DEIGN TECHNIQUE 3.0 Introduction olid-stte microwve mplifiers ply n importnt role in communiction where it hs different pplictions, including low noise, high gin, nd high power mplifiers.
More informationA COMPARISON OF CIRCUIT IMPLEMENTATIONS FROM A SECURITY PERSPECTIVE
A COMPARISON OF CIRCUIT IMPLEMENTATIONS FROM A SECURITY PERSPECTIVE Mster Thesis Division of Electronic Devices Deprtment of Electricl Engineering Linköping University y Timmy Sundström LITH-ISY-EX--05/3698--SE
More informationProceedings of Meetings on Acoustics
Proceedings of Meetings on Acoustics Volume 19, 2013 http://cousticlsociety.org/ ICA 2013 Montrel Montrel, Cnd 2-7 June 2013 Signl Processing in Acoustics Session 4SP: Sensor Arry Bemforming nd Its Applictions
More informationExperimental Application of H Output-Feedback Controller on Two Links of SCARA Robot
INTERNATIONAL JOURNAL OF CONTROL, AUTOMATION AND SYSTEMS VOL.5 NO. Jnury 6 ISSN 65-877 (Print) ISSN 65-885 (Online) http://www.reserchpu.org/journl/jc/jc.html Experimentl Appliction of H Output-Feedck
More information10.4 AREAS AND LENGTHS IN POLAR COORDINATES
65 CHAPTER PARAMETRIC EQUATINS AND PLAR CRDINATES.4 AREAS AND LENGTHS IN PLAR CRDINATES In this section we develop the formul for the re of region whose oundry is given y polr eqution. We need to use the
More informationA New Algorithm to Compute Alternate Paths in Reliable OSPF (ROSPF)
A New Algorithm to Compute Alternte Pths in Relile OSPF (ROSPF) Jin Pu *, Eric Mnning, Gholmli C. Shoj, Annd Srinivsn ** PANDA Group, Computer Science Deprtment University of Victori Victori, BC, Cnd Astrct
More informationTHE STUDY OF INFLUENCE CORE MATERIALS ON TECHNOLOGICAL PROPERTIES OF UNIVERSAL BENTONITE MOULDING MATERIALS. Matej BEZNÁK, Vladimír HANZEN, Ján VRABEC
THE STUDY OF INFLUENCE CORE MATERIALS ON TECHNOLOGICAL PROPERTIES OF UNIVERSAL BENTONITE MOULDING MATERIALS Mtej BEZNÁK, Vldimír HANZEN, Ján VRABEC Authors: Mtej Beznák, Assoc. Prof. PhD., Vldimír Hnzen,
More informationResearch Letter Investigation of CMOS Varactors for High-GHz-Range Applications
Reserch Letters in Electronics Volume 29, Article ID 53589, 4 pges doi:1.1155/29/53589 Reserch Letter Investigtion of CMOS Vrctors for High-GHz-Rnge Applictions Ming Li, Rony E. Amy, Roert G. Hrrison,
More informationMEASURE THE CHARACTERISTIC CURVES RELEVANT TO AN NPN TRANSISTOR
Electricity Electronics Bipolr Trnsistors MEASURE THE HARATERISTI URVES RELEVANT TO AN NPN TRANSISTOR Mesure the input chrcteristic, i.e. the bse current IB s function of the bse emitter voltge UBE. Mesure
More informationDataflow Language Model. DataFlow Models. Applications of Dataflow. Dataflow Languages. Kahn process networks. A Kahn Process (1)
The slides contin revisited mterils from: Peter Mrwedel, TU Dortmund Lothr Thiele, ETH Zurich Frnk Vhid, University of liforni, Riverside Dtflow Lnguge Model Drsticlly different wy of looking t computtion:
More informationExperiment 3: The research of Thevenin theorem
Experiment 3: The reserch of Thevenin theorem 1. Purpose ) Vlidte Thevenin theorem; ) Mster the methods to mesure the equivlent prmeters of liner twoterminl ctive. c) Study the conditions of the mximum
More informationECE 274 Digital Logic. Digital Design. Datapath Components Shifters, Comparators, Counters, Multipliers Digital Design
ECE 27 Digitl Logic Shifters, Comprtors, Counters, Multipliers Digitl Design..7 Digitl Design Chpter : Slides to ccompny the textbook Digitl Design, First Edition, by Frnk Vhid, John Wiley nd Sons Publishers,
More informationRe: PCT Minimum Documentation: Updating of the Inventory of Patent Documents According to PCT Rule 34.1
C. SCIT 2508 00 August 10, 2000 Re: PCT Minimum Documenttion: Updting of the Inventory of Ptent Documents According to PCT Rule 34.1 Sir, Mdm, The current version of the Inventory of Ptent Documents for
More informationThree-Phase NPC Inverter Using Three-Phase Coupled Inductor
ThreePhse NPC Inverter Using ThreePhse Coupled Inductor Romeu Husmnn 1, Rodrigo d Silv 2 nd Ivo Brbi 2 1 Deprtment of Electricl nd Telecommuniction Engineering, University of Blumenu FURB Blumenu SC Brzil,
More informationWe are IntechOpen, the world s leading publisher of Open Access books Built by scientists, for scientists. International authors and editors
We re IntechOpen, the world s leding pulisher of Open Access ooks Built y scientists, for scientists 3,5 8,.7 M Open ccess ooks ville Interntionl uthors nd editors Downlods Our uthors re mong the 5 Countries
More informationAnalysis of circuits containing active elements by using modified T - graphs
Anlsis of circuits contining ctive elements using modified T - grphs DALBO BOLEK *) nd EA BOLKOA**) Deprtment of Telecommunictions *) dioelectronics **) Brno Universit of Technolog Purknov 8, 6 Brno CECH
More informationThe Math Learning Center PO Box 12929, Salem, Oregon Math Learning Center
Resource Overview Quntile Mesure: Skill or Concept: 300Q Model the concept of ddition for sums to 10. (QT N 36) Model the concept of sutrction using numers less thn or equl to 10. (QT N 37) Write ddition
More informationABB STOTZ-KONTAKT. ABB i-bus EIB Current Module SM/S Intelligent Installation Systems. User Manual SM/S In = 16 A AC Un = 230 V AC
User Mnul ntelligent nstlltion Systems A B 1 2 3 4 5 6 7 8 30 ma 30 ma n = AC Un = 230 V AC 30 ma 9 10 11 12 C ABB STOTZ-KONTAKT Appliction Softwre Current Vlue Threshold/1 Contents Pge 1 Device Chrcteristics...
More informationLecture 16: Four Quadrant operation of DC Drive (or) TYPE E Four Quadrant chopper Fed Drive: Operation
Lecture 16: Four Qudrnt opertion of DC Drive (or) TYPE E Four Qudrnt chopper Fed Drive: Opertion The rmture current I is either positive or negtive (flow in to or wy from rmture) the rmture voltge is lso
More informationTwo-layer slotted-waveguide antenna array with broad reflection/gain bandwidth at millimetre-wave frequencies
Two-lyer slotted-wveguide ntenn rry with rod reflection/gin ndwidth t millimetre-wve frequencies S.-S. Oh, J.-W. Lee, M.-S. Song nd Y.-S. Kim Astrct: A 24 24 slotted-wveguide rry ntenn is presented in
More informationHigh-resolution ADC operation up to 19.6 GHz clock frequency
INSTITUTE OF PHYSICS PUBLISHING Supercond. Sci. Technol. 14 (2001) 1065 1070 High-resolution ADC operation up to 19.6 GHz clock frequency SUPERCONDUCTOR SCIENCE AND TECHNOLOGY PII: S0953-2048(01)27387-4
More informationPostprint. This is the accepted version of a paper presented at IEEE PES General Meeting.
http://www.div-portl.org Postprint This is the ccepted version of pper presented t IEEE PES Generl Meeting. Cittion for the originl published pper: Mhmood, F., Hooshyr, H., Vnfretti, L. (217) Sensitivity
More informationDirect Current Circuits. Chapter Outline Electromotive Force 28.2 Resistors in Series and in Parallel 28.3 Kirchhoff s Rules 28.
P U Z Z L E R If ll these pplinces were operting t one time, circuit reker would proly e tripped, preventing potentilly dngerous sitution. Wht cuses circuit reker to trip when too mny electricl devices
More informationInterference Cancellation Method without Feedback Amount for Three Users Interference Channel
Open Access Librry Journl 07, Volume, e57 ISSN Online: -97 ISSN Print: -9705 Interference Cncelltion Method without Feedbc Amount for Three Users Interference Chnnel Xini Tin, otin Zhng, Wenie Ji School
More informationDESIGN OF CONTINUOUS LAG COMPENSATORS
DESIGN OF CONTINUOUS LAG COMPENSATORS J. Pulusová, L. Körösi, M. Dúbrvská Institute of Robotics nd Cybernetics, Slovk University of Technology, Fculty of Electricl Engineering nd Informtion Technology
More informationEngineer-to-Engineer Note
Engineer-to-Engineer Note EE-297 Technicl notes on using Anlog Devices DSPs, processors nd development tools Visit our Web resources http://www.nlog.com/ee-notes nd http://www.nlog.com/processors or e-mil
More informationLow noise SQUID simulator with large dynamic range of up to eight flux quanta
Low noise SQUID simultor with lrge dynmic rnge of up to eight flux qunt A. Mrtinez*, J. Flokstr, C. Rillo**, L.A. Angurel**, L.M. Grci** nd H.J.M. ter Brke Twente University of Technology, Deprtment of
More informationDesign and Development of 8-Bits Fast Multiplier for Low Power Applications
IACSIT Interntionl Journl of Engineering nd Technology, Vol. 4, No. 6, Decemer 22 Design nd Development of 8-Bits Fst Multiplier for Low Power Applictions Vsudev G. nd Rjendr Hegdi, Memer, IACSIT proportionl
More informationG9SA. Safety Relay Unit. The G9SA Series Offers a Complete Line-up of Compact Units. Model Number Structure
Sfety Rely Unit G9 CSM_G9_DS_E The G9 Series Offers Complete Line-up of Compct Units. Four kinds of -mm wide Units re ville: A -pole model, -pole model, nd models with poles nd OFF-dely poles, s well s
More informationCONVENTIONAL design of RSFQ integrated circuits
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 19, NO. 3, JUNE 2009 1 Serially Biased Components for Digital-RF Receiver Timur V. Filippov, Anubhav Sahu, Saad Sarwana, Deepnarayan Gupta, and Vasili
More informationLeaky Wave Antennas Designed on a Substrate Integrated Waveguide
Leky Wve Antenns Designed on Sustrte Integrted Wveguide Jn Mchc Czech Technicl University in Prgue, Fculty of Electricl Engineering Technick 2 16627 Prgue 6, Czech Repulic mchc@fel.cvut.cz Astrct This
More informationThe Discussion of this exercise covers the following points:
Exercise 4 Bttery Chrging Methods EXERCISE OBJECTIVE When you hve completed this exercise, you will be fmilir with the different chrging methods nd chrge-control techniques commonly used when chrging Ni-MI
More informationOn the Description of Communications Between Software Components with UML
On the Description of Communictions Between Softwre Components with UML Zhiwei An Dennis Peters Fculty of Engineering nd Applied Science Memoril University of Newfoundlnd St. John s NL A1B 3X5 zhiwei@engr.mun.c
More informationSolutions to exercise 1 in ETS052 Computer Communication
Solutions to exercise in TS52 Computer Communiction 23 Septemer, 23 If it occupies millisecond = 3 seconds, then second is occupied y 3 = 3 its = kps. kps If it occupies 2 microseconds = 2 6 seconds, then
More informationThe Design and Verification of A High-Performance Low-Control-Overhead Asynchronous Differential Equation Solver
he Design nd Verifiction of A High-Performnce Low-Control-Overhed Asynchronous Differentil Eqution Solver Kenneth Y. Yun, Memer, IEEE, Peter A. Beerel, Memer, IEEE, Vid Vkilotojr, Student Memer, IEEE,
More informationHomework #1 due Monday at 6pm. White drop box in Student Lounge on the second floor of Cory. Tuesday labs cancelled next week
Announcements Homework #1 due Mondy t 6pm White drop ox in Student Lounge on the second floor of Cory Tuesdy ls cncelled next week Attend your other l slot Books on reserve in Bechtel Hmley, 2 nd nd 3
More informationExperiment 3: Non-Ideal Operational Amplifiers
Experiment 3: Non-Idel Opertionl Amplifiers Fll 2009 Equivlent Circuits The bsic ssumptions for n idel opertionl mplifier re n infinite differentil gin ( d ), n infinite input resistnce (R i ), zero output
More informationVLSI Design of High-Throughput SISO-OFDM and MIMO-OFDM Baseband Transceivers for Wireless LAN Networks
74 ECTI TRANSACTIONS ON ELECTRICAL ENG., ELECTRONICS, AND COMMUNICATIONS VOL.5, NO.2 August 2007 VLSI Design of High-Throughput SISO-OFDM nd MIMO-OFDM Bsend Trnsceivers for Wireless LAN Networks Shingo
More informationCS2204 DIGITAL LOGIC & STATE MACHINE DESIGN SPRING 2005
CS2204 DIGITAL LOGIC & STATE MACHINE DESIGN SPRING 2005 EXPERIMENT 1 FUNDAMENTALS 1. GOALS : Lern how to develop cr lrm digitl circuit during which the following re introduced : CS2204 l fundmentls, nd
More informationThis is a repository copy of Effect of power state on absorption cross section of personal computer components.
This is repository copy of Effect of power stte on bsorption cross section of personl computer components. White Rose Reserch Online URL for this pper: http://eprints.whiterose.c.uk/10547/ Version: Accepted
More informationThree-Phase Synchronous Machines The synchronous machine can be used to operate as: 1. Synchronous motors 2. Synchronous generators (Alternator)
Three-Phse Synchronous Mchines The synchronous mchine cn be used to operte s: 1. Synchronous motors 2. Synchronous genertors (Alterntor) Synchronous genertor is lso referred to s lterntor since it genertes
More informationCOMPARISON OF THE EFFECT OF FILTER DESIGNS ON THE TOTAL HARMONIC DISTORTION IN THREE-PHASE STAND-ALONE PHOTOVOLTAIC SYSTEMS
O. 0, NO., NOEMBER 05 ISSN 89-6608 ARPN Journl of Engineering nd Applied Sciences 006-05 Asin Reserch Pulishing Network (ARPN). All rights reserved. www.rpnjournls.com OMPARISON OF THE EFFET OF FITER ESIGNS
More informationSoftware for the automatic scaling of critical frequency f 0 F2 and MUF(3000)F2 from ionograms applied at the Ionospheric Observatory of Gibilmanna
ANNALS OF GEOPHYSICS, VOL. 47, N. 6, Decemer 2004 Softwre for the utomtic scling of criticl frequency f 0 F2 nd MUF(3000)F2 from ionogrms pplied t the Ionospheric Oservtory of Giilmnn Michel Pezzopne nd
More informationMesh and Node Equations: More Circuits Containing Dependent Sources
Mesh nd Node Equtions: More Circuits Contining Dependent Sources Introduction The circuits in this set of problems ech contin single dependent source. These circuits cn be nlyzed using mesh eqution or
More informationDesign of UHF Fractal Antenna for Localized Near-Field RFID Application
1 Design of UHF Frctl Antenn for Loclized Ner-Field RFID Appliction Yonghui To, Erfu Yng, Yxin Dong, nd Gng Wng, Memer, IEEE Astrct In this pper, frctl structure is proposed for loclized ner-field UHF
More informationSINGLE FLUX QUANTUM ONE-DECIMAL-DIGIT RNS ADDER
Applied Superconductivity Vol. 6, Nos 10±12, pp. 609±614, 1998 # 1999 Published by Elsevier Science Ltd. All rights reserved Printed in Great Britain PII: S0964-1807(99)00018-6 0964-1807/99 $ - see front
More informationLocalization of Latent Image in Heterophase AgBr(I) Tabular Microcrystals
Interntionl ymposium on ilver Hlide Technology Locliztion of Ltent Imge in Heterophse AgBr(I) Tulr Microcrystls Elen V. Prosvirkin, Aigul B. Aishev, Timothy A. Lrichev, Boris A. echkrev Kemerovo tte University,
More informationAvailable online at ScienceDirect. Procedia Engineering 89 (2014 )
Aville online t www.sciencedirect.com ScienceDirect Procedi Engineering 89 (2014 ) 411 417 16th Conference on Wter Distriution System Anlysis, WDSA 2014 A New Indictor for Rel-Time Lek Detection in Wter
More informationIN the past few years, superconductor-based logic families
1 Synthesis Flow for Cell-Based Adiabatic Quantum-Flux-Parametron Structural Circuit Generation with HDL Backend Verification Qiuyun Xu, Christopher L. Ayala, Member, IEEE, Naoki Takeuchi, Member, IEEE,
More informationD I G I TA L C A M E R A S PA RT 4
Digitl Cmer Technologies for Scientific Bio-Imging. Prt 4: Signl-to-Noise Rtio nd Imge Comprison of Cmers Yshvinder Shrwl, Solexis Advisors LLC, Austin, TX, USA B I O G R A P H Y Yshvinder Shrwl hs BS
More informationTHE Josephson junction based digital superconducting
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 26, NO. 3, APRIL 2016 1300205 Investigation of Readout Cell Configuration and Parameters on Functionality and Stability of Bi-Directional RSFQ TFF Tahereh
More informationY9.ET1.3 Implementation of Secure Energy Management against Cyber/physical Attacks for FREEDM System
Y9.ET1.3 Implementtion of Secure Energy ngement ginst Cyber/physicl Attcks for FREED System Project Leder: Fculty: Students: Dr. Bruce cillin Dr. o-yuen Chow Jie Dun 1. Project Gols Develop resilient cyber-physicl
More informationDigital Encoder for RF Transmit Waveform Synthesizer Amol Inamdar, Deepnarayan Gupta, Saad Sarwana, Anubhav Sahu, and Alan M.
556 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 17, NO. 2, JUNE 2007 Digital Encoder for RF Transmit Waveform Synthesizer Amol Inamdar, Deepnarayan Gupta, Saad Sarwana, Anubhav Sahu, and Alan
More informationExperiment 3: Non-Ideal Operational Amplifiers
Experiment 3: Non-Idel Opertionl Amplifiers 9/11/06 Equivlent Circuits The bsic ssumptions for n idel opertionl mplifier re n infinite differentil gin ( d ), n infinite input resistnce (R i ), zero output
More informationSoft-decision Viterbi Decoding with Diversity Combining. T.Sakai, K.Kobayashi, S.Kubota, M.Morikura, S.Kato
Softdecision Viterbi Decoding with Diversity Combining T.Ski, K.Kobyshi, S.Kubot, M.Morikur, S.Kto NTT Rdio Communiction Systems Lbortories 2356 Tke, Yokosukshi, Kngw, 2383 Jpn ABSTRACT Diversity combining
More information(CATALYST GROUP) B"sic Electric"l Engineering
(CATALYST GROUP) B"sic Electric"l Engineering 1. Kirchhoff s current l"w st"tes th"t (") net current flow "t the junction is positive (b) Hebr"ic sum of the currents meeting "t the junction is zero (c)
More informationDesign And Implementation Of Luo Converter For Electric Vehicle Applications
Design And Implementtion Of Luo Converter For Electric Vehicle Applictions A.Mnikndn #1, N.Vdivel #2 ME (Power Electronics nd Drives) Deprtment of Electricl nd Electronics Engineering Sri Shkthi Institute
More informationComputing Logic-Stage Delays Using Circuit Simulation and Symbolic Elmore Analysis
Computing Logic-Stge Delys Using Circuit Simultion nd Symolic Elmore Anlysis Clyton B. McDonld Rndl E. Brynt Deprtment of Electricl nd Computer Engineering Crnegie Mellon University, Pittsurgh, PA 15213
More informationREVIEW QUESTIONS. Figure 2.63 For Review Question 2.6. Figure 2.64 For Review Question The reciprocal of resistance is:
EVIEW QUESTIONS 2.1 The reciprocl of resistnce is: () voltge () current (c) conductnce (d) couloms 2.2 An electric heter drws 10 A from 120-V line. The resistnce of the heter is: () 1200 () 120 (c) 12
More informationModeling of Conduction and Switching Losses in Three-Phase Asymmetric Multi-Level Cascaded Inverter
Proceedings of the 5th WEA nt. onf. on Power ystems nd Electromgnetic omptibility, orfu, Greece, August 23-25, 2005 (pp176-181) Modeling of onduction nd witching Losses in Three-Phse Asymmetric Multi-Level
More informationNevery electronic device, since all the semiconductor
Proceedings of Interntionl Joint Conference on Neurl Networks, Orlndo, Florid, USA, August 12-17, 2007 A Self-tuning for Rel-time Voltge Regultion Weiming Li, Xio-Hu Yu Abstrct In this reserch, self-tuning
More information