Open Access A Novel Parallel Currentsharing Control Method of Switch Power Supply


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1 Send Orders for Reprints to 170 The Open Electricl & Electronic Engineering Journl, 2014, 8, Open Access A Novel Prllel Currentshring Control Method of Switch Power Supply Cho Wu, Bingjun Lu nd Yuwng Ge * Deprtment of Electricl Engineering nd Automtion, Luoyng Institute of Science nd Technology, Henn, Chin, Astrct: A novel prllel currentshring control method of switch power supply is proposed, on the sis of detiled nlysis of severl common prllel currentshring control methods nd recent relted ptents. Only the current of switch power modules with mximum nd minimum output current will e regulted, which is selected y the extreme current selection circuit in this method. Four cses with different extremum sitution re discussed, nd in ech cse, principles nd equtions re given. Finlly the currentshring control of switch power supply prllel system is relized. Experimentl results show tht the currentshring method is resonle nd effective. Keywords: Currentshring control, extreme current selection circuit, switch power supply. 1. INTRODUCTION With the development of power electronics technology, switch power supply hs widely emerged in fields of computer, industry nd communiction. Prllel rchitecture is commonly used, which comines multiple power modules into highpower supply, tht is, distriuted power, to improve output nd reliility. The modules in distriuted power supply re independent nd flexile, whose cpcity cn e expnded ccording to lod. The stndrdized module system reduces volume, weight s well s the cost. In distriuted power genertion, inconsistency etween prllel modules my occur. In this cse, power modules with good externl chrcteristics my sustin more current or even result in overlod which gretly reduces their service lives. Currentshring control is necessry for prllel power system. It gurntees current lnce nd resonle lloction etween prllel power modules nd prevent certin modules from overlod. In this pper, fter reviewing severl common prllel currentshring control strtegies, novel strtegy is proposed. It selects the mximum nd minimum output switch power supply modules with extremum current selection circuit nd regultes the current through them. Experiments indicte its good effectiveness nd resonleness. 2. COMMON PARALLEL CURRENTSHARING CONTROL STRATEGIES In order to relize uniform current distriution mong prllel power modules, mny currentshring control strtegies hve een rised nd developed [1]. The most common methods re externl chrcteristics drooping (output impednce method), mster/slve module setting nd ctive currentshring Externl Chrcteristic Drooping (Output Impednce Method) Externl chrcteristic drooping [2] regultes output impednce to chieve current shring. Every module in prllel system works independently, whose current is determined y its externl chrcteristics nd output impednce. This strtegy is simple without ny dedicted equipment for its openloop chrcter. However the method is not ccurte enough, so individul chnges hs to e performed. Besides, power differences mong prllel modules will induce unlnced current mong modules Mster/Slve Module Setting Mster/slve module setting method [3] selects one of the prllel modules s mster module, while others s slve modules. Current of mster module is compred with feedck signl, nd trnsmits the difference to control circuits of ll modules (including mster nd slve) to regulte the output current of modules. Mster/slve module setting method is closedloop without ny dedicted control element, so its ccurcy is higher. However, communictions is required mong modules, which mkes complex connection. Furthermore, if mster module fils, the whole power system will crsh, nd it is not suitle for redundnt prllel system Active CurrentShring Active currentshring includes uto verge current shring nd uto mximum current shring [4]. Auto verge current shring connects current mplifier output of ll prllel power modules to pulic us through resistor R, which is clled currentshring us. Its lock digrm is shown in Fig. (1). As we cn see, this topology is not complex with cceptle ccurcy; however, if currentshring us is short or ny module connected with us fils, the verge voltge of us s well s other module is reduced. So this method is not suitle for prllel power sys / Benthm Open
2 A Novel Prllel Currentshring Control Method The Open Electricl & Electronic Engineering Journl, 2014, Volume Block Digrm Vin Switch Power Module Tc Output Current Io Lod Vr Vr ΔVr Current Amp VI Ve R Currentshring Bus Currentshring Controller Fig. (1). Block digrm of uto verge currentshring method. Block Digrm Vin Switch Power Module Tc Output Current Io Lod Vr Vr ΔVr Current Amp VI Ve D Currentshring us V Currentshring Controller Fig. (2). Block digrm of uto mximum currentshring method. tem with utowithdrwl mechnism when power module filing. Auto mximum current shring is dynmic method which determines mster module utomticlly ccording to mximum output current. The differences etween mster module nd slve modules re regulted respectively to regulte the current distriution, so it s clled uto mster/slve control method. Its lock digrm is shown in Fig. (2). The prllel power sources re not isolted ut connected through currentshring us. It provides current reference to every module nd regultes output current ccording to the reference so tht ccurte currentshring is chieved mong prllel modules. This topology is proved to e good redundnt system, voiding system performnce degrdtion due to one single module fult. However, mster/slve modules re switching ll the time, nd it will result in low frequency oscilltion t output current; esides, power modules regulte the output ccording to mximum current, it mens ll power modules except mster will increse output current. With constnt lod, current increments mong slve modules re greter thn current reduction of mster module, which results in output voltge eing higher thn rted voltge (known s overvoltge ). Overvoltge my hve some d influence on sfety, reliility nd stility of power system nd it will reduce the system dynmic response Other Advnced CurrentShring Methods There re other common methods such s therml stress uto method which monitors the temperture to chieve currentshring nd externl controller method which dds dedicted controller for mngement nd control. As well s the methods mentioned ove, we cn see tht trditionl currentshring methods hve their own merits s well s their own demerits. So, nowdys reserchers hve focused on novel currentshring topology to improve performnce. One of the most fmous is nmed "Control circuit nd method of prllel DC switch power source with doule currentshring uses" [5]. The inventor lso rised 4 currentshring method sed on intelligent controller (CPU) (shown in Fig. 3). The system proposed depends gretly upon processor nd softwre progrmming, which increses the totl cost. Also we listed the currentshring method proposed to see if it is possile to e improved: 1. Currentshring sed on minimum current: processor of every power module clcultes minimum current ccording to signl from the first nd second currentshring us. Tke the minimum output current s reference, every power module ut the module with minimum output will reduce its current which results in current decrement of ll current modules eing greter thn the current increment. It mens
3 172 The Open Electricl & Electronic Engineering Journl, 2014, Volume 8 Wu et l. Power Module 1 Voltge Detection Current Detection DC Power Supply Lod PWM genertor U I Currentshring us 1 Currentshring genertion Currentshring us 2 CPU ADC I Mx I Min Power Module N Fig. (3). Control circuit nd method of prllel DC switch power source with doule currentshring uses. totl output of power modules is smller thn the rted voltge, nmed s "undervoltge". "Undervoltge" cnnot fulfill the power requirement of lod, nd increses regulting frequency of system pssively. 2. Simplified minimum current control method: CPU of every module compres its own output current signl with mximum current to see if the module is the module with mximum current. Only the module with mximum current will e regulted, referred s minimum current, while other modules won't e involved. Since the output current of mximum module is reduced, in cse of constnt lod, current of other modules will increse so tht some module will replce s the mximum module nd e regulted. In this wy, the regulting frequency is much higher thn theoreticl vlue. Moreover, if there re more thn one modules with mximum output current, they will e regulted simultneously y minimum current nd other modules my e influenced even strongly, which increses regulting frequency nd ffects dynmic response of system. 3. Currentshring sed on middle current: CPU clcultes middle current (not verge current) ccording to the difference etween mximum current nd minimum current, nd tkes the middle current s reference to regulte outputs. Modules with lower current will increse their currents while modules with higher current will decrese their currents. However, every module in system will e regulted so regulting frequency is much greter thn (1) nd (2). 4. Simplified middle currentshring method: CPU of every module compres its own output current signl with mximum nd minimum current to see if the module is the module with mximum or minimum current. Only the module with mximum or minimum current will e regulted, referred s middle current clculted in (3), while other modules won't e involved. Since the output current of mximum module is reduced nd minimum module is incresed, in cse of constnt lod, current of other modules will chnge so tht some module will replce s the mximum nd minimum module nd e regulted. In theory, only two modules re regulted t the sme time nd frequency my e low, ut the two modules themselves re switching ll the time. Besides, they're regulted ccording to middle vlue rther thn verge vlue. All these fcts increse theoreticl frequency. If there re more thn one module with mximum or minimum output currents, nd current decrement of ll current modules my not e equl to the current increment due to the complexity of system. So "overvoltge" or "undervoltge" will occur. Other reserchers such s in [6] proposed power supply with currentshring function using us terminl s currentshring control interfce. The power circuit provides n output voltge nd n output current to n output terminl which genertes currentsense signl ccording to the output current. A feedck control circuit controls the power circuit ccording to the output of the powersupply pprtus. A currentshring unit genertes nd outputs us signl to the us terminl ccording to the currentsense signl [7]. Declred power system with comintion of ctive current shring nd droop current shring (shown in Fig. 4). The power system includes system lod nd multiple power supplies connected with ech other nd connected to the system lod. Active current shring circuit selects its opertion mode depending on whether the lod current is higher thn first current set point, while droop current
4 A Novel Prllel Currentshring Control Method The Open Electricl & Electronic Engineering Journl, 2014, Volume Feedck Power Supply System Lod Power Supply Feedck And/Or Droop Current Shring Current Detecting Current Detecting Droop Current Shring And/Or Active Current Shring Active Current Shring Fig. (4). Power system with comintion of ctive currentshring nd droop current shring. Vin Element 1 Vo mximum current selection us A Element 2 Lo d D11 D21 D31 Dn1 Element 3 Io Element n D12 D22 D32 minimum current selection us B Dn2 extreme current selection circuit Fig. (5). Block digrm of the novel currentshring method. shring circuit depends on whether the lod current is higher thn second current set point. [8] Rised the rchitecture with multiple chnnels. Ech chnnel hs current shring controller tht is coupled to shred current nd voltge signl us. In recent yers, mny reserchers hve chieved their gols s currentshring hs een grnted ptents [912]. Resonle prllel control topology ecomes key issue for improving system reliility nd cpcity. While through the nlysis ove, we find tht much work hs een crried out in improving currentshring. However, with the incresing requirement towrds reliility, dynmic response, cpcity redundncy nd reltime chrcter, we need to propose novel nd more rtionl control method [1315]. 3. A NOVEL CURRENTSHARING METHOD To improve the performnce of prllel switch power supply, novel currentshring method is proposed in this pper, whose digrm is shown in Fig. (5). Every element of prllel switch power supply consists of power module nd control circuit, whose output current represented y voltge signl is connected to one couple of seril diode with extremum current selection circuit. So, n elements require n couples of seril diodes. Upper rms (Common cthode) of the diodes constitute mximum current selection us, while lower rms (Common node) constitute minimum current selection us. The two uses re connected through us isoltion resistor R m. Extremum current selection circuit consisted of n couples of diodes work s nphse circuit. Only the voltge (representing current) from mximum current output module cn rech mximum current selection us nd the voltge from minimum current output module cn rech minimum current selection us. Current induced y the voltge difference etween the two uses forms devition voltge V e cross isoltion resistor R m, which forms new reference voltge V r with initil reference voltge V r. The new vlue controls power module to relize currentshring. Block digrm of the novel system is shown in Fig. (6). Running/fult indictor of power module is provided in this currentshring topology for redundncy rchitecture so tht if one of the power modules fils, the system will not crsh. In Fig. (6), if one of the power modules fils, output voltge of current detection circuit flls to zero nd the optocoupler is disconnected, which mkes rely lose power. Then fulty module is isolted from system nd fult indictor is turned on. In this wy, system reliility is improved.
5 174 The Open Electricl & Electronic Engineering Journl, 2014, Volume 8 Wu et l. Block Digrm Vin Switch Power Module Tc Current Detection VI Extreme current selection circuit Vr ΔVr  Ve + Currentshring Controller Rg Vcc Rj Rely1 VD Rd Running LED Output Current Io Rz J Lod Vr Fult LED Optocoupler Extreme current selection circuit Jk Fig. (6). Block digrm of sic element. 4. MECHANISM OF THE NOVEL CURRENT SHARING METHOD This currentshring strtegy otins voltge vlues V I1 V I2...V In, which represent the current from every module, through current detection circuits, nd trnsmits the extremum vlue to selection circuit. The uses will get the elements with mximum nd minimum current outputs, represented s V I_mx nd V I_min. The difference etween V I_mx nd V I_min forms current through nd R m, nd the voltge required y mximum nd minimum current modules V e_mx = U > 0 nd V e_min = U < 0 cn e clculted. The clcultion process should e differentited into four ctegories nd hndled ccordingly: (1) i = 1, j = 1: In this cse, only one mximum nd minimum output current modules exist, whose equivlent circuit is shown in Fig. (7). We get: V e_ mx =!V e_ min "V e_ mx =!V e_ min (1) (2) i = 1, j > 1:In this cse, one mximum nd j minimum output current modules exist, whose equivlent circuit is shown in Fig. (7). We get: V e_ mx =! V e_ min_1! V e_ min_ 2!...! V e_ min_ j V e_ mx =!V e_ min_1!v e_ min_ 2!...!V e_ min_ j (3) (2)!V e_ min = V e_ mx_1 + V e_ mx_ V e_ mx_ i!v e_ min = V e_ mx_1 +V e_ mx_ V e_ mx_ i (6)!V e_ min > V e_ mx_1 = V e_ mx_ 2 =... = V e_ mx_ i (7) (4) i > 1, j > 1: In this cse, i mximum nd j minimum output current modules exist, whose equivlent circuit is shown in Fig. (7d). We get: V e_ mx_1 + V e_ mx_ V e_ mx_ i =! V e_ min_1! V e_ min_ 2 V e _ mx_1 V e _ min_ 2!...! V e_ min_ j + V e _ mx_ 2... V V e _ min_ j e _ mx_ i = V This sitution hs multiple possiilities: 1. i = j V e_ mx_1 = V e_ mx_ 2 =... = V e_ mx_ i =!V e_ min_1 =!V e_ min_ 2 =... =!V e_ min_ j 2. i < j e _ min_1 (5) (8) (9) (10) V e_ mx >!V e_ min_1 =!V e_ min_ 2 =... =!V e_ min_ j (3) i > 1, j = 1: In this cse, one minimum nd i mximum output current modules exist, whose equivlent circuit is shown in Fig. (7c). We get: (4) V e_ mx_1 = V e_ mx_ 2 =... = V e_ mx_ i >!V e_ min_1 =!V e_ min_ 2 =... =!V e_ min_ j 3. i > j (11)
6 A Novel Prllel Currentshring Control Method The Open Electricl & Electronic Engineering Journl, 2014, Volume VI_mx VI_min VI_mx VI_min_1 VI_min_ j Current Direction Current Direction ) ) VI_mx_1 VI_mx_i VI_min VI_mx_1 VI_mx_i VI_min_1 VI_min_ j Current Direction Current Direction c) d) Fig. (7). Extreme current selection circuit when. ) i = 1, j = 1 ; ) i = 1,j > 1 ; c) i > 1, j = 1 ;d) i > 1, j > 1 V e _ mx_1 V e _ min_1 = V e _ mx_ 2 = V e _ min_ 2 =... = V e _ mx_ i =... = V < e _ min_ j Conclusion cn e drwn from the nlysis of 4 cses: (12) If i > j, s to sy the numer of mximum current modules is greter thn minimum ones, the verge current is close to mximum current. Extreme current selection circuit gurntees the current decrement of every mximum current module is smller thn the current increment of every minimum current module; If i < j, s to sy the numer of minimum current modules is greter thn mximum ones, the verge current is close to minimum current. Extreme current selection circuit gurntees the current decrement of every mximum current module is greter thn the current increment of every minimum current module; If i = j, s to sy the numer of minimum current modules is equl to mximum ones, the verge current is close to the verge vlue of mximum nd minimum current. Extreme current selection circuit gurntees the current decrement of every mximum current module is equl to the current increment of every minimum current module; current decrement of i mximum current modules nd current increment of j minimum current modules lwys keep equilirium. In cse of constnt lod, only (i+j) modules with mximum or minimum current output re regulted, which reduces the regulting frequency of the entire system. Low frequency oscilltion of output current is effectively voided to improve system dynmic response. To summrize, the most ovious fether of our method lies in tht: through extremum vlue selection circuit, sic element with mximum nd minimum output current is determined nd regulted, nd only the selected modules will e controlled. Detiled steps re descried s follows: 1: Determine the given voltges of every element: V r1 = V r2 = V r3 =... = V rn ; 2: Otin output current of elements through current detection circuit, which is converted into voltge signls representing current, nd sent to the optocoupler of running/fult indictor; 3: If element opertes t running stte, the voltge V I ecomes greter thn zero nd rely coil in running/fult indictor is on so tht normllyopen contcts of rely is closed. Running indictor is switched on while fult one is off, the element is regulted; 4: If element opertes t fult stte, the voltge V I stys round zero nd rely coil in running/fult indictor is off so tht normllyopen contcts of rely is opened. Running indictor is switched off while fult one is on, the element will not e regulted; 5: V I1,V I2,V I3,...V In from every element is sent to extremum vlue selection circuit, through which i elements with mximum current output nd j elements with minimum current output will e determined y the uses; 6 The voltge difference etween V I_mx nd V I_min psses through resistor R m nd, nd V e_mx nd V e_min re clculted s the voltge cross ; 7: V e_mx is trnsmitted currentshring controller of the mximum current element to otin given voltge difference Δ V r_mx. Then Δ V r_mx s well s reference V r re sent to sum controller nd control voltge V r_mx ' is clculted; 8: V e_min is trnsmitted currentshring controller of the minimum current element to otin given voltge difference Δ V r_min. Then Δ V r_min s well s reference V r re sent to sum controller nd control voltge V r_min ' is clculted; 9: V r_mx ' is utilized to decrese the output current of mximum current element while V r_min ' is to increse the output
7 176 The Open Electricl & Electronic Engineering Journl, 2014, Volume 8 Wu et l. Fig. (8). Experimentl dt of currentshring control. Tle 1. Experimentl dt of currentshring control. Lod1 Lod2 Lod3 I o1/a I o2/a I o3/a I o4/a I o5/a I o/a I v/a I error/a error% current of minimum current element, which ensures the current decrement of ll current modules is equl to the current increment so tht other elements will not e ffected. In this wy, regulting frequency of system cn e gretly reduced; 10: After the mximum nd minimum elements re regulted, system will strt to select new mximum nd minimum elements nd repet the regulted process until output current of every element ecomes lnced. Block digrm of proposed system is shown in Fig. (6). 5. EXPERIMENTAL RESULT AND ANALYSIS OF CURRENT SHARING To vlidte the currentshring control effect of multiple prllel power modules, experimentl system with 5 switch power modules (48V/10A) is designed in cse of pure resistive lod nd mesured currents through the lod nd every power module with oscilloscope. Experimentl dt re shown in Tle 1. The currents fter regultion re listed for comprison nd in Fig. (8), histogrm is shown to give n intuitive view of results. From the experimentl dt in Tle 1, it s cler tht the unlnced degree with light lod is out 3% while 1.89 with hevy lod. Unlnced degree will e less thn 5% with 1545A lod, whose dt re not listed in this pper for spce considertion. Results shown ove relize uto currentshring effectively with good ccurcy nd reliility. 6. CURRENT AND FUTURE DEVELOPMENTS The pper hs reviewed common prllel currentshring control methods nd recent relted ptent [1619], nd pre
8 A Novel Prllel Currentshring Control Method The Open Electricl & Electronic Engineering Journl, 2014, Volume sented novel method. The extreme current selection circuit consists of resistors nd diodes nd selects mximum nd minimum output current modules with uses. In this method proposed, only modules with mximum or minimum current output in current condition re regulted, which improves system dynmic response. Moreover, only hrd distriuted hrdwre such s resistor nd diode re used to chieve currentshring mong prllel systems rther thn intelligent controller (CPU) nd complex progrmming, which gretly reduces the cost of power supply. Running/fult indictor of power module is provided for redundncy rchitecture. All these fethers ensure the leding position in currentshring field of our method. Through current tuning, the effective currentshring control is chieved. Finlly experimentl result demonstrtes the good performnce of our novel control strtegy. CONFLICT OF INTEREST The uthors confirm tht this rticle content hs no conflict of interest. ACKNOWLEDGEMENTS This work ws supported in prt y Nturl Science Reserch Project of Eduction Deprtment in Henn Province ( ). REFERENCES [1] X. S. Zhn, "Technique of prllel lnced current in smps", Agriculture nd Technology, vol. 29, no. 3, pp , [2] Y. F. Go, nd X. J. Hu, "Prllel currentshring system in locking switch power supply", Chinese Journl of Power Sources, vol. 35, no. 2, pp , [3] Y. P. Zhong, nd Z. C. Wei, "Study on Current Shring of A Lrge Cpcity Switching Power in Prllel", Power Electronics, vol.39, no. 6, [4] S. L. Du, nd P. Wng, "A control strtegy for prllel current shring technology in switching power supply", Chinese Journl of Power Sources, vol. 36, no. 7, pp , [5] Q. Zhng, nd X. L. Yo, "Control circuit nd method of prllel DC switch power source with doule currentshring uses," Chin Ptent , My 19, [6] T. Y. Yng, "Power supply with currentshring control nd currentshring method thereof," U. S. Ptent 37,523,944, June 8, [7] C. C. Hsu, nd C. C. Yeh, "Power system with comintion of ctive current shring nd droop current shring nd power system ssemly using the sme," U. S. Ptent 50,099,567, Jnury 2, [8] K. Siri, "Current shring power system," U. S. Ptent 44,656,308, Mrch 24, [9] C. S. Lee, nd S. C. Lee, "Currentshring power supply pprtus with ridge rectifier circuit," U. S. Ptent 43,756,483, Septemer 18, [10] K. J. Buterugh, "Dynmiclly configuring current shring nd fult monitoring in redundnt power supply modules," U. S. Ptent 41,567,989, April 30, [11] C. S. Lee, nd S. C. Lee, "Currentshring power supply pprtus with ridge rectifier circuit," U. S. Ptent 43,756,483, Septemer 18, [12] J. Brrenscheen, "System nd method for trnsmitting current shring informtion mong prlleled power trins," U. S. Ptent 42,221,080, Decemer 19, [13] J. B. Wng, R. Lo, nd J. H. Chng. "Prlleled DC/DC Converter Vi Primry Current Droop Current Shring Control". In: Interntionl Conference on PEDS, 2009, pp [14] J. Sun, nd Q. Liu, "A Current Shring Control Strtegy Of Prlleled Dc/Dc Converter Bsed on Simple Model". In: Interntionl Conference on PEDS Optics, Photonics nd Energy Engineering, 2010, pp [15] C. H. Cheng, P. J. Cheng, nd M. J. Xic, "Current shring of prlleled dc/dc converters using gsed pid controllers", Expert Systems with Applictions, vol. 1, pp , [16] S. J. Guo, nd B. Yi, "Currentshring of prlleled control technology for improved switch power supply modules", Chinese Journl of Power Sources, vol. 37, no. 4, pp , [17] Y. Q. Liu, nd S. X. Dun, "An improved current shring control strtegy for prllel inverter system", Power Electronics, vol. 41, no. 6, pp. 89, 26, [18] Q. Zhng, nd X. L. Yo, "Current shring control in the prllel opertion of dc power supplies", Power Electronics, vol. 45, no. 4, pp , [19] X. J. Zuo, nd Y. Yng, "Design of prllel currentshring in switch power supply", Journl of Qingdo University(Engineering & Technology Edition), vol. 27, no. 3, pp , Received: Septemer 22, 2014 Revised: Novemer 03, 2014 Accepted: Novemer 06, 2014 Wu et l.; Licensee Benthm Open. This is n open ccess rticle licensed under the terms of the Cretive Commons Attriution NonCommercil License ( which permits unrestricted, noncommercil use, distriution nd reproduction in ny medium, provided the work is properly cited.
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