THE Josephson junction based digital superconducting

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1 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 26, NO. 3, APRIL Investigation of Readout Cell Configuration and Parameters on Functionality and Stability of Bi-Directional RSFQ TFF Tahereh Jabbari, Hesam Zandi, Farshad Foroughi, Ali Bozbey, and Mehdi Fardmanesh, Senior Member, IEEE Abstract Considering the two main categories of rapid single flux quantum gates with destructive and nondestructive readout process, we have investigated the effects of readout cell topology and involved critical parameters on the proper functionality and stability of the states of the newly developed bidirectional T flip-flops (TFFs). It is observed that instabilities and fluctuations in the state of the gate (memory of TFF) after each transition determine the minimum time intervals between the clock pulses set by the ac bias current, further limiting the ultimate operation frequency of the circuits. The absolute values of the current levels of the junctions at each state, which play an important role in the behavior of the cell, are studied, and their variations over several consequent pulses are stabilized by optimizing the cell parameters. The appropriate values of the circuit and junction parameters are found, resulting in the optimum operation of the circuit for having the best margins possible. We report on the investigated circuit topology and parameter optimizations of the readout circuit of the considered bidirectional TFF. Index Terms NDRO, rapid single flux quantum (RSFQ), superconductivity, TFF. I. INTRODUCTION THE Josephson junction based digital superconducting circuits have ultra-high speed with ultra-low power circuit technology especially for digital applications [1]. Digital superconducting technology, with only a modest number of researchers worldwide, has yielded some of the world s highest digital performance in mixed-signal circuits [2]. This technology offers a way to developed operating frequency of about 770 GHz which is already above the limits of the semiconductor technology or available devices. This technology also significantly reduces the power consumption as well as the complexity and cost of the systems [3], [4]. The leading digital superconducting logic is the rapid single flux quantum (RSFQ) family [5] [7], in which the SFQ pulses pass between the cells in a very short time and modify the state Manuscript received September 8, 2015; accepted December 29, Date of publication January 12, 2016; date of current version February 1, T. Jabbari, H. Zandi, and M. Fardmanesh are with the School of Electrical Engineering, Sharif University of Technology, Tehran , Iran ( fardmanesh@sharif.edu). F. Foroughi is with the Quantum Technology Group, Second Institute of Physics, RWTH University, Aachen 52062, Germany ( forooghi. farshad@gmail.com). A. Bozbey is with the Department of Electrical and Electronics Engineering, TOBB University of Economics and Technology, Ankara 06560, Turkey ( bozbey@etu.edu.tr). Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TASC of the circuits [8]. Elementary cells in this circuit family can generate, pass, memorize, and reproduce picosecond voltage pulses but with a nominally quantized area of the pulse corresponding to transfer of a single magnetic flux quanta across the Josephson junctions. Each cell can be viewed as a combination of a logic gate and an internal memory (loop) controlled by input SFQ pulses [6]. The latching of the data is essential in this electronics family, while its pulse-driven nature requires rigid stable states [9]. In conventional RSFQ logic, such loops are constructed having separable stable states, e.g., by using asymmetric bias currents. The switch operations are also obtained by controlling the direction of the bias current applied to the Josephson junction [10]. Memory loops must be designed to have exactly two stable states for binary data representation, although in modern RSFQ circuits, a bi-directional design has been emerging which has three stable states in corresponding loops [11] [14]. There are two advantages of using such bi-directional RSFQ logic, including: more energy-efficient computation and flexibility in design. These points make bidirectional RSFQ logic compatible with ultra-low-temperature quantum computers. These circuits might be powerful tools in next-generation supercomputers [12], [13]. In bi-directional design, the information unit as a bit data is again stored in the internal loop, and is controlled by the input positive/negative SFQ pulse. In this manner, digital conceptual circuits such as TFF, DFF, and famous gates can be implemented, considering the novel bi-directional logic [15]. There are experimented bi-directional RSFQ circuits including digital SQUID and up/down counter with fewer number of Josephson junctions with respect to uni-directional RSFQ circuits [12]. Investigation of the bi-directional RSFQ circuits has become a concern and more attractive circuits are being suggested. In this logic, digital information is coded as negative and positive pulses. In this work, the bi-directional circuit operation as an up/ down counter is studied. This circuit can be used in digital SQUID s application based on decreasing/increasing the external magnetic field. The readout part of the bi-directional circuit is designed and the stability of the functioning of the cell versus the configuration, parameters of the readout circuit, and the fluctuations in output pulses are investigated. II. BI-DIRECTIONAL RSFQ TFF We studied an up/down counter that is introduced based on bi-directional logic. Accurate timing is necessary for these IEEE. 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2 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 26, NO. 3, APRIL 2016 Fig. 1. Schematic of a single-bit bidirectional counter. circuits. AC current bias is used as the clock signal and determines the circuit frequency. In bi-directional counter, when a pulse arrives at the input, the internal register and a ripple carry-out pulse (RCP) output signal are updated. The positive and negative pulses are defined as below: The positive pulse at the input means the counter is going to be incremented, the negative pulse at the input means the counter is going to be decremented. If the register state is 1, it changes to 0 and no RCP signal is generated. But if the state is 0, it changes to 1 and a negative RCP signal will be produced. Fig. 1 shows the simplified schematic of the designed bidirectional counter based on T flip-flop (TFF). This circuit is similar to the counter in uni-directional RSFQ logic, but the current source I 2 is added which results in an asymmetry in the loop operation. This asymmetry gives the circuit the ability to count the positive and negative pulses. The junctions J1 and J2 in Fig. 1 are used as the buffer and pulse splitter in the input port. The pulses are split into separate two pluses and guided to the Junctions J3 and J4. These junctions along with the inductance L3 form a superconducting loop which would be the memory, the internal register of the counter. The loop has three stable states. These three states include the state 0, absence of the flux quanta, state 1, the presence of the positive flux quanta (clockwise circulating current), and the third state is the presence of the negative flux quanta (counter clockwise circulating current). The later state is out of reach based on the structure of the circuit consisting current sources I 1 and I 2.I 1 is positive in positive half cycles and biases J3 close to 70% of its critical current, whereas the I 2 is off. In negative half cycles, I 2 is negative and keeps J4 current about 70% of its critical current and I 1 is off. Considering these conditions for current sources, the loop is not able to have negative flux quanta. In positive half cycles, an arriving positive input pulse switches J3 or J4 whether the memory state is 0 or 1, and the corresponding junction goes to voltage state and the superconducting loop generates or breaks. In negative half cycle, an arriving negative input pulse switches J4 or J3 whether the memory state is 0 or 1, and the superconducting loop generates or breaks. Fig. 2 shows the input and output pulses of the bi-directional counter and the circulating current of the Fig. 2. (a) Output and input pulses. (b) Loop circulating current. loop. The simulation results are obtained using Linux based Josephson junction circuit simulation program. In the considered fabrication technology, junctions are designed to work in over-damped condition with proper McCumber parameter (β <1) having 1 kacm 2 critical current density and 5 pf per unit area capacitance. Reading the bi-directional memory cell is essential; using the bi-directional logic on the bi-directional counter, we designed other lateral bi-directional SFQ parts such as readout circuit. Therefore, we have suggested and designed a bi-directional non-destructive readout circuit based on bi-directional counter/ memory. Considering the introduced bi-directional NDRO up/down counter, one can read the internal state of the memory without changing the state in bi-directional logic. III. READOUT CIRCUIT FOR BI-DIRECTIONAL TFF We investigated the primary schematic design of the bidirectional readout circuit for bi-directional counter based on TFF, which is shown in Fig. 3 [15], [16]. This cell has separate nondestructive readout input (V NR ) and output (S) ports. The junctions J2, J3, J4, and J5 are connected to the flux storing loop, and are directly affected by the stored flux in the loop which ensures nondestructive readout of the cell content without generation of the SFQ pulses at the output port TFF. The output pulse at the terminal S can be induced by the signal V NR, if and only if the internal memory is in the state 1, whereas the readout circuit does not reset the state of the memory with any arriving pulse from port V NR. When the memory state is 0 and no flux quantum is stored in the loop, J5 current is much lower than its critical current value. Hence when the readout pulse arrives from the input port V NR, J4 as the input buffer is being switched and other junctions remain

3 JABBARI et al.: FUNCTIONALITY AND STABILITY OF BI-DIRECTIONAL RSFQ TFF Fig. 4. Final schematic of the bidirectional NDRO cell. Fig. 3. Schematic of readout circuit for the bidirectional counter. unchanged. So no SFQ pulse is produced at the readout output port S, which means the state 0 is read. In the other case, when the state is 1, the junctions J5 and J2 are biased close to their critical current values. Thus if the incoming readout pulse arrives, the junctions J2, J4, and J5 are switched and a SFQ pulse is generated at the output port S. This is while, when an input pulse changes the state of the internal memory, the junction J3 is switched and prevents the readout output port to be affected by the incoming pulse. This junction also prevents any possible unwanted flux loops formed by the readout circuit. Investigating the effect of modifying the critical current of J3 on the appearance of the output readout pulses, we obtained the optimized value, whereas the circuit is stable and it has the proper response and minimum fluctuations in the readout output SFQ pulses. Amount of passing current through J4 is another important factor of the reading process. The current level of J4 has different values in each memory state. We controlled the passing current through J4 by modifying the value of the input inductance of the readout part. Consequently, due to merging input current and the loop current, we achieved the optimal values for the critical current of J4 and the input inductance leading to the proper functioning of the circuit in both states. We also found the optimized parameters of J2 for nondestructive reading of the memory. In state 1 by switching J5, the input current passes through the J2, which will be switched for protection of the memory. Then the readout part produces the SFQ pulse at its output port. The input port has to be open circuit after arriving SFQ input pulse. Therefore in simulations, connection configuration of the input source of SFQ pulse has to be considered precisely. By optimization of the circuit elements and an input SFQ pulse to reach the correct functioning, we found the optimal values for the input source and effective parameters on the storage path (input source, L4, J4, L5, and J5). Comparing to uni-directional cells, the bi-directional readout circuit has an AC bias current which serves as a clock signal and sets the operating frequency. While the fundamental structure of the uni-directional cell is used in the designed bi-directional circuit, the input and output JTLs and the circuit parameters are modified being different from that of the unidirectional cell to obtain the proper functioning and interfacing between the cells. All junctions in the considered technology are shunted with appropriate corresponding resistances tuning the McCumber parameter to eliminate the effect of the hysteretic I-V characteristics. Simulations of the conventional readout circuits of the uni-directional cells has revealed fluctuations and instabilities in the current levels of the junctions and the output response, more detailed description of which is studied and reported in [14]. IV. DESIGN AND OPTIMIZATION OF THE BI-DIRECTIONAL CELL We have investigated the possible designs of the bidirectional TFF topologies and the corresponding readout part. Fig. 4 shows the schematic of the designed bi-directional NDRO cell based on bi-directional TFF and modified design of the readout circuit. The memory operation of the cell is completely similar to that of the bi-directional TFF. The model shown in Fig. 4 has two output ports: the main output of TFF and the readout output port. Readout input pulses are applied by an external circuit and assumed as positive SFQ pulses. Therefore, the readout part can only read in the positive half cycles. In positive half cycles the readout output shows the state of the internal memory if a SFQ pulse is applied to V NR. Considering a situation in which an input pulse of the readout part (positive SFQ) arrives in a negative half cycle, we have added a block to preserve the applied pulse till the next positive half cycle. For holding the input pulse, we used an AND block including a D Flip Flop (DFF) at the input of the designed bi-directional NDRO. The final schematic of the cell with most effective values of the critical elements that is connected to the AND gate block is shown in Fig. 4. The configuration for the input pulses of the AND gate is also included in Fig. 4, which is for the generation of the input pulses of the readout circuit and a SFQ pulse train that is applied only in the positive half cycles. This pulse train can be constructed by a uni-directional DC/SFQ circuit. As observed in our simulations, the circulating current in the negative half cycles can strongly affect the performance of the readout part of the cell. In logic overview, we will have the

4 IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, VOL. 26, NO. 3, APRIL 2016 carry output pulse after two input pulses. Hence, the appropriate possible connections of the output port and the readout circuit is investigated and the proper configuration is chosen as the connection node B in the figure, in which after every evennumbered of the input, a SFQ pulse appears at the node. For correct operation of the cell in the negative half cycle, we have investigated the effect of the critical currents of the most effective junctions. The most effective junctions are J6, J7, and J8, which are connected to the memory. Using recursive simulation, we investigated the effect of modifying the critical currents to obtain their favorable margins and reach the optimal values. Moreover, the critical current of the junctions must be optimized whereas the circuit is stable in both cycles. Another essential consideration is the current source values, which have an important role in biasing the junctions and the operation of the circuit. The junctions are biased at the optimal points in different states. Inquiring the effects of modifying the values of the current sources on the output response in the negative half cycles, we observed that the circuit is most sensitive to the values of some of the critical current sources such as I 2 and I 3. The width of the applied SFQ pulse, needed to switch the junctions, also has been studied. Considering the stored single flux quanta, Φ 0, in the loop and the performance of the cell, SFQ input pulses have flux entity of slightly less than a Φ 0. The proper functionality of the circuit is also observed to be most sensitive to the energy of the pulses with critical margin of 5 7% below a Φ 0. In our design, we also have investigated the influence of the parasitic inductances caused by the fabrication process of the RSFQ circuits by means of simulation. We have observed that parallel possible parasitic inductances with a junction have almost no effect on the performance of the circuits. Although, series parasitic inductances to a Josephson junction significantly reduce the performance as well as the response speed of the circuits whereas also increase the latency of the readout part [17]. We have optimized the circuits for proper operation and minimizing the fluctuations in output pulses with the consideration of the series parasitic inductances. The value of these parasitic inductances are related to the fabrication technology that we considered them to be about ph. As well known, for the communication between the RSFQ circuits, the circuits also require the input and output JTLs, which can decrease the fluctuations of the output signals whereas also reducing the loading effect of the connected gates leading to further stability. Including the parasitic inductances and junction parameters in our simulations for the considered technology mentioned earlier, Fig. 5 shows the final results of the proposed bi-directional NDRO cell. The results are obtained using the Josephson circuit simulator for a sample sequence of input pulses, illustrating the proper operation of the cell. V. C ONCLUSION AND SUMMARY We have focused on the proper operation of a bi-directional RSFQ TFF, an introduced bi-directional non-destructive readout (NDRO) cell, and the readout process of the cells. A readout circuit is an inevitable lateral circuit for the state readout of Fig. 5. Final results of the designed bidirectional NDRO cell. the RSFQ circuits having an internal memory loop. We have designed and proposed a bi-directional NDRO cell based on T Flip Flop. In this design, the cell can store a bit in the positive and negative half cycles. The readout part of this circuit can read the state of the memory without destroying it, and produce the SFQ pulse corresponding to the possible state of the stored bit in the loop. The bi-directional non-destructive readout cell is investigated and optimized leading to more stable operation. We have successfully studied the effects of the readout cell topology and critical parameters on the proper functionality and stability of the internal states of the bi-directional NDRO circuit based on the T Flip-Flop. We have also investigated the cell behavior in the negative half cycles considering the correct operation in the readout part. Afterwards we designed and optimized the bi-directional NDRO cell by using the obtained optimal parameters for the further stability in the response and minimizing the fluctuations in the output SFQ pulses, leading to optimal performance. Finally, we presented an improved version of a bi-directional NDRO circuit, using a combination of RSFQ blocks consisting of JTL, AND gate, memory (TFF), and readout part, where for reading the memory in the negative half cycles, we used a DFF next to the AND gate. This configuration promises the correct timing of applying the readout input pulse to the main TFF circuit in the positive half cycles. REFERENCES [1] K. Gaj, E. G. Friedman, and M. J. Feldman, Timing of multi-gigahertz rapid single flux quantum digital circuits, J. VLSI Signal Process., vol. 16, no. 2, pp , [2] D. K. Brock, RSFQ technology: Circuits and systems, Int. J. High Speed Electron. Syst., vol. 11, no. 1, pp , [3] O. A. Mukhanov, S. Sarwana, D. Gupta, A. F. Kirichenko, and S. V. Rylov, Rapid single flux quantum technology for SQUID applications, Physica C, Supercond., vol. 368, no. 1, pp , Mar [4] W. Chen, A. V. Rylyakov, V. Patel, J. E. Lukens, and K. K. Likharev, Rapid single flux quantum T-flip flop operating up to 770 GHz, IEEE Trans. Appl. Supercond., vol. 9, no. 2, pp , Jun [5] K. K. Likharev, O. A. Mukhanov, and V. K. Semenov, Resistive single flux quantum logic for the josephson-junction digital technology, in Proc. SQUID, 1985, pp

5 JABBARI et al.: FUNCTIONALITY AND STABILITY OF BI-DIRECTIONAL RSFQ TFF [6] K. K. Likharev and V. K. Semenov, RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems, IEEE Trans. Appl. Supercond., vol. 1, no. 1, pp. 3 28, Mar [7] T. Van Duzer et al., Engineering issues in high-frequency RSFQ circuits, Physica C, Supercond., vol. 372, no. 1, pp. 1 6, Aug [8] T. Van Duzer and C. W. Turner, Principles of Superconductive Devices and Circuits, 2nd ed. Englewood Cliffs, NJ, USA: Prentice-Hall, [9] T. Ortlepp et al., RSFQ Circuitry Using Intrinsic π-phase Shifts, IEEE Trans. Appl. Supercond., vol. 17, no. 2, pp , Jun [10] J.Y. Kim,S. H.Baek, and J. H.Kang, Construction of a single magnetic flux quantum switch and its usage in an arithmetic logic unit, J. Korean Phys. Soc., vol. 43, no. 6, pp , [11] T. Reich, T. Ortlepp, and F. Hermann Uhlmann, Digital SQUID sensor based on SFQ technique, IEEE Trans. Appl. Supercond., vol. 15, no. 2, pp , Jun [12] F. Foroughi, A. Bozbey, and M. Fardmanesh, Design and Optimization of fully digital SQUID based on bi-directional RSFQ, J. Supercond. Novel Magn., vol. 27, no. 7, pp , [13] F. Foroughi, Design and Optimization of Fully Digital SQUID Based on Bi-Directional RSFQ. Tehran, Iran: Sharif Univ. Technol., [14] T. Jabbari, H. Zandi, F. Foroughi, and M. Fardmanesh, Stability Investigation in RSFQ NDRO CEll, Proc. IEEE 23rd Iranian Conf. Elect. Eng., 2015, pp [15] T. Jabbari, Design and Optimization of T1 Flip Flop in Bi-directional RSFQ Logic. Tehran, Iran: Sharif Univ. Technol., [16] RSFQ-Cell Library, Dept. Phys., Stony Brook Univ. New York, New York, NY, USA, [Online]. Available: sunysb.edu/physics/rsfq/lib/contents.html [17] M. Maezawa, Numerical study of the effect of parasitic inductance on RSFQ circuits, IEICE Trans. Electron., vol. 84, no. 1, pp , 2001.

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