1 Send Orders of Reprints t 244 Recent Ptents on Electricl & Electronic Engineering 2012, 5, DP4T RF CMOS Switch: A Better Option to Replce the SPDT Switch nd DPDT Switch Virnjy M. Srivstv 1, *, Klyn S. Ydv 2 nd Ghnshym Singh 1 1 Deprtment of Electronics nd Communiction Engineering, Jypee University of Informtion Technology, Soln , Indi; 2 VLSI Design Group, Centrl Electronics Engineering Reserch Institute (CEERI), Pilni , Indi Received: August 7, 2012; Revised: Septemer 22, 2012; Accepted: Octoer 1, 2012 Astrct: In this pper we hve explored the design of doule-pole four-throw (DP4T) RF CMOS switch t 45-nm technology nd nlyzed the etter drin current nd switching speed s compred to the existing single-pole doule-throw (SPDT) switch nd doule-pole doule-throw (DPDT) switch. For the proposed DP4T RF CMOS switch results the pek output currents round ma nd switching speed of 36 ps. We re using the CMOS inverter propertied to some extent to design this DP4T switch. This rticle dels with the evolution of RF switches nd its design through reviewing ville ptents nd introduces the ltest pplictions of proposed switch. Keywords: DP4T switch, RF CMOS switch, single-gte MOSEFT, VLSI. 1. INTRODUCTION The trditionl DP4T switch uses MOSFET s cell in its min design, nd requires high control voltge upto 5.0 V nd lrge resistnce t the receivers nd ntenns to detect the signl. Becuse of its high vlue of control voltge, it is not suitle for modern portle devices which demnd smller power consumption. Therefore, we proposed DP4T switch y using RF CMOS technology nd nlyzed its performnce. A semiconductor device includes switch circuit selecting signl pthwy etween common terminl nd one of plurlity of terminls using plurlity of FETs provided in series etween the common terminl nd ech of the terminls . A dimmer switch couplele to circuit including power source, lod, nd single-pole doule-throw three-wy switch tht comprises first nd second fixed contct nd movle contct . The wireless communictions circuitry my hve ntenn diversity circuitry tht llows n optimum ntenn or optimum ntenns in n ntenn structure to e switched into use during device opertions . The ntenn structure my e shred etween multiple rdio-frequency trnsceivers in rdio-frequency trnsceiver circuit. The rdio-frequency trnsceiver circuit my e coupled to the ntenn structure using switching nd filtering circuitry. The proposed design cn y used to connect these ntenns. A three-pole three-throw (3P3T) switch nd communiction device employing the three-pole three-throw switch include six diodes nd six inductors . The three poles nd the three throws receive control signls vi the six inductors, respectively. A three-wy or four-wy switching circuit for lighting, nd the like, is descried [5, 6]. One three-wy *Address correspondence to this uthor t the Deprtment of Electronics nd Communiction Engineering, Jypee University of Informtion Technology, Soln , Indi; Tel: ; Fx: ; E-mil: switch is replced with n electronic switch. Both legs of the switching circuit re powered ll the time nd current is sensed in the legs to determine when one of the three-wy or four-wy switches hs een switched. Further, min ojective is to provide plurlity of such switches rrnged in densely configured switch rry. Here new RF DP4T with inverter properties CMOS switch circuit is proposed, where the power nd re could e reduced s compred to lredy existing switch configurtion s SPDT nd DPDT trnsceiver switches, which is simply reduction of signl strength during trnsmission of the RF [7-9]. The proposed DP4T RF CMOS switch exhiits etter drin current nd switching speed compred to existing SPDT nd DPDT switch [10, 11]. The insertion loss nd power hndling cpility of the switch is lso found improved y using higher control voltge of 1.2 V. The proposed switch is suitle for short rnge wireless communictions where power hndling requirements re comprtively smll. Bsed on the simultion results, it is demonstrted tht drin currents increses in wy from SPDT to DPDT, nd DPDT to DP4T switch structures. A etter reduction of the short chnnel effects nd improvement of the device reliility could lso e expected y chnging the chnnel width to length rtio, gte mterils nd optimizing these prmeters. The enhncement in frequency response of Si-CMOS devices hs motivted for their use in the millimeter nd rdio-frequencies wve pplictions, such s high cpcity wireless in locl re network, short-rnge high dt-rte, wireless personl re network, nd collision voidnce rdr for utomoiles. Using Si-CMOS for these pplictions llows for higher levels of integrtion nd lower cost lso improving the efficiency. Since for the 65-nm technology hs ppliction of 60 GHz power mplifier designs, ut recently reported reserch  hs demonstrted 60 GHz power mplifiers in 45-nm technology. The CMOS wide /12 $ Benthm Science Pulishers
2 DP4T RF CMOS Switch Recent Ptents on Electricl & Electronic Engineering, 2012, Vol. 5, No nd switches re designed primrily to meet the requirements of devices trnsmitting t ISM (industril, scientific, nd medicl) nd frequencies (900 MHz nd up). The low insertion loss, high isoltion etween ports, low distortion, nd low current consumption of these devices mke them n excellent solution for mny high frequency pplictions tht require low power consumption. 2. DESIGN OF DOUBLE-POLE FOUR THROW SWITCH The ojective of the proposed design of switch is to operte t 2.4 GHz nd 5.0 GHz for MIMO systems. This switch mitigtes the ttenution of pssing signls nd exhiit high isoltion to void interruption of simultneously received signls . Figure 1 shows the proposed DP4T RF CMOS inverter switch. It contins two trnsistors which re used for first ntenn, the working process t time ny one of trnsistor M 1 or M 3 will operte nd in the sme fshion ny one of trnsistor M 2 or M 4 will operte. Sme working function is oserved in the proposed DP4T CMOS switch s in Fig. (2). A DP4T RF CMOS switch hs the properties s fixed tuned mtching networks, low qulity fctor, mtching networks, high power output, mounting flnge pckges, power gin or power mplifiction, (rtio of output power to input power), noise-figure or mount of noise dded during norml opertion (rtio of the signl-to-noise rtio t the input nd the signl-to-noise rtio t the output), high power dissiption (totl power consumption). Some ipolr RF CMOS trnsistors re suitle for utomotive, commercil or generl industril pplictions [14, 15]. The choice of RF CMOS switches requires n nlysis of the performnce prmeters s mximum drin sturtion current, operting frequency, cut-off frequency, threshold voltge of n-mosfet nd p- MOSFET, control voltge, output power nd forwrd trnsconductnce [16-18]. Also controls the increse or decrese of chnnels for devices which opertes in depletion region. Fig. (1). Schemtic of the proposed DP4T SG RF CMOS switch with ) inverter property  nd ) two trnsistors.
3 246 Recent Ptents on Electricl & Electronic Engineering, 2012, Vol. 5, No. 3 Srivstv et l. Since DP4T switch is fundmentl switch for multipleinput, multiple-output dt trnsfer pplictions ecuse prllel dt strems cn e trnsmitted or received simultneously using the multiple ntenns, we tke two ntenns nd four ports s shown in Fig. (1), the trnsmitted signl from power mplifier is sent to trnsmitter A_Tx port nd trvel to the ANT 1 node while the received signl will trvel from the ANT 2 node to the receiver B_Rx port nd pss on to the low noise mplifier or ny other ppliction s required for trnsceiver systems. The proposed switch contins CMOS in its rchitecture nd needs only two control lines (V 1, V 2 ) of 1.2 V to control the signl congestion etween two ntenns nd four ports s shown in Fig. (1). Therefore it improves the port isoltion performnce two times s compred to the DPDT switch nd reducing signl distortion. Since connecting n n-chnnel MOSFET in prllel with p-type MOSFET llows signls to pss in either direction. Whether the n-type or the p-type device crries more signl current depends on the rtio of input to output voltge. Becuse the switch hs no preferred direction for current flow, so no preferred input or output. 3. WORKING ANALYSIS OF DOUBLE-POLE FOUR THROW SWITCH When low voltge is pplied t the input, the upper p- type trnsistor is conducting (nd switch closed) while the lower n-type trnsistor ehves like n open circuit. Therefore, the supply voltge (5 V) ppers t the output. Conversely, when high voltge is pplied t the input, the n- type trnsistor is conducting (nd switch closed) while the upper p-type trnsistor ehves like n open circuit. Hence, the output voltge is low (0 V). Alwys one of the trnsistors will e n open circuit nd no current flows from the supply voltge to ground. The voltge trnsfer chrcteristic (VTC) gives the response of the DP4T inverter switch circuit with the ntenns (ANT 1 nd ANT 2 ) with the specific input voltges V 1 nd V 2 [19-21]. The gte to source voltge V gs of the n-type MOS- FET is equl to V in, while the gte to source voltge of the p- type MOSFET clcultes s V p gs = V in -V dd nd the drin to source voltge of the p-type MOSFET cn e expressed s V dsp = V n ds - V dd. From the output chrcteristics of the two trnsistors s shown in Fig. (2), we cn conclude tht the resulting drin currents in the circuit is equl for ech V in c Fig. (2). ) Proposed DP4T switch lyout with two trnsistors nd ) & c) re its voltge trnsfer chrcteristics.
4 DP4T RF CMOS Switch Recent Ptents on Electricl & Electronic Engineering, 2012, Vol. 5, No Fig. (3). ) Output ntenn voltge with the input voltges, nd ) drin current nd output voltge. nd the drin currents I d of oth trnsistors re equl. From this lyout of DP4T CMOS switch we lso extrct the voltge trnsfer chrcteristics. So, it is ovious tht when p-type MOSEFT is ON, then ANT 1 nd ANT 2 re connected to the A_T x nd B_T x respectively, which re shown here with the 5 V or V DD. Similrly when the n-type MOSEFT is ON, then ANT 1 nd ANT 2 re connected to the A_R x nd B_R x respectively which is shown here with the zero or ground voltge s shown in the Fig. (2) nd Fig. (2c) for the ntenn-1 nd ntenn-2 respectively. 4. CURRENT & FUTURE DEVELOPMENTS From the nlysis of the Fig. (3), for the proposed DP4T RF CMOS switch results the pek output currents round ma s summrized in the Tle 1, nd switching speed of 36 ps. Hence we cn replce the SPDT switch nd DPDT switch with the proposed DP4T RF CMOS switch . To reduce the short chnnel effects of nnoscle devices, the proposed DP4T RF CMOS switch cn e designed y using the doule-gte MOSFET process.
5 248 Recent Ptents on Electricl & Electronic Engineering, 2012, Vol. 5, No. 3 Srivstv et l. Tle 1. Simultion Results for Drin Currents Structures SPDT DPDT DP4T Drin Current ma ma ma CONFLICT OF INTEREST The uthors confirm tht this rticle content hs no conflicts of interest. ACKNOWLEDGEMENTS The uthor wnts to thnk Prof. A.B. Bhttchhry, Jypee University, Noid, Indi nd Mr. Peeyush Tripthi, IBM, Bnglore, Indi for mny insightful discussions. The uthor lso wnts to thnk Prof. Anshumn Shrm, Deprtment of Interntionl Business Administrtion, College of Applied Science, IBRI, Ministry of Higher Eduction, Sultnte of Omn for support from their site. REFERENCES  Y. Ymd, Semiconductor device nd method for testing sme, U.S. Ptent , My 4,  S.E. Detmer, J.M. Kegy, J.J. Steffie, Lighting control device for use with lighting circuits hving three-wy switches, U.S. Ptent 82,12,425, July 2,  N.W. Lum, L.J. Snguinetti, Shred multind ntenns nd ntenn diversity circuitry for electronic devices, U.S. Ptent 82,08,867, June 26,  A.N. Song, X.Y. Liu, S.Q. Li, Three-pole three-throw switch nd communiction device, U.S. Ptent 01,19,818, My 17,  G.T. Grice, Three-wy nd four-wy switching circuit, U.S. Ptent 03,16,350, Septemer 20,  G.V. Klimovitch et l. Switching methods nd pprtus, U.S. Ptent 02,91,736, August 9,  T. Dinc, S. Zihir, Y. Guruz, CMOS SPDT T/R switch for X- nd, on-chip rdr pplictions, Electronics Letters, vol. 46, no. 20, pp ,  M. Uzunkol nd G. M. Reeiz, A low loss GHz SPDT switch in 90 nm CMOS, IEEE J. of Solid Stte Circuits, vol. 45, no. 10, pp , Oct  Chien Cheng Wei, Hsien Chin Chiu, Sho Wei Lin, Ting Huei Chen, Jeffrey S. Fu nd Feng Tso Chien, A comprison study of CMOS T/R switches using gte/source terminted field plte trnsistors, Microelectronic Engineering, vol. 87, no. 2, pp , Fe  E. J. Nowk, Turning silicon on its edge, IEEE Circuits Devices Mg., Vol.20, No.1, Jn. 2004, pp  S. H. Lee, C. S. Kim nd H. K. Yu, A smll signl RF model nd its prmeter extrction for Sustrte Effects in RF MOSFETs, IEEE Trns. on Electron Devices, vol. 48, no. 7, pp , July  V. M. Srivstv, K. S. Ydv nd G. Singh, Anlysis of doulegte CMOS for doule-pole four-throw RF switch design t 45-nm technology, J. of Computtionl Electronics, vol. 10, no. 1-2, pp , June  U. Gogineni nd J. Almo, Effect of sustrte contct shpe nd plcement on RF chrcteristics of 45 nm low-power CMOS devices, Proc. of Rdio Frequency Integrted Circuits Symp., USA, June 7-9, 2009, pp  P. Meknnd nd D. Eungdmorng, DP4T CMOS switch in trnsciever of MIMO system, Proc. of 11th IEEE Int. Conf. of Advnced Communiction Technology, Kore, 2009, pp  V. M. Srivstv, K. S. Ydv nd G. Singh, Optimiztion of drin current nd voltge chrcteristics for the DP4T doule-gte RF CMOS switch t 45-nm technology, Procedi Engineering, vol. 38, pp , April  F. J. Hung nd O. Kenneth, A 0.5 m CMOS T/R switch for 900 MHz wireless pplictions, IEEE J. of Solid Stte Circuits, vol. 36, no. 3, pp , Mrch  K. Miytuji nd D. Ued, A GAs high power RF single-pole dul-throw switch IC for digitl moile communiction system, IEEE J. of Solid Stte Circuits, vol. 30, no. 9, pp , Sept  L. Qing nd Y. P. Zhng, CMOS T/R switch design: towrds ultr widend nd higher frequency, IEEE J. of Solid Stte Circuits, vol. 42, no. 3, pp , Mrch  V. M. Srivstv, K. S. Ydv nd G. Singh, Cpcitive model nd S-prmeters of doule-pole four-throw doule-gte RF CMOS switch, Int. J. of Wireless Engineering nd Technology, vol. 2, no. 1, pp , Jn  A. Poh nd Z. Ping, Design nd nlysis of trnsmit/receive switch in triple-well CMOS for MIMO wireless systems, IEEE Trns. on Microwve Theory nd Techniques, vol. 55, no. 3, pp , Mrch  V. M. Srivstv, K. S. Ydv nd G. Singh, Anlysis of drin current nd switching speed for SPDT switch nd DPDT switch with the proposed DP4T RF CMOS switch, J. of Circuits, Systems nd Computers, vol. 21, no. 4, pp. 1-18, June 2012.