Low noise SQUID simulator with large dynamic range of up to eight flux quanta

Transcription

1 Low noise SQUID simultor with lrge dynmic rnge of up to eight flux qunt A. Mrtinez*, J. Flokstr, C. Rillo**, L.A. Angurel**, L.M. Grci** nd H.J.M. ter Brke Twente University of Technology, Deprtment of Applied Physics, PO Box 217, 7500 AE Enschede, The Netherlnds **ICMA nd Fcultd e Ciencis, University of Zrgoz, Zrgoz, Spin Received 17 July 1989; revised 3 November 1989 A 19 chnnel d.c. SQUID mgnetometer for biomgnetic reserch is under construction. The system needs compctly built control nd detection electronics nd to fcilitte the test n electronic circuit simulting the typicl periodic chrcteristics of SQUID ws developed. In totl nine steps of tringulr shpe were implemented with step voltge reference genertor nd precision full-wve rectifier. The trnsfer function of the SQUID electronics nd the mximum slew rte of the system could be esily mesured. Keywords: SQUIDs; instrumenttion; SQUID electronics Multichnnel SQUID mgnetometry requires compctly built premplifiers nd control nd detection electronics. The uthors re constructing 19 chnnel d.c. SQUID mgnetometer for brin reserch, nd vrious schemes for the electronic processing hve been designed. To fcilitte functionl test nd djustment of the modules of the SQUID electronics, SQUID simultor with dynmic rnge of up to eight flux qunt hs been designed. Severl interesting dvntges hve been obtined. There is no need for cryogenic infrstructure nd there is no risk of destroying the sensor. Furthermore, the electronic system cn be simply extended to multichnnel version so tht 19 SQUIDs with equl qulity fctors cn be simulted. Typicl trnsfer problems in multichnnel systems such s cross-tlk between trnsmission lines cn be esily studied, It is cler tht specific properties due to the SQUID configurtion, such s resonnces cused by the coupling between the SQUID loop nd plnr coupling coil, cnnot be simulted. Also, the 1If noise cnnot be considered. Despite these two shortcomings, the SQUID simultor is powerful instrument in multichnnel SQUID instrumenttion. In severl ppers 1'2 electronic circuits hve been described tht represent the functionl behviour of Josephson junctions nd SQUIDs. The vrious terms in the non-liner differentil equtions re simulted by electronic networks, mking it possible to study the effect of ll relevnt prmeters. This leds to rther complicted designs. For testing the SQUID red-out electronics such n overll pproch is not necessry becuse only the flux-voltge trnsfer hs to be simulted nd much simpler circuits re dequte. In this pper n electronic circuit is described which *On leve from ETSI Industriles, University of Zrgoz, Zrgoz, Spin implements nine steps of the typicl periodic chrcteristic of SQUID. Although the implementtion involves the tringulr flux-voltge response of RF SQUID system, there is no reduction in vlidity when d.c. SQUID electronics re tested with the simultor. The use of one-step SQUID simultor hs been reported by Rillo et l. 3. The trnsfer function of the SQUID is replced by V shpe voltge-flux curve, simulted with precision full-wve rectifier (PFWR). However, the rel trnsfer function is periodic with respect to the flux nd the use of multiplexed series of PFWRs ws suggested to obtin this behviour. In the present design only one PFWR is used for the genertion of ll steps, leding to reduction in the necessry components. Furthermore, the forwrd trnsfer rtio does not chnge from step to step. The nine periods were relized with reference voltge step genertor. The forwrd trnsfer rtio, S, coupling between modultion coil nd SQUID, Mr, nd dynmic resistnce of the SQUID, Rd, re ll relevnt quntities in d.c. SQUID feedbck loop opertion. Typicl vlues re: S = 100 #V/Oo, Mf ~o/a nd R d = 4f~. These vlues hve been implemented in the simultor. The multi-step simultor enbles the study of the mximum slew rte of the system. An input signl of known frequency nd incresing mplitude is used to provoke the unlock. This will result in monotonous increment of the flux error signl up to 0 /4, corresponding to the mximum limit for the locked opertion. This sitution is internlly detected by the simultor nd ppropritely signlled with LED lmp. By exceeding the slew rte limit the system unlocks nd new lock t nother step my be obtined. The content of this pper is s follows. First, the different prts of the circuit re described nd it is shown how the min prmeters S, Mf nd R d hve been relized. Second, /90/ Butterworth & Co (Publishers) Ltd 324 Cryogenics 1990 Vol 30 April

2 severl tests of the simultor re reported. Then, in the lst prt of the pper, some conclusions will be drwn. Circuit description A schemtic digrm of d.c. SQUID configurtion is presented in Figure 1, showing the input nd feedbck coils nd the min electricl prmeters involved. The input coil drives current, Ii, nd is coupled to the SQUID by M i. The corresponding quntities for the feedbck coil re If nd Mr, respectively, lb represents the bis current nd Vo the output voltge of the sensor. An equivlent block scheme of the d.c. SQUID nd the typicl trnsfer function re given in Figures 2 nd b, respectively. The fluxes induced by the input nd feedbck currents re ~i(s =j~o) nd ~t(s), respectively. Co(s) is the resulting coupled flux. The voltge-flux chrcteristic is obtined in n open loop. [ Vo b Low noise SQUID simultor: A Mrtinez et l. + F re(s) Zf(s) G3(s) Vo(S) )-, I Figure 1 D.c. SQUID consisting of two Josephson junctions in superconducting loop of inductnce L. Currents / i nd If through input coil nd feedbck coil, respectively, couple mgnetic flux into SQUID vi mutul inductnces M i nd Mr, respectively. / b is the bis current nd V o the output voltge modulted by the flux b Vo r + Cf(S) P Zf Is) I I i.~ I 2 3 e/ o Vo(S) Figure2 () Equivlent block scheme of the d.c. SQUIO in Figure I. Fl(s =jo)), F2(s ) nd F3(s ) re trnsfer functions. (b) V o for constnt bis current, d) o is flux quntum I z 3 e/ o Figure 3 () Scheme equivlent to tht of Figure 2 with n internl representtion of flux s voltge. (b) Approximtion of sinusoidl shpe of Figure 2b with V shpe pttern The inputs of the simultor re currents nd the output is voltge (Figure 3) s holds for the d.c. SQUID. The trnsfer function of the d.c. SQUID is pproximted by the tringulr pttern of Figure 3b, which cn be esily relized without disrupting the operting principle. Using the pproprite vlues for Mr, S nd R d in the design, s mentioned previously, the simultor cn be directly coupled to the d.c. SQUID control electronics without ny other interfce. As is seen from Figures 2 nd 3, the flux coupled to the SQUID is represented by voltge. It would be necessry to use two current-to-voltge converters nd one voltge dder in the simultor to obtin the error signl, V~(s). However, if Mj is tken to be equl to Mf (which cn be done without loss of vlidity), only one current-to-voltge converter is necessry, with the dding point relized t its input. This simplifiction is used in the following considertions. A schemtic block digrm of the simultor, consisting of five blocks, is shown in Figure 4. Block (1) is stndrd current-to-voltge converter built with n opertionl mplifier (OP mp) nd feedbck resistor. The current, Ip, ppers in ddition to Ii nd If nd is used s preset current. The preset current determines one prticulr point of the trnsfer function when no other signls re present t the input. The order of mgnitude of the currents follows from the coupling fctor Mf = 10 5 (I)o/A; thus, is generted by current of 10 #A. All currents re dded t the negtive input of the OP mp. Due to intrinsic limits of the components used, the uncertinty in offset voltges will be of the order of 3 mv, nd in order to obtin n ccurcy within 1 ~o in the internl voltge repesenttion of the flux quntum, o, minimum trnsfer of 300 mv/ o is necessry. Here, trnsfer of 330 mv/~o ws chosen, leding to feedbck resistor of 33 kf~.

3 Low noise SQUID simultor: A Mrtinez et l. st e{o SWI i R l i ~ I[-~EI~ ~ ~ ~Attenuofor ~ 7.5{ o Figure 4 Modules of the simultor: (1), current-to-voltge converter; (2) genertes discrete vlues of voltge references E2; (3) bsolute vlue circuit with differentil input; (4) ttenutor to dpt internl nd externl levels of signl; (5) logic circuit to disply step in opertion nd slew rte occurrence 7{o 6.5~ o 6 ~o A low noise type (OP27) OP mp ws selected which enbled work to be crried out with modultion frequency of 100kHz with squre wve. A smll compenstion cpcitor, empiriclly selected, should be plced in prllel with the feedbck resistor to obtin n dequtely shped wve form. Block (2) is genertor of voltge reference E 2, hving discrete vlues of the form E2 = n 330 mv, thus representing flux vlues of n@o. Implementtion involves nine step simultor, so tht n = 0, The vlue of E2 holds for the intervl E1 = (n 330 _ 165) mv nd thus for the flux intervl no -t- (noo/2). The ctul vlue of n is the step in which the simultor is working. The lyout of the step voltge genertor nd the output chrcteristic re given in Figures 5 nd b. An rry of resistors of equl vlue, R, fed by current source of vlue I, provides the series of reference voltges equivlent to 80 o, 7.5@o, o, 0. The nlog switches, SW1 nd SW2, controlled by the voltge comprtors, VCi, select one of the integer vlues. The swpping occurs when E 1 exceeds vlue equivlent to (n + 1/2)O o. The ccurcy of the representtion of one 0 is determined by: 1, the precision of the resistors, R; 2, the rtio Voff/RI, where Vof is the offset voltge of one voltge comprtor; nd 3, (E/b)//, where i b is the bis current of one voltge comprtor. Ech bis current flows from the current source to the voltge comprtor cross the resistors, R. Consequently, becuse of ib there is mismtch in the voltge drop between two consecutive resistors of Rib (mximum). For the two resistors t both ends of the rry this difference will be ZibR in the worst cse. Assuming n ccurcy of 1% for 0o, the resistors should t lest hve precision of 1%. Furthermore, point 3 will determine I, nd points 2 nd 3 will determine R. Tking typicl vlues from the CPM-02 voltge comprtor, the following vlues result: R = 2.2 Q, I = 75 ma. Block (3) is n bsolute vlue circuit (AVC) with differentil input. The output of this block is given by kle1 - E21, k being constnt. If one of the inputs is 0, the behviour of this block is tht of full-wve rectifier. With E1 from block (1) nd E2 from block (2), the nine steps re generted. Intrinsic limittions of the rte of chnge between two consecutive levels of E 2 nd delys due to the chnge of stte of the AVC restrict the speed of chnge of E1 to vlues of ~ 1800 steps per second. In cses of higher speed, the V shpe pttern becomes disconnected. However, when the simultor opertes in closed loop I~o 0.5 ~o b 8{o ' 7 t o 6} 0 5 {o 2~o ' // ' ' ', e, 0.5~o 1.5~o 2.5~o 5.5~o 6.5~o 7.5½0 Figure 5 () Circuit tht genertes discrete voltge references E 2. Output voltge E 2 is determined by the ctivted voltge comprtor with the highest number in the figure. (b) Chrcteristic obtined from the circuit in Figure 5 only one step is involved nd the limittions concerning Ez re not relevnt. There re severl schemes for PFWRs. The best performnce is obtined with the power supply current sensing technique, where the sensing is relized with current mirror 4'5. In this cse the frequency behviour is optiml nd the distortion for low level signls is smll. In Figure 6 the scheme for the AVC is presented. Two mtched low noise OP mps (OP1 nd OP2 re OP 227 type) re used for obtining the chrcteristics of PFWR,

4 Low noise SQUID simultor: A Mrtinez et l. o +v c~ R4[ PI +V VC8 9 to 4 priority encoder 4 / 4 to I0 BCD to 7 segment decoder code converter El o~ o, m 05 ~ z J, =ID C2 ~ Z / - ~ V ~ LED Figure 6 Scheme of bsolute vlue circuit. Current sink, I= IE -- E 11/R 3. It is sensed by the current mirror rrngement of T1, T2, T3 nd T4 with current rtio 0.5. If E 2 = E 1, current t collector of T3 is compensted with current source supplied by T5. Attenutor dpts the levels of internl nd externl signls. Current through R s defines S = 100/4V/~o. R 9 + R 10 determines R d = 4 fl. Attenutor hs lod of ~, 1 1 for the AVC Slew- rte Slew- rote step 4 step 5 Slew- rote step 6 Figure 7 Logic circuit to disply number of ctivted step nd to signl tht flux error of the SQUID being simulted is lrger thn (I)o/4. This is indicted by the slew rte LEDs. VC 1... VC s re outputs of voltge genertors of Figure 5 being in principle present in the current I. This current is sensed by the current mirror rrngement of the trnsistors T1, T2, T3 nd T4, leding to the mirror current of 1/2. The ccurcy for the current trnsfer rtio with four mtched trnsistors is within 1%6,7. When E~ = E2, there my still be smll current, I, due to the bis of the internl circuits of the two OP mps. However, the effect of this current is compensted with the current source provided by T5. The cse E 1 < E 2 results in current flow through the pth A-B-C-M-D, wheres E~ > E z leds to the pth E~C-B-L-D. In both cses, the current t the output is given by 0.51E~-Ezl/R 3. The vlue for R3 is tken s 16.5 f~ in order to obtin sensed current t the input of the current mirror of 20 ma/@o. This vlue is dequte for obtining n lmost non-rounded V shpe. Block (4) is n ttenutor (Figure 6). It determines the two importnt prmeters, the forwrd trnsfer rtio, S, nd the dynmic resistnce, R. It is in fct network of resistors which divides the current by fctor of 100 (R 7 --'- 1 Q, R s = 98 Q, R ~). The voltge drop t R 9 is 100/=V/@o, being the ssumed forwrd trnsfer rtio. The output resistnce is determined by R 9 -I- Rio, nd to obtin R = 411 the vlue of Rzo hs to be tken s equl to 3 f~. The ttenutor is very smll lod for the AVC, producing mximum voltge drop of 5 mv. This smll swing of voltge results in idel current source behviour of T3 nd T5, with only smll distortion. Block (5) is circuit to disply the step number in which the system is ctully operting. It is lso used to mesure the vlue of the slew rte of the input signl necessry to unlock the system when it is working in dosed loop. The steps re identified from the discrete levels of E2, nd thus from the stte of the voltge comprtors. To signl the step number properly, the stte of the eight comprtors is codified into seven segment disply. This is relized with nine to four priority encoder nd BCD to seven segment code converter (Figure 7). To mesure the slew rte, the simultor is connected to the control electronics in closed loop. The 100 khz modultion signl is set to +0.25(1)o. A sinusoidl input signl is pplied nd its slew rte is incresed slowly (this cn be done by fixing the frequency nd incresing the mplitude). Correspondingly, the error signl V~(s) in Figure 2 will increse nd El will go beyond the set rnge, leding to switch of E2. This unlocking of the system is detected by the seven segment disply. There is, however, one compliction. Being ner to but still below the mximum vlue of the error signl, spikes from the environment my led to E1 momentrily exceeding the set rnge, directly followed by return to norml vlues. The voltge comprtor is fst enough to detect this nd thus it is signlled on the disply. This short disturbnce does not chnge E2 so the system is still locked. Therefore, chnge in the seven segment disply is not proof of mximum slew rte occurrence. An dditionl circuit ws designed tht discrimintes between the ctivtion of the voltge comprtors due to spikes nd due to the exceeding of the slew rte limit. In the first cse the ctivtion sequence of the voltge comprtors is VCi, VCi+ 1, VC~,nd in the second cse VCi, VCi+ 1, VCi, VCi-1, VC~. The criterion for the slew rte limit is tht the ltter sequence occurs within 0.1 ms. This time intervl is obtined with monostbles nd the occurrence is detected by LED. Prt of Figure 7 depicts the circuit. The number of the step codified in binry is decoded with four to ten decoder nd this is used to ctivte the monostbles, D i. Ech line drives two monostbles; one is sensitive to the rising edge nd the other to the flling edge. The monostbles connected to the output line i detect the incoming level, Ii, into step i nd the outgoing levels O~, from step i, respectively. To perform the desired function the LED is ctivted if, within the time intervl of the monostbles, sequences of the form O~*I~+t*l~_ 1 or Oi*I~_ 1"Ii 1 re detected. Tests on the circuit The following tests hve been performed on the simultor, while obtining input currents with voltge signls

5 Low noise SQUID simultor." A Mrtinez et l. through high vlue resistors: 1 Output chrcteristics of the simultor nd output from the genertor of voltge references obtined with low frequency input signl of 100 Hz. 2 Opertion of the simultor in configurtion equivlent to tht of SQUID electronics. A squre wve modultion of 100kHz nd mplitude is used. 3 Dynmic behviour for smll sinusoidl input signls (~<0.25eo). 4 Noise mesurements. 5 Slew rte experiments. /vvn *-4~ o I00 Hz D.c. SQUID simultor x I / I0 -~ 0.25(} ~ IOkHz Low pss IO0 khz I00 khz +- I OV filter Phse djusted Ech of these tests will now be considered in more detil For the first test, the system is internlly djusted with ip set to strt t step number 4. Then low frequency (100 Hz) tringulr wve of current equivlent to 4.5"o nd 100 Hz is pplied s the input. Figure 8 represents photogrph of the input signl (tringulr wve), the output from the genertor of voltge references (stir-step shpes) nd the nine output steps (V shpes). This lst signl hs been tken from the input of the ttenutor to give better disply. The second test ws performed using the scheme shown in Figure 9. The input signl is tringulr wve of 100 Hz nd mplitude 4"o. Additionlly, squre wve of 100 khz nd 0.25"o mplitude hs been pplied s modultion signl. "An mplifier with Av = 890 nd multiplier with scle fctor of 1/10 re used to detect the response of the simultor. The reference input of the multiplier is sinusoidl wve of _ 10 V nd f = 100 khz, djusted in phse. Using this rrngement the results in Figure 9b hve been obtined, these being the simulted results for SQUID in opertion. The forwrd trnsfer rtio, S, cn be clculted from Figure 9b s #V/~ o, which is close to the expected vlue. To mesure the smll signl response of the simultor for test 3, the scheme shown in Figure 9 ws used nd the tringulr wve ws replced by sinusoidl signl with n mplitude smller thn 0.25(I)o. Now the system Figure 8 Nine steps of simultor (V shpes) nd output from genertor of voltge references obtined with tringulr input signl of 100 Hz. Scle for V shpes: horizontl 0.5ps division -1, verticl 1 mv division -1. Scle for voltge references: 500 mv division -1. Input is unclibrted to fit into the screen. V shpes hve been tken from the input of ttenutor for better disply Figure 9 () Arrngement used to obtin Figure 9b. Input signl equivlent to +_4(1), is modulted with squre wve of +0.25(I) 0 nd frequency of 100kHz. (b) Nine steps of simultor obtined fter detection. Scle for tringulr wve with long period (input signl): horizontl unclibrted ~<0.5#s division -1, verticl 2 V division-1. Scle for output: 10 mv division -1 opertes in one step nd the frequency response cn be mesured. At the output of the premplifier not only is the bsic signl with frequency f mesured but lso hrmonics with frequencies 100 khz + f, 200 khz + f... due to the modultion frequency of 100 khz. To observe the output properly low pss filter of 20 khz nd 24 db/octve roll-off ws pplied, this being dequte to test the simultor in the frequency rnge up to 500 Hz. This rnge covers ll biomgnetic experiments plnned with the multichnnel d.c. SQUID system. The mesured frequency behviour ws completely determined by the 20 khz filter. Thus it is concluded tht the simultor hs fit frequency response in the rnge of biomgnetic experiments (up to 500 Hz). For the fourth test, n upper limit for the noise contribution of the simultor ws indirectly evluted. A monolithic premplifier ws used (gin= 1000) with equivlent noise prmeters t the input t 100 khz of E. = 1.8 nv/hz 1/2 nd I, = 1 pa/hz 1/2. No increse in the noise level ws observed fter connection of the simultor to the premplifier. Due to the low output resistnce of the simultor, the current noise contribution is negligible. Therefore the voltge noise of the simultor is below 1.8 nv/hz 1/. A second test ws mde using the simultor nd the premplifier with d.c. SQUID electronics in feedbck mode opertion. The trnsfer rtio of the system is 1 V/~ o nd with the forwrd trnsfer rtio of the simultor t 100 #V/~. it follows tht the rtio between the SQUID electronics output nd premplifier input is 104. Using this configurtion noise level of 18 #V/Hz 1/2 ws mesured t the output, nd it ws concluded tht the premplifier is the most noisy prt of the circuit.

6 Low noise SQUID simultor: A Mrtinez et l ,o:: _ ii::ii 5i O" -5 J i i i i i I I00 I000 I0000 Frequency ( Hz ) Figure 10 Reconstruction of open loop trnsfer function of system through slew rte mesurements chieved with simultor. - - Vlues clculted from oj c, to z nd cop_; R, vlues obtined from slew rte mesurements (the differences re of the order of 0.7 db) For the finl test, the slew rte limit of SQUID system is given by the mximum rte of chnge of input flux, doi/dt, tht cn be followed without interrupting the closed loop opertion. This mximum depends on the open loop trnsfer function of the SQUID electronics3. For system with one dominnt pole it holds tht do'ddtmx = to~ x 00/4, to~ being the (ngulr) frequency t the point where the open loop gin is 0 db. For system with two poles nd one zero the mximum is given by do~dtm x = (to~ x to,jto)00/4 for vlues to < to=, nd do.ddtm=x = toe x 00/4 for co > to~, where toz is the frequency of the zero signl nd to the frequency of the input signl The slew rte experiments were performed with d.c. SQUID control electronics of the second type. For this system, toc = 2;t x , the pole frequency, (.L)p = 2n x 400 nd to~ = 2n x The open loop gin, 20 log lg(jto) x H(jto)l, of this system is clculted with these vlues nd is depicted s continuous line in Figure 10. G(jr,) nd H(jog) re the frequency dependent trnsfer functions of the forwrd nd the feedbck pth of the loop. The im of the experiment is to reconstruct the open loop trnsfer function with the informtion obtined from the slew rte mesurements. It hs been shown 3 tht doi/dtm x = 0 i to nd toe x (.Oz/to 2 = I G(jto) x H(jto)l for vlues to<toz, nd toe/to= I G(jto) x H(jto)l for to >toz. So, it follows tht 201oglG(jto) x n(jto)l = 20 log(4 x.d o) for both cses. This is the formul used to obtin the open squres in Figure 10. Prior to the slew rte mesurements, the simultor nd the d.c. SQUID electronics hve been connected in closed loop nd the open loop gin hs been djusted to obtin the desired closed loop trnsfer function. For the frequency rnge top < to < toc the mesured vlues re within 0.7 db of the theoreticl ones. This gives level of error of ~ 8 % for the experimentl mesurement of slew rte using this procedure. Concluding remrks An electronic circuit ws developed tht simultes nine steps of SQUID. This simple instrument is extremely suited to testing nd djustment of multichnnel d.c. SQUID electronics. The work cn be performed in n electronics lbortory, s there is no need for cryogenic infrstructure. The min prmeters of d.c. SQUID, such s forwrd trnsfer rtio, feedbck coupling nd dynmic resistnce could be esily implemented nd modifictions of these vlues cn be simply relized. Thus the system cn be dpted to suit ech specific SQUID development. Acknowledgements A. Mrtinez is supported in prt by the Diputci6n Generl de Arg6n, Zrgoz, Spin. References 1 Henry, R.W. nd Prober, D.E. Rev Sci lnstrum (1981) Tuckermn, D.B. Rev Sci lnstrum (1978) Rillo, C., Veldhuis, D. nd FIokstr, J. IEEE Trns lnstrum Mes (1987) IM Toumzou, C. nd Lidgey, F.J. lee Proc G (1987) Toumzou, C. nd Lidgey, FJ. Electronics nd Wireless World(1987) Wilson, 13. Wireless Worm (1981) Lidgey, F.J. Wireless World (1979) 85 57