Experiment 3: NonIdeal Operational Amplifiers


 Roland Sanders
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1 Experiment 3: NonIdel Opertionl Amplifiers 9/11/06 Equivlent Circuits The bsic ssumptions for n idel opertionl mplifier re n infinite differentil gin ( d ), n infinite input resistnce (R i ), zero output resistnce (R o ), infinite bndwidth, zero output voltge ( o ) when nd  re equl or lterntively when d =   = 0, zero input bis currents, nd zero input offset voltge. Under these idel conditions, n opertionl mplifier (opmp) does not lod down its input nor does the lod ffect the output. Under these conditions the nlysis of the resulting electronic system is reduced to its simplest form. Although most opmps pproch these idel conditions, in number of pplictions it is importnt to understnd the limittions imposed by the rel behvior of opmps. Shown in Figure 1 re equivlent circuits for both idel opmp (upper circuit) nd more relistic mcromodel of n opmp (lower circuit). The mcromodel shows the dditionl components tht pproximte the nonidel behvior of rel opmps. In modern opmps, the differentil gin is typiclly 100 to 300 olts/m. The input resistnce (for smll differentil input voltges) cn rnge from few Meg ohms for bipolr input devices up to 10 Ter ohms for FET input devices (e.g. LMC6081). The output resistnce is typiclly 50 to 100 ohms Idel OpAmp 2 d d d o d = I d R i d d I 2 c c offset d =   c = (  )/2 R o Mcromodel of Rel OpAmp o Figure 1 Opertionl Amplifier Equivlent Circuits To ccount for n output voltge ( o ) when nd  re equl, common mode gin ( c ) nd common mode voltge, c = ( )/2, re introduced into the circuit. Two current 1
2 sources (I nd I) represent nonzero input bis currents nd bttery ( offset ) represents the nonzero dc offset voltge. An oftenused figure of merit for n opmp is the common mode rejection rtio (CMRR), defined s d CMRR = (1) CMRR t low frequencies is typiclly bout 90 db. Be wre tht the common mode rejection typiclly degrdes rpidly with incresing frequency, beginning t firly low frequencies. Another chrcteristic of rel opmps is limited frequency response nd slew rte. These two effects limit the high frequency response of the mplifiers, but in different wys. Almost ll opmps hve nerly flt gin up to some corner frequency. Above tht frequency the gin decreses t bout 6 db/octve (or 20 db/decde). This is the sme frequency response s simple RC low pss filter. When the input signl hs frequency higher thn this corner frequency, the output will still be sinusoidl, but the gin will reduced. In ddition there is seprte slew rte limittion. This is usully the result of cpcitor introduced in the design to stbilize the mplifier nd mke it esier to use. (Some very high speed mplifiers re vilble without compenstion, nd they cn be tricky to use prticulrly t low closed loop gin.) The result of this cpcitor is tht no mtter wht the input to the mplifier does, the output voltge will not chnge fster thn some limiting rte (volts/µsec). Another effect of this cpcitor cn be dely from input to output following lrge (sturting) input signls. This results when this cpcitor chrges to lrge voltge while the input is sturted, nd then hs to dischrge before the output cn resume trcking norml input. Differentil Gin c O CC SAT d =   Slope = d  SAT  CC Figure 2 Trnsfer chrcteristic of n opertionl mplifier Becuse the differentil gin of n opmp is so high, it is difficult to mesure ccurtely. Referring to Figure 2, it cn be seen tht the differentil input voltge ( d ) must be very smll to obtin opertion in the liner mplifiction region. Otherwise, the output will sturte t voltge ( SAT ) somewht less thn the power supply voltge ( CC ). Becuse of this, we will use unity gin inverter circuit (negtive feedbck) with voltge divider input s shown in Figure 3 below to mesure the differentil gin s function of frequency. 2
3 I R i R R f I f S R1 I i  R2 I i _ o Figure 3 Circuit for mesuring differentil gin If in the circuit of Figure 3, we set (R 1 R 2 ) much greter thn R i or R f nd R2 << R 1 so tht  is smll nd I i is negligible, then Rf 0 = S Ri (2) To obtin unity gin inverter we set R f equl to R i nd, so s long s d is very lrge, then Consider now the voltge divider ssuming I i 0 which results in 0 = s (3) Since the differentil gin is then d R 2 = R (4) R1 R = = = (5) d ( R R ) d R2 R = (6) To fcilitte the mesurement of high differentil gin, eqution (6) indictes tht we should set R 1 much greter thn R 2 nd then mesure 0 nd R s functions of frequency. Most opertionl mplifiers hve single dominnt pole so the differentil gin should show frequency dependence of the form d ( ω ) ( 0) d = (7) ω 1 j ω where ω 0 is the rdin frequency of the dominnt pole nd d (0) is the dc differentil gin. 0 3
4 Common Mode Rejection Rtio (CMRR) S 0 Figure 4  Circuit for mesuring common mode rejection rtio We will ssume tht d >> 1 nd tht d >> c. Under these ssumptions, it is strightforwrd to verify in the circuit of Figure 4 tht 0 S 0 = d ( S 0) C. (8) 2 Therefore, since d 0 >> 0 nd 0 S, it is esily shown tht CMRR = d c S = 0 S. (9) Since over most of its usble frequency rnge the common mode gin of n opmp is much less thn the differentil gin, 0 S will be much less thn S nd my be difficult to mesure with n oscilloscope. An AC voltmeter tht cn be isolted from circuit ground is more useful here for mesuring the vlue of 0  S. Also, to obtin redily mesurble vlue, it will be necessry to use rther lrge vlue for S. An input signl S = 20 pektopek is recommended so long s the output is distortion free. Slew Rte Slew rte determines the mximum frequency t which rted output cn be delivered without significnt distortion. It is esily mesured with the simple inverter circuit shown in Figure 5 by pplying squrewve input signl ( S ) nd exmining the output voltge ( 0 ) on n oscilloscope. Typiclly, the pplied S is lrge enough to drive the output between SAT nd SAT so tht the resulting o (t) looks s shown in Figure 6. R i R f S 0 Figure 5 Circuit for mesuring slew rte 4
5 o (t) SAT t SAT t Figure 6 Oscilloscope output voltge wveform for squre wve input From the oscilloscope wve form s in Figure 6, the Slew Rte (SR) is given by SR = (10) t The mximum time rte of chnge of signl tht cn be reproduced by n opmp is limited by the slew rte, so slew rte cn be used to determine the frequency rnge over which sine wve cn be mplified without serious distortion. For exmple, ssume tht the output voltge is given by The slope is v o ( t) sin ( 2πft) = (11) p dvo ( t) = 2πfp cos(2πft) (12) dt The mximum vlue of the slope occurs t time t=0, so nd dvo(0) = 2πfp (13) dt f mx = SR /(2π ) (14) p where f mx is the mximum frequency t which the opmp cn reproduce sine wve with pek vlue of p without serious distortion. 5
6 Offset oltge nd Bis Currents R 2  I d R 1 offset I c c o Figure 7 Circuit for mesuring dc offset voltge nd bis currents Offset oltge Mesurement To mesure the dc offset voltge ( offset ) of n opmp we set R 1 nd R 2, indicted in Figure 7, to zero, tht is, short circuits. Under these conditions so  = o nd = offset (15) nd, since d >>1>> c, then c 1 d 2 offset = (16) 0 c d 2 offset 0 (17) Therefore, from eqution (17) we see tht with the inverting input connected directly to the output nd the noninverting input connected to circuit common ground, the output will hve nonzero vlue which is the dc offset voltge. 6
7 I Bis Current Mesurement To mesure I of the opmp we set R 2 = 0 in Figure 7. The result is c c 0 1 d offset d 2 2 I = (18) c R1 d 2 Choosing R 1 reltively lrge, sy 1MΩ, nd gin ssuming tht d >>1>> c, we get: I 0 offset (19) R1 I  Bis Current Mesurement To mesure I  set R 1 to zero. In mnner similr to tht bove we find: I 0 offset (20) R2 Notice the difference in minus signs between equtions (19) nd (20). Experiment: Equipment List 1 Printed Circuit Bord with Two 741 Opertionl Amplifiers 1 Printed Circuit Bord Fixture 1 Screwdriver 1 Solderless Wiring Fixture Assorted Resistors Procedure The printed circuit bord with two 741 opertionl mplifiers should be mounted in the printed circuit bord fixture with the components of the bord on the sme side s the bnn plug jcks of the fixture. With the components fcing you, jck 1 will be on your fr left nd jck 22 on your fr right. Notice tht jcks 1, 4, 18, nd 22 hve BNC s well s bnn plug connectors. In this experiment the opertionl mplifier on the left is used for the open loop gin mesurements while the one on the right is used for ll subsequent mesurements. 7
8 1. Open Loop Gin Mesurement. Connect the circuit s indicted in Figure 8 using the lefthnd portion of the printed circuit bord. Notice tht ll resistors for this prt of the experiment re on the printed circuit bord. With zero volts cross the inputs, djust the 10k potentiometer to keep the mplifier t zero dc offset. Mesure the mgnitude nd phse of the input voltge t jck 9 nd the output voltge t jck 5 s function of frequency. Note tht from Eqution (6) d = / 9. Keep the output voltge s lrge s is prcticl without distortion (bout 20 pp ). Consider using the 10x Probe to observe R to keep from loding down this node. ry the frequency over the rnge from 1 Hz to 10 khz. Be sure to tke enough dt to observe ll interesting fetures, especilly in the 1 to 20 Hz rnge. Mke your mesurements s ccurtely s possible. You should be ble to get t lest two significnt digits even from n oscilloscope disply. Consider using the HP Digitl Multimeter (DMM) for to mesure R for better ccurcy. Function Genertor S R k 10 k 100 k k 1 O 5 Signl 15 Figure 8  Open Loop Gin Mesurement Circuit 2. Common Mode Rejection Rtio (CMRR). To mesure the common mode rejection rtio, construct the circuit of Figure 9. This employs the opertionl mplifier on the right hnd side of the bord. The CMRR depends strongly on the setting of the null djust potentiometer, so before tking dt, set the null djustment potentiometer for zero dc offset. Disply both the input signl ( 15 ) nd the output signl ( 17 ) on the oscilloscope. With the input signl ( 15 ) bout 20 pektopek nd the output signl ( 17 ) reltively free of distortion when observed on the scope, mesure the mgnitude nd phse of the output voltge 17 compred to the input voltge 15 over the frequency rnge from 5 Hz to 10 KHz. Use the HP DMM to get ccurte redings of ( ). Mesuring ech seprtely nd then tking the difference using the mth function on the scope does not work well! 8
9 22 15 Function Genertor S O Figure 9  Common Mode Rejection Rtio Mesurement Circuit 3. Slew Rte. Construct the inverting mplifier circuit shown in Figure 10. Note tht the 1k nd 10k resistors re externl. Apply squre wve of bout 1 pektopek t 10Hz to the input of the circuit. Mesure nd record the rise time of the input signl. With this input mesure nd record the output rise time nd voltge. Mesure the dely time between the input nd output t both the rising nd flling edges. Repet these mesurements t 100 Hz, 1 KHz, 10 KHz, 100 KHz nd 1 MHz. Is there ny chnge in slew rte or dely time with frequency? 10 k Function Genertor 1 k Figure 10  Slew Rte nd Overlod Recovery Mesurement Circuit. 9
10 4. Overlod Recovery Time. Use the previous circuit in Figure 10 nd pply 1 KHz squre wve. Slowly increse the mplitude until the output begins to sturte. Mke certin the mplifier hs sturted on both the positive nd negtive sides of the squre wve. You my hve to djust the DC offset of the function genertor to get the mplifier to sturte on both polrities. Wht is the input mplitude t sturtion? Wht re the sturted high nd low output voltges? Increse the input signl to twice the vlue required to sturte the output. Mesure the overlod recovery time (dely time) between the input nd output for both the rising nd flling edges. Repet this mesurement for 100 Hz, 1 KHz, 10 KHz nd 100 KHz. 5. Bis nd Offset Mesurements. Mesure the input offset voltge nd bis currents: With resistors 1 nd 2 equl to zero in the circuit of Figure 11 exmine nd record the vrition of the output voltge s the null djust potentiometer is chnged. Set the output voltge s close to zero s is possible nd do not chnge the potentiometer during the reminder of the experiment. With R 1 equl to 1 MΩ nd R 2 equl to zero, record the output voltge. Clculte I. With R 1 equl to zero nd R 2 equl to 1 MΩ, record the output voltge. Clculte I . R R Figure 11 Bis nd Offset Mesurement Circuit Report 1. Plot on single semilog grph the mgnitude of the differentil gin, in db, nd the phse, in degrees, s function of frequency. Wht is the brek frequency of the dominnt pole for this opertionl mplifier? Wht is the ginbndwidth product? Extrpolte the gin curve t high frequency to predict the unity gin bndwidth? Are the ginbndwidth product nd unity gin bndwidth vlues equl? How much uncertinty do you estimte for these mesurements? Are your mesured results within specifictions for this mplifier? 10
11 2. Plot on single semilog grph the mgnitude, in db, nd phse, in degrees, of the common mode rejection rtio (CMRR) s function of frequency. Does the pproximtion derived in clss for the common mode rejection rtio remin vlid over the entire frequency rnge? Clculte the CMRR t 60 Hz. Is your mesured CMRR within the published specifictions? 3. Exmine the slew rte dt you recorded. Present your vlues for slew rte nd discuss ny frequency dependence. Using the mesured vlues of slew rte, clculte the mximum frequency t which the opertionl mplifier cn develop 10 pek sine wve output. 4. Review the recovery time dt you recorded. Present your vlues for overlod recovery time nd discuss ny frequency dependence. 5. Review the offset voltge nd bis current dt you recorded. Over wht rnge could the offset voltge be chnged with the null djust potentiometer? Wht vlues did you obtin for the inverting nd noninverting bis currents? 6. Exmine the inverting mplifier circuit in Figure 12. Assume tht R 1 = 5 kω nd R 2 = 1 MΩ. Wht is its predicted low frequency gin? Bsed on the dt presented in prt 1 bove nd the low frequency gin of this mplifier, clculte the expected the 3 db bndwidth of this inverting mplifier. Assume tht the offset voltge nd bis currents re zero nd tht R 3 = 0. Wht useful function does R 3 serve in n inverter circuit? Wht should nonzero vlue of R 3 be? R 1 R 2 Input R 3 Figure 12  Hlf Power (3 db) Bndwidth Circuit References nd Suggested Reding 1. Adel S. Sedr nd Kenneth C. Smith, Microelectronic Circuits, 5 th Edition, (Oxford University Press, New York, 2004) 2. ictor H. Grinich nd Horce G. Jckson, Introduction to Integrted Circuits, (McGrw Hill, New York, 1975). 3. Gene E. Tobey, Jerld G. Greme, nd Lwrence P. Huelsmn, Opertionl Amplifiers: Design nd Applictions, (McGrwHill, New York, 1971),App. A nd B. 11
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